256K x 18 Synchronous-Pipelined Cache RAM
WCSS0418V1P
Document #: 38-05247
Revised February 6, 2001
Y7C1327
Features
Supports 100-MHz bus for Pentium
and PowerPCTM
operations with zero wait states
Fully registered inputs and outputs for pipelined
operation
256K by 18 common I/O architecture
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
-- 3.5 ns (for 166-MHz device)
-- 4.0 ns (for 133-MHz device)
-- 5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP pinout
"ZZ" Sleep Mode option and Stop Clock option
Functional Description
The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipe-
lined cache SRAM designed to support zero wait state sec-
ondary cache with minimal glue logic.
The WCSS0418V1P I/O pins can operate at either the 2.5V or
the 3.3V level. The I/O pins are 3.3V tolerant when V
D-
DQ
=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The WCSS0418V1P supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the four Byte Write
Select (BW
[1:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
A
[17:0]
GW
BWE
BW
1
BW
0
CE
1
CE
3
CE
2
OE
ZZ
BURST
COUNTER
ADDRESS
REGISTER
OUTPUT
REGISTERS
INPUT
REGISTERS
256KX18
MEMORY
ARRAY
CLK
CLK
Q
0
Q
1
Q
D
CE
CE
CLR
SLEEP
CONTROL
18
18
18
16
16
18
(A
[1;0]
)
2
MODE
ADSP
Logic Block Diagram
DQ
[15:0]
DP
[1:0]
DQ[15:8], DP[1]
BYTEWRITE
REGISTERS
D
Q
DQ[7:0], DP[0]
BYTEWRITE
REGISTERS
D
Q
ENABLE CE
REGISTER
D
Q
ENABLE DELAY
REGISTER
D
Q
CE
WCSS0418V1P
Document #: 38-05247
Page 2 of 17
Selection Guide
-166
-133
-100
Maximum Access Time (ns)
3.5
4.0
5.5
Maximum Operating Current (mA)
Commercial
420
375
325
Maximum CMOS Standby Current (mA)
Commercial
10
10
10
Pin Configurations
A
5
A
4
A
3
A
2
A
1
A
0
DN
U
DN
U
V
SS
V
DD
DN
U
A
11
A
12
A
13
A
14
A
15
A
17
A
10
NC
NC
V
DDQ
V
SS
NC
DP
0
DQ
7
DQ
6
V
SS
V
DDQ
DQ
5
DQ
4
V
SS
NC
V
DD
DQ
3
DQ
2
V
DDQ
V
SS
DQ
1
DQ
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
8
DQ
9
V
SS
V
DDQ
DQ
10
DQ
11
NC
V
DD
NC
V
SS
DQ
12
DQ
13
V
DDQ
V
SS
DQ
14
DQ
15
DP
1
NC
V
SS
V
DDQ
NC
NC
NC
A6
A7
CE
1
CE
2
NC
NC
BW
S
1
BW
S
0
CE
3
V
DD
V
SS
CLK
GW
BW
E
OE
AD
SP
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE0
BYTE1
A
16
AD
V
AD
S
C
ZZ
MO
D
E
DN
U
WCSS0418V1P
100-Lead TQFP
WCSS0418V1P
Document #: 38-05247
Page 3 of 17
Pin Configurations
(continued)
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
A
A
A
A
ADSP
V
DDQ
CE
2
A
NC
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
V
SS
NC
NC
NC
NC
A
A
NC
V
DDQ
V
DDQ
V
DDQ
A
NC
A
A
CE
3
A
A
A
A
A
A
A0
A1
DQ
a
DQ
b
NC
NC
DQ
a
NC
DQ
a
DQ
a
NC
NC
DQ
a
NC
DQ
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
DQP
b
DQP
a
V
ss
BW
b
NC
V
DD
NC
BW
a
NC
BWE
V
ss
ZZ
119-Ball BGA
A
Pin Definitions
Name
I/O
Description
A
[17:0]
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the
2-bit counter.
BW
[1:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[1:0]
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the device.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
WCSS0418V1P
Document #: 38-05247
Page 4 of 17
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz
device).
The WCSS0418V1P supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The in-
terleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize
a linear burst sequence. The burst order is user selectable,
and is determined by sampling the MODE input. Accesses can
be initiated with either the Processor Address Strobe (ADSP)
or the Controller Address Strobe (ADSC). Address advance-
ment through the burst sequence is controlled by the ADV in-
put. A two-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[1:0]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs (A
[17:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[17:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[1:0]
) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
[15:0]
and DP
[1:0]
inputs is written into
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[1:0]
signals. The WCSS0418V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
[1:0]
) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
is
captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition
with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
DQ
[15:0]
DP
[1:0]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
[1:0]
are placed
in a three-state condition.
V
DD
Power Supply Power Supply inputs to the core of the device. Should be connected to 3.3V power supply.
V
SS
Ground
Ground for the core of the device. Should be connected to ground of the system.
V
DDQ
I/O Power
Supply
Power Supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
V
SSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal
pull-up.
NC
No Connects.
Pin Definitions
(continued)
Name
I/O
Description
WCSS0418V1P
Document #: 38-05247
Page 5 of 17
Because the WCSS0418V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-
ing data to the DQ
[15:0]
and DP
[1:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[15:0]
and DP
[1:0]
are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
[1:0]
) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
[17:0]
is loaded into the address register and the address ad-
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ
[15:0]
and DP
[1:0]
is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the WCSS0418V1P is a common I/O device, the
Output Enable (OE) must be deasserted HIGH before present-
ing data to the DQ
[15:0]
and DP
[1:0]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ
[15:0]
and DP
[1:0]
are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The WCSS0418V1P provides a two-bit wraparound counter,
fed by A
[1:0]
, that implements either an interleaved or linear
burst sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow
a linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation "sleep" mode. Two clock
cycles are required to enter into or exit from this "sleep" mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the "sleep" mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the "sleep" mode.
CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain inactive for the
duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
A
[1:0]
A
[1:0]
A
[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A
[1:0]
A
[1:0]
A
[1:0]
A
[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
DDZZ
Snooze mode
standby current
ZZ > V
DD
-
0.2V
3
mA
t
ZZS
Device operation to
ZZ
ZZ > V
DD
-
0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ns
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