WT6016

Digital Monitor Controller

Ver. 1.51 Jul-31-1998

Weltrend Semiconductor, Inc.

GENERAL DESCRIPTION

The WT6016 is a member of WT60XX microcontroller family. It is specially designed for digital
controlled multi-sync monitor. It contains 8-bit CPU, 16K bytes ROM, 288 bytes RAM, 14 PWMs,
parallel I/O, SYNC processor, timer, one DDC interface (slave mode I

C interface with DDC1), one

master/slave I

C interface, two 4-bit A/D convertors and watch-dog timer.

FEATURES

* 8-bit 6502 compatible CPU, 4MHz operating frequency
* 16384 bytes ROM, 288 bytes SRAM
* 8MHz crystal oscillator
* 14 channels 8-bit/62.5kHz PWM outputs (8 open drain outputs & 6 CMOS outputs)
* Sync signal processor with H+V separation, frequency calculation, H/V polarity detection/control
* Three free-running sync signal outputs for burn-in test (64kHz/62.5Hz, 48kHz/75Hz, 31kHz/60Hz)
* Self-test pattern generator generates cross hatch picture
* DDC interface supports VESA DDC1/DDC2B standard
* Master/slave I

C interface

* Watch-dog timer (0.524 second)
* Maximum 25 programmable I/O pins
* One 8-bit programmable timer
* Two 4-bit A/D converter
* One external interrupt request
* Built-in low V

voltage reset

* +5V power supply

PIN ASSIGNMENT

I2C is a trademark of Philips Corporation.

DDC is a trademark of Video Electronics Standard Association (VESA).

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

GND

HSYNC

OSCI

OSCO

PA0/DA8

PA1/DA9

PA2/DA10

PA3/DA11

PA4/DA12

PA5/DA13

PA6/VSO

PA7/HSO

PB0/HLFO

PB1/HLFI

PB2

PB3/PAT

PB4/SCL2

PB5/SDA2

PB6/IRQ

PC0/AD0

PC1/AD1

PC2

PC3

PC4

PC5

PC6

PC7

SCL1/PD0

SDA1/PD1

VDD

VSYNC

RESET

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

GND

HSYNC

OSCI

OSCO

PA0/DA8

PA1/DA9

PA2/DA10

PA3/DA11

PA4/DA12

PA5/DA13

PA6/VSO

PA7/HSO

PB0/HLFO

PB1/HLFI

PB2

PB3/PAT

PB4/SCL2

PB5/SDA2

PB6/IRQ

PC0/AD0

PC1/AD1

PC2

PC3

PC4

PC5

PC6

PC7

SCL1/PD0

SDA1/PD1

VDD

VSYNC

RESET

42-Pin SDIP

40-Pin PDIP

WT6016

Digital Monitor Controller

Ver. 1.51 Jul-31-1998

Weltrend Semiconductor, Inc.

PIN DESCRIPTION

Pin No.

40 42

Pin Name

I/O

Descriptions

DA2

D/A converter 2. Open-drain output. External applied voltage can up to 10V.

DA1

D/A converter 1. Open-drain output. External applied voltage can up to 10V.

DA0

D/A converter 0. Open-drain output. External applied voltage can up to 10V.

/RESET

Reset. Active low. Schmitt trigger input with internal pull high.

VDD

Power supply (+5V).

GND

Ground (0V).

OSCO

Oscillator Output. Connects a 8MHz crystal.

OSCI

Oscillator Input. Connects a 8MHz crystal.

PB5/SDA2

I/O

I/O Port B5 or I

C data pin. This pin can be an I/O port or I

C serial data pin.

PB4/SCL2

I/O

I/O Port B4 or I

C clock pin. This pin can be I/O port or I

C clock pin.

PB3/PAT

I/O

I/O Port B3 or self-test pattern output. When as an I/O port, it is same as PB2.
When it is configured to test pattern output, a vedio signal is output.

PB2

I/O

I/O Port B2. When it is an input pin, it has an internal pull-up resistor. When it is
an output pin, the source/sink current is 5mA

PB1/HLFI

I/O

I/O Port B1 or half frequency input.

PB0/HLFO

I/O

I/O Port B0 or half frequency output.

PB6/IRQ

I/O

I/O Port B6 or Interrupt Request . When as interrupt request input, it has an
internal pull high resistor. When as an I/O port, it is same as PB3.

PC7

I/O

I/O Port C7. When it is an input pin, it has an internal pull-up resistor. When it is
an output pin, the sink current is 10mA and the source current is 5mA.

PC6

I/O

I/O Port C6. Same as PC7.

PC5

I/O

I/O Port C5. Same as PC7.

PC4

I/O

I/O Port C4. Same as PC7.

PC3

I/O

I/O Port C3. Same as PC7.

PC2

I/O

I/O Port C2. Same as PC7.

PC1/AD1

I/O

I/O Port C1 or A/D converter input 0.

PC0/AD0

I/O

I/O Port C0 or A/D converter input 1.

SDA1/PD1

I/O

DDC serial data or I/O Port D1. When it is a DDC interface pin, It is an open-
drain output. When as an I/O port, it is same as Port B.

SCL1/PD0

I/O

DDC serial clock or I/O Port D0. When it is a DDC interface pin, It is an open-
drain output. When as an I/O port, it is same as Port B.

PA0/DA8

I/O

I/O Port A0 or D/A converter 8. This pin can be the output of D/A converter 8
(source/sink = 5mA) or an I/O pin (source = -100uA, sink = 5mA).

PA1/DA9

I/O

I/O Port A1 or D/A converter 9. Same as PA0/DA8.

PA2/DA10

I/O

I/O Port A2 or D/A converter 10. Same as PA0/DA8.

PA3/DA11

I/O

I/O Port A3 or D/A converter 11. Same as PA0/DA8.

PA4/DA12

I/O

I/O Port A4 or D/A converter 12. Same as PA0/DA8.

PA5/DA13

I/O

I/O Port A5 or D/A converter 13. Same as PA0/DA8.

PA6/VSO

I/O

I/O Port A6 / VSYNC OUT. This pin can be the output of VSYNC or an I/O pin.
When as an I/O pin, it is same as PA0.

PA7/HSO

I/O

I/O Port A7 / HSYNC OUT. This pin can be the output of HSYNC or an I/O pin.
When as an I/O pin, it is same as PA0.

DA7

D/A converter 7. Open-drain output. External applied voltage can up to 10V.

DA6

D/A converter 6. Open-drain output. External applied voltage can up to 10V.

DA5

D/A converter 5. Open-drain output. External applied voltage can up to 10V.

DA4

D/A converter 4. Open-drain output. External applied voltage can up to 10V.

DA3

D/A converter 3. Open-drain output. External applied voltage can up to 10V.

HSYNC

HSYNC input. Schmitt trigger input.

VSYNC

VSYNC input. Schmitt trigger input.

WT6016

Digital Monitor Controller

Ver. 1.51 Jul-31-1998

Weltrend Semiconductor, Inc.

FUNCTIONAL DESCRIPTION

CPU

The CPU core is 6502 compatible, operating frequency is 4MHz. Address bus is 16-bit and data bus is
8-bit. the non-maskable interrupt (/NMI) of 6502 is changed to maskable interrupt and is defined as
the INT0. The interrupt request (/IRQ) of 6502 is defined as the INT1.
Default stack pointer is 01FFH.
Please refer the 6502 reference menu for more detail.

ROM

16384 bytes maskable ROM is provided for program codes.
Address is located from C000H to FFFFH.
The following addresses are reserved for special purpose :
FFFAH (low byte) and FFFBH (high byte) : INT0 interrupt vector.
FFFCH (low byte) and FFFDH (high byte) : program reset vector.
FFFEH (low byte) and FFFFH (high byte) : INT1 interrupt vector.

RAM

Built-in 288 bytes SRAM, address is located from 0080H to 019FH. Because the initial stack pointer
is 01FFH, so program must set proper stack pointer when program starts. A recommended value is
019FH.

0000H

0020H

REGISTERS

0021H

007FH

Reserved

0080H

019FH

RAM

01A0H

BFFFH

Reserved

C000H

:
:
:

FFFFH

ROM

Low VDD Voltage Reset

A VDD voltage detector is built inside the chip. When VDD is below 4.0 volts, the whole chip will be
reset just like power-on-reset.

Note that the 4.0 volts varies with temperature and process. Please refer the electrical characteristics.

WT6016

Digital Monitor Controller

Ver. 1.51 Jul-31-1998

Weltrend Semiconductor, Inc.

PWM D/A Converter

The WT6018 provides 14 PWM D/A converters. DA0 to DA7 are open-drain outputs and external
applied voltage on these pins can be up to 10 volts. DA8 to DA13 are 5 volts push-pull CMOS outputs
and are shared with I/O Port PA0 to PA5. All D/A converters are 62.5kHz frequency with 8-bit
resolution. Each D/A converter is controlled by the corresponding register (REG#00H to REG#0DH),
the duty cycle can be programmed from 1/256 (data = 01H) to 255/256 (data = FFH).

Duty cycle = 1/256
62.5ns

Duty cycle = 2/256
125ns

62.5ns
Duty cycle = 255/256
1/62.5kHz=16us

To program the PWM D/A converters, write the corresponding registers ( REG#00H to REG#0DH).

Address

R/W

Initial

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0000H

R/W

80H

DA0

0001H

R/W

80H

DA1

0002H

R/W

80H

DA2

0003H

R/W

80H

DA3

0004H

R/W

80H

DA4

0005H

R/W

80H

DA5

0006H

R/W

80H

DA6

0007H

R/W

80H

DA7

0008H

R/W

80H

DA8

0009H

R/W

80H

DA9

000AH

R/W

80H

DA10

000BH

R/W

80H

DA11

000CH

R/W

80H

DA12

000DH

R/W

80H

DA13

Bit Name

Bit value

DAx7-DAx0

01H : 1/256 duty cycle
02H : 2/256 duty cycle
03H : 3/256 duty cycle
:
FFH : 255/256 duty cycle

** Do not write 00H to the PWM registers. This will cause unstable
output on the corresponding pin.

WT6016

Digital Monitor Controller

Ver. 1.51 Jul-31-1998

Weltrend Semiconductor, Inc.

I/O Ports

Port_A :

Pin PA0/DA8 - general purpose I/O shared with DA8 output.
Pin PA1/DA9 - general purpose I/O shared with DA9 output.
Pin PA2/DA10 - general purpose I/O shared with DA10 output.
Pin PA3/DA11 - general purpose I/O shared with DA11 output.
Pin PA4/DA12 - general purpose I/O shared with DA12 output.
Pin PA5/DA13 - general purpose I/O shared with DA13 output.
Pin PA6/VSO - general purpose I/O shared with VSYNC output.
Pin PA7/HSO - general purpose I/O shared with HSYNC output.

Port_A is controlled by REG#10H & REG#11H. In REG#10H, each corresponding bit enables

HSYNC output, VSYNC output or D/A converter output when it is "1". If the corresponding bit is "0",
the output level is decided by REG#11H. In REG#11H, if the I/O corresponding bit (PAn) is "0", the
output is low level (I

=5mA). If PAn bit is "1", the output is high level (I

= -100uA) and can be

used as an input.

Address

R/W

Initial

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0010H

00H

EHO

EVO

EDA13 EDA12 EDA11 EDA10

EDA9

EDA8

0011H

FFH

PA7W

PA6W

PA5W

PA4W

PA3W

PA2W

PA1W

PA0W

0011H

PA7R

PA6R

PA5R

PA4R

PA3R

PA2R

PA1R

PA0R

Bit Name

Bit value = "1"

Bit value = "0"

EHO

Enable PA7 as HSYNC output.

PA7 as general purpose I/O.

EVO

Enable PA6 as VSYNC output.

PA6 as general purpose I/O.

EDA13

Enable PA5 as DA13 output.

PA5 as general purpose I/O.

EDA12

Enable PA4 as DA12 output.

PA4 as general purpose I/O.

EDA11

Enable PA3 as DA11 output.

PA3 as general purpose I/O.

EDA10

Enable PA2 as DA10 output.

PA2 as general purpose I/O.

EDA9

Enable PA1 as DA9 output.

PA1 as general purpose I/O.

EDA8

Enable PA0 as DA8 output.

PA0 as general purpose I/O.

PA7W - PA0W

Outputs high level (I

= -100uA).

Outputs low level (I

= 5mA).

PA7R- PA0R

Pin is high level.

Pin is low level.

* If the program wants to force VSYNC output (VSO pin) in low state, write "0" to PA6 bit first, then
write "0" to EVO bit. This is used to prevent high frequency output on VSO pin when the VSYNC
frequency is increased to read EDID data in DDC1 mode.

EDAx

DAx

PAnW

PAnR

Pin PAn

5mA

100uA

Электронный компонент: WT6016