NexFlash Technologies, Inc.
1
PRELIMINARY
NXSF018B-0600
06/22/00
FEATURES
Flash Storage for Resource-Limited Systems
Ideal for portable/mobile and microcontroller-based
applications that store voice, text, and data
0.35
NexFlash
Memory Technology
8M-bit, AND 16M-bit with 2048 and 4096 sectors
Small 536-byte sectors
Erase/Write time of 5 ms/sector (typical)
10K (Sector) / 100K (Block) write cycles
Optional 16KB (32 sector) block erase for faster
programming
Ultra-low Power for Battery-Operation
Single 5V or 3V supply for read and erase/write
1
A standby current, 5 mA active @ 3V (typical)
Low frequency read command for lower power
NX25F080B
NX25F160B
8M-BIT, AND 16M-bit SERIAL FLASH MEMORIES
WITH 4-PIN SPI INTERFACE
PRELIMINARY
JUNE 2000
4-pin SPI Serial Interface
Easily interfaces to popular microcontrollers
Clock operation as fast as 16 MHz
On-chip Serial SRAM
Dual independent 536-byte Read/Write SRAM buffers
Use in conjunction with or independent of Flash
Off-loads RAM-limited microcontrollers
Special Features for Media-Storage Applications
Byte-level addressing for reads and SRAM writes
Transfer or compare sector to SRAM
Versatile hardware and software write-protection
In-system electronic part number option
Removable Serial Flash Module package option
Auto verify for increased endurance
Serial Flash Development Kit
DESCRIPTION
The NX25F080B and NX25F160B Serial Flash memories
provide a storage solution for systems limited in power,
pins, space, hardware, and firmware resources. They are
ideal for applications that store voice, text, and data in a
portable or mobile environment. Using
NexFlash's patented
single transistor EEPROM cell, the devices offer a
high-density, low-voltage, low-power, and cost-effective
non-volatile memory solution. The devices operate on a
single 5V or 3V (2.7V-3.6V) supply for Read and
Erase/Write with typical current consumption as low as 5
mA active and less than 1
A standby. Sector erase/write
speeds as fast as 5 ms increase system performance,
minimize power-on time, and maximize battery life.
The NX25F080B and NX25F160B provide 8M-bit, and
16M-bit of flash memory organized as 2048 and 4096 sectors
of 536 bytes each. Each sector is individually addressable
through basic serial-clocked commands. The 4-pin SPI serial
interface works directly with popular microcontrollers. Special
features include: two on-chip serial SRAMs, byte-level
addressing, double-buffered sector writes, transfer/compare
sector to SRAM, hardware and software write protection,
alternate oscillator frequency, electronic part number, and
removable Serial Flash Module package option. Develop-
ment is supported with the PC-based SFK-SPI Serial
Flash Development Kit.
This document contains PRELIMINARY INFORMATION. NexFlash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication.
Copyright 1998, NexFlash Technologies, Inc.
2
NexFlash Technologies, Inc.
PRELIMINARY
NXSF018B-0600
06/22/00
NX25F080B
NX25F160B
FUNCTIONAL OVERVIEW
An architectural block diagram of the NX25F080B and
NX25F160B is shown in Figure 2. Key elements of the
architecture include:
SPI Interface and Command Set Logic
Serial Flash Memory Array
Serial SRAMs and Program Buffer
Write Protection Logic
Configuration and Status Registers
Device Information Sector
DEVICE INFORMATION SECTOR
(READ ONLY)
WRITE PR
O
TECT LOGIC
(16 BLOCKS OF 128 SECT
ORS EA
CH)
8/16 MEGABIT
SERIAL FLASH MEMORY ARRAY
2048/4096 BYTE-ADDRESSABLE
SECTORS OF 536 BYTES EACH
R
O
W DECODE (2048 OR 4096 SECT
ORS)
SRAM BUFFER 2 (536 BYTES)
4288
8
8
8
COLUMN DECODE, SENSE AMP LATCH
AND DATA COMPARE LOGIC
HIGH-VOLTAGE
GENERATORS
SECTOR-ADDRESS
LATCH
DATA
10
WRITE CONTROL
LOGIC
WP
HOLD OR
READ/BUSY
LOGIC
CONFIGURATION
REGISTER
STATUS
REGISTER
SPI
COMMAND
AND
CONTROL
LOGIC
BYTE-ADDRESS
LATCH/COUNTER
9
16
HOLD
OR R/
B
SCK
CS
SI
SO
SRAM BUFFER 1 (536 BYTES)
Figure 2. NX25F080B and NX25F160B Architectural Block Diagram
Pin Descriptions
Package
The NX25F080B and NX25F160B are available in a 28-pin
TSOP (Type I) surface mount package. See Figure 3 and
Table 1 for pin assignments. All interface and supply pins
are on one side of the TSOP package. The "No Connect"
(NC) pins are not connected to the device, allowing the pads
and the area around them to be used for routing PCB system
traces. The devices are also available in a cost-effective
and space-efficient removable Serial Flash Module
package.
NX25F080B
NX25F160B
NexFlash Technologies, Inc.
3
PRELIMINARY
NXSF018B-0600
06/22/00
1
2
3
4
5
6
7
8
9
10
11
12
Table 1. Pin Descriptions
SI
Serial Data Input
SO
Serial Data Output
SCK
Serial Clock Input
CS
Chip Select Input
WP
Write Protect Input
Hold, R/B
Hold Input or Read Busy Output
Vcc
Power Supply
Once deselected, the SO pin will enter a high-impedance
state and power consumption will decrease to standby levels
unless programming is in process, in which case standby will
resume when programming is complete.
Write Protect (
WP
WP
WP
WP
WP)
The Write Protect input (
WP) works in conjunction with the
write protect range set in the configuration register bits.
When
WP is asserted (active low) the entire Flash memory
array is write protected. When high, any Flash memory
sector can be written to unless its address is within the write
protect range that is set in the configuration register.
Hold or Ready/Busy (
HOLD
HOLD
HOLD
HOLD
HOLD or R/B
B
B
B
B)
This multifunction pin can serve either as a Hold input
(
HOLD) or as a Ready-Busy output (R/B). The pin function
is user-programmable through the non-volatile configuration
register. Factory-programmed as a no-connect, the pin can
be reconfigured as a Ready-Busy output or as a Hold input
by setting the configuration register. See the configuration
register section of this data sheet for further details.
Power Supply Pins (Vcc and GND)
The NX25F080B and NX25F160B support single power
supply Read and Erase/Write operations in 5V and 3V
versions. Typical active power is as low as 5 mA for the 3V
version with standby current less than 1 A.
Serial Data Input (SI)
The SPI bus Serial Data Input (SI) provides a means for data
to be written to (shifted into) the device.
Serial Data Output (SO)
The SPI bus Serial Data Output (SO) provides a means for
data to be read from (shifted out of) the device during a read
operation. When the device is deselected (
CS=1 or HOLD=0)
the SO pin is in a high-impedance state.
Serial Clock (SCK)
All commands and data written to the Serial Input (SI) are
clocked relative to the rising edge of the Serial Clock (SCK).
All data read from the Serial Data Output (SO) is clocked
relative to the falling or rising edge of SCK as specified in
the configuration register. The data output clock edge is
factory-programmed to the default condition of the falling
edge, allowing compatibility with standard SPI systems.
Clock rates of up to 16 MHz are supported.
Chip Select (
CS
CS
CS
CS
CS)
The NX25F080B and NX25F160B are selected for operation
when the Chip Select input (
CS) is asserted low. SCK must
be low when (
CS) is asserted to a low state. Upon power-up,
an initial low-to-high transition of
CS is required before any
command sequence will be acknowledged. The device can
be deselected to a non-active state when
CS is brought high.
Figure 3. NX25F080B and NX25F160B
Pin Assignments, 28-Pin TSOP (Type I)
HOLD-R/B
NC
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-PIN TSOP (Type I)
NX25F080B
NX25F160B
SPI Interface
4
NexFlash Technologies, Inc.
PRELIMINARY
NXSF018B-0600
06/22/00
NX25F080B
NX25F160B
Serial Flash Memory Array
The NX25F080B and NX25F160B Serial Flash memory
arrays are organized as 2048 and 4096 sectors of
536-bytes (4,288 bits) each, as shown in Figure 4.
The Serial Flash memory of the NX25F080B and NX25F160B
are byte-addressable for read operations. This allows a
single byte, or specified sequence of bytes, to be read
without having to clock an entire 536-byte sector out of the
device. Data can be read directly from a sector in the Flash
memory array by using a
Read from Sector command.
Data can be written to the Flash memory array one sector
(536-bytes) at a time through the Serial SRAM using a
Write
to Sector command or a Transfer SRAM to Sector com-
mand. After a sector has been written, the memory array
will become busy while it is programming the specified
non-volatile memory cells of that sector. This busy time will
not exceed t
WP
during which time the Flash array is
unavailable for read or write access. The device can be
tested to determine the array's availability using the
Ready/Busy status that is available during most read
commands, through the status register, or on the
Ready/Busy pin. Note that the SRAM is generally avail-
able, even when the memory array is busy. See the Serial
SRAM section for more details.
The NX25F080B and NX25F160B do not require pre-erase.
Instead, the device incorporates an auto-erase-before-write
feature that automatically erases the addressed sector at
the beginning of the write operation. Separate commands
for
Erase Sector, Erase Block (32 sectors), and Write
Sector Only are also available to improve performance for
applications that can accommodate pre-erase. An internal
auto-verify is performed after every erase and write com-
mand. The results of the auto-verify are available in the
status register. The status register EE and EW bits must
be checked to confirm proper erase or write operation.
Byte 0
000H
Sector 0
000H
IS25F080/160B
S[10:0] / S[11:0]
Sector Address:
Byte Address: B[9:0]
Sector 1
001H
Sector 2047/4095
7FFH/FFFH
Sector 2046/4094
7FEH/FFEH
Sector 3-2045/4093
003H-7FDH/FFDH
Byte1
001H
Byte1
001H
Byte 2-533
002H-215H
Byte 2-533
002H-215H
8M/16M-bit Serial Flash Memory Array
2048/4096 Byte-Addressable Sectors
of 536-Bytes each
Byte 534
216H
Byte 534
216H
Byte 535
217H
Byte 0
000H
Byte 535
217H
Byte 0
000H
Byte 0
000H
Byte 1
001H
Byte 1
001H
Byte 2-533
002H-215H
Byte 2-533
002H-215H
Byte 534
216H
Byte 534
216H
Byte 535
217H
Byte 535
217H
Figure 4. NX25F080B and NX25F160B Serial Flash Memory Array
NX25F080B
NX25F160B
NexFlash Technologies, Inc.
5
PRELIMINARY
NXSF018B-0600
06/22/00
1
2
3
4
5
6
7
8
9
10
11
12
Serial SRAM
One of the most powerful features of the NX25F080B and
NX25F160B are the dual Serial SRAMs. The main pur-
pose of the Serial SRAMs is to serve as the buffer for sector
data to be written into the Serial Flash memory array. Using
the
Write to Sector command, data is first shifted into the
SRAM from the SPI bus. When the command sequence has
been completed, the entire 536-bytes is written to the
selected sector. See Erase/Write cycle timing (t
WP
). While
the array is programming the second SRAM can be ac-
cessed to allow a continous stream of data to be transfered.
The SRAM is fully byte-addressable. Thus, the entire
536-bytes, a single byte, or a sequence of bytes can be read
from, or written to the SRAMs. This allows the SRAMs to
be used as a temporary work area for read-modify-write
operations prior to a sector write.
The
Transfer Sector to SRAM command allows the con-
tents of a specified sector of Flash memory to be moved to
the SRAM. This can be useful when only a portion of a sector
needs to be altered. In this case the sector is first transferred
to the SRAM, where modifications are made using the
Write
to SRAM command. Once complete, a Transfer SRAM to
Sector command is used to update the sector.
The
Compare Sector command allows the contents of the
SRAM to be compared with the specified sector in memory.
The result of the compare is set in the status register. This
command can be useful when re-writing multi-sector files
that have only minor changes from the previous write. If the
new data in the SRAM is the same as the previously written
data, the sector write can be skipped. Used in this way, the
command saves time that would have been used for
re-programming. It also extends the endurance of the Flash
memory cells.
SPI
COMMAND
AND
CONTROL
LOGIC
SCK
CS
SI
SO
STATUS
REGISTER
CONFIGURATION
REGISTER
COMPARE SECTOR
TO SRAM
READ FROM
DEVICE INFORMATION
SECTOR
Note:
1.
A single byte, several bytes, or all bytes of a Flash sector, the SRAM, or Program Buffer may be addressed.
2.
All double lines represent implied connections or actions.
SERIAL FLASH MEMORY ARRAY
512, 1024 AND 2048 BYTE-ADDRESSABLE
SECTORS OF 264-BYTES EACH
DEVICE INFORMATION SECTOR
WRITE TO SECTOR
(VIA SRAM)
SERIAL SRAM 1
SERIAL SRAM 2
READ FROM
OR WRITE TO
SRAM
TRANSFER
SECTOR TO
SRAM
READ FROM
SECTOR
Figure 5. Command Relationships of the SPI Interface, Serial Flash Memory Array and SRAM
PDF 
ZIP