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W241024A
128K
8 HIGH SPEED CMOS STATIC RAM
Publication Release Date: July 1998
- 1 -
Revision A9
GENERAL DESCRIPTION
The W241024A is a high speed, low power CMOS static RAM organized as 131072
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
High speed access time: 12/15/20 nS (max.)
Low power consumption:
-
Active: 600 mW (typ.)
Single +5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 32-pin 300 mil SOJ, 400
mil SOJ, skinny DIP and standard type one
TSOP (8 mm
20 mm), and small type one
TSOP (8 mm
13.4 mm)
PIN CONFIGURATIONS
V
A8
A9
WE
1
2
3
4
5
2 4
2 5
2 6
2 7
2 8
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
2 0
2 1
2 2
2 3
A11
OE
A1 0
CS1
I/O 8
I/O 7
I/O 6
I/O 5
1 0
1 1
1 2
1 3
16
1 7
1 8
1 9
A0
I/O 2
I/O 3
I/O 1
1 4
15
I/O 4
A13
V
A14
A16
32
31
30
29
A15
CS2
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
DQ3
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O8
A15
A12
A7
A6
A5
A4
V
CS2
WE
A13
A8
DD
A11
A9
NC
A14
A16
V
SS
DQ2
DQ1
BLOCK DIAGRAM
A0
.
CS1
A16
WE
I/O1
I/O8
OE
V
V
.
.
DATA I/O
ARRAY
DECODER
CORE
CS2
.
CONTROL
DD
SS
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A16
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS1, CS2
Chip Select Inputs
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
NC
No Connection
W241024A
- 2 -
TRUTH TABLE
CS1
CS2
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H
X
X
X
Not Selected
High Z
I
SB
, I
SB1
X
L
X
X
Not Selected
High Z
I
SB
, I
SB1
L
H
H
H
Output Disable
High Z
I
DD
L
H
L
H
Read
Data Out
I
DD
L
H
X
L
Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to +70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.2
-
V
DD
+0.5
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-10
-
+10
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD
CS1
=
V
IH
(min.)
or CS2 = V
IL
(max.)
or OE = V
IH
(min.)
or WE = V
IL
(max.)
-10
-
+10
A
Output Low Voltage
V
OL
I
OL
= +8.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0 mA
2.4
-
-
V
Operating Power
Supply Current
I
DD
CS1 = V
IL
(max.), and
CS2 = V
IH
(min.)
12
-
-
200
mA
I/O = 0 mA, Cycle = min.
15
-
-
200
mA
Duty = 100%
20
-
-
170
mA
Standby Power
Supply Current
I
SB
CS1 = V
IH
(min.),
or CS2 = V
IL
(max.) Cycle = min.
-
-
30
mA
I
SB1
CS1
V
DD
-0.2V or
-
-
10
mA
CS2
0.2V
Note: Typical characteristics are at V
DD
= 5V, T
A
= 25
C.
W241024A
Publication Release Date: July 1998
- 3 -
Revision A9
CAPACITANCE
(V
DD
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
10
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
AC Test Loads and Waveform
90%
90%
5 nS
10%
5 nS
10%
R1 480 ohm
5V
OUTPUT
R2
255 ohm
30 pF
Including
Jig and
Scope
3.0V
0V
5V
OUTPUT
R1 480 ohm
5pF
Including
Jig and
Scope
R2
255 ohm
(For T
CLZ1,
CLZ2,
OLZ,
CHZ1,
CHZ2,
OHZ,
WHZ,
OW
T
T
T
T
T
T
T
)
W241024A
- 4 -
AC Characteristics, continued
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
Read Cycle
PARAMETER
SYM.
W241024A-12
W241024A-15
W241024A-20
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
12
-
15
-
20
-
nS
Address Access Time
T
AA
-
12
-
15
-
20
nS
Chip Select Access Time
CS1
T
ACS1
-
12
-
15
-
20
nS
CS2
T
ACS2
-
12
-
15
-
20
nS
Output Enable to Output Valid
T
AOE
-
6
-
7
-
10
nS
Chip Selection to Output in Low Z
CS1
T
CLZ1
*
3
-
3
-
3
-
nS
CS2
T
CLZ2
*
3
-
3
-
3
-
nS
Output Enable to Output in Low Z
T
OLZ
*
0
-
0
-
0
-
nS
Chip Deselection to Output in
CS1
T
CHZ1
*
-
6
-
7
-
10
nS
High Z
CS2
T
CHZ2
*
-
6
-
7
-
10
nS
Output Disable to Output in High Z
T
OHZ
*
-
6
-
7
-
10
nS
Output Hold from Address Change
T
OH
3
-
3
-
3
-
nS
*
These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W241024A-12
W241024A-15
W241024A-20
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
T
WC
12
-
15
-
20
-
nS
Chip Selection to End of Write
CS1
T
CW1
10
-
13
-
17
-
nS
CS2
T
CW2
10
-
13
-
17
-
nS
Address Valid to End of Write
T
AW
10
-
13
-
17
-
nS
Address Setup Time
T
AS
0
-
0
-
0
-
nS
Write Pulse Width
T
WP
10
-
10
-
12
-
nS
Write Recovery Time
CS1
, WE
T
WR1
0
-
0
-
0
-
nS
CS2
T
WR2
0
-
0
-
0
-
nS
Data Valid to End of Write
T
DW
7
-
9
-
10
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
7
-
8
-
10
nS
Output Disable to Output in High Z
T
OHZ
*
-
7
-
8
-
10
nS
Output Active from End of Write
T
OW
0
-
0
-
0
-
nS
*
These parameters are sampled but not 100% tested.
W241024A
Publication Release Date: July 1998
- 5 -
Revision A9
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
T
T
T
D
OH
AA
RC
OH
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D
T
T
T
T
T
T
ACS1
ACS2
CLZ1
CLZ2
CHZ1
CHZ2
OUT
Read Cycle 3
(Output Enable Controlled)
Address
T
OE
CS1
CS2
D
T
T
T
T
T
T
T
T
T
T
T
OH
CHZ1
CHZ2
OHZ
AA
RC
AOE
CLZ1
ACS1
ACS2
CLZ2
OLZ
OUT