W24129A
16K
8 HIGH-SPEED CMOS STATIC RAM
Publication Release Date: July 1995
- 1 -
Revision A2
GENERAL DESCRIPTION
The W24129A is a high-speed, low-power CMOS static RAM organized as 16384
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
High-speed access time: 12/15 nS (max.)
Low-power consumption:
-
Active: 400 mW (typ.)
Single
+
5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 28-pin 300 mil SOJ and
skinny DIP
PIN CONFIGURATION
A8
A9
1
2
3
4
5
24
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
A10
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16
17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
A13
CS
OE
WE
V
DD
V
SS
BLOCK DIAGRAM
A0
.
.
CS
A13
WE
I/O1
I/O8
OE
ARRAY
V
DD
V
SS
.
.
DATA I/O
DECODER
CONTROL
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A13
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
W24129A
- 2 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to +70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
TRUTH TABLE
CS
OE
WE
MODE
I/O1-I/O8
V
DD
CURRENT
H
X
X
Not Selected
High Z
I
SB
,I
SB1
L
H
H
Output Disable
High Z
I
DD
L
L
H
Read
Data Out
I
DD
L
X
L
Write
Data In
I
DD
OPERATING CHARACTERISTICS
(V
DD
= 5V
5%, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.2
-
V
DD
+0.5
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-10
-
+10
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD,
CS = V
IH
or OE = V
IH
or WE = V
IL
-10
-
+10
A
Output Low Voltage
V
OL
I
OL
= +8.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0 mA
2.4
-
-
V
Operating Power
I
DD
CS = V
IL,
I/O = 0 mA
12
-
-
160
mA
Supply Current
Cycle = MIN
15
-
-
150
mA
Standby Power
Supply Current
I
SB
CS = V
IH
Cycle = MIN, Duty = 100%
-
-
30
mA
I
SB1
CS
V
DD
-0.2V
-
-
5
mA
Note: Typical characteristics are at V
DD
= 5V, T
A
= 25
C.
W24129A
Publication Release Date: July 1995
- 3 -
Revision A2
CAPACITANCE
(V
DD
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
10
pF
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
AC TEST LOADS AND WAVEFORM
90%
90%
5 nS
10%
5 nS
10%
R1 480 ohm
5V
OUTPUT
R2
255 ohm
5 pF
R2
255 ohm
R1 480 ohm
5V
OUTPUT
30 pF
Including
Jig and
Scope
3.0V
0V
Including
Jig and
Scope
)
(For T
CLZ
,
,
,
,
,
T
OLZ
T
CHZ
T
OHZ
T
WHZ
T
OW
W24129A
- 4 -
AC CHARACTERISTICS
(V
DD
= 5V
5%, V
SS
= 0V, T
A
= 0 to 70
C)
Read Cycle
PARAMETER
SYM.
W24129A-12
W24129A-15
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
12
-
15
-
nS
Address Access Time
T
AA
-
12
-
15
nS
Chip Select Access Time
T
ACS
-
12
-
15
nS
Output Enable to Output Valid
T
AOE
-
6
-
7
nS
Chip Selection to Output in Low Z
T
CLZ
3
-
3
-
nS
Output Enable to Output in Low Z
T
OLZ
0
-
0
-
nS
Chip Deselection to Output in High Z
T
CHZ
-
6
-
7
nS
Output Disable to Output in High Z
T
OHZ
-
6
-
7
nS
Output Hold from Address Change
T
OH
3
-
3
-
nS
These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W24129A-12
W24129A-15
UNIT
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
T
WC
12
-
15
-
nS
Chip Selection to End of Write
T
CW
10
-
13
-
nS
Address Valid to End of Write
T
AW
10
-
13
-
nS
Address Setup Time
T
AS
0
-
0
-
nS
Write Pulse Width
T
WP
10
-
10
-
nS
Write Recovery Time
CS, WE
T
WR
0
-
0
-
nS
Data Valid to End of Write
T
DW
7
-
9
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
nS
Write to Output in High Z
T
WHZ
-
7
-
8
nS
Output Disable to Output in High Z
T
OHZ
-
7
-
8
nS
Output Active from End of Write
T
OW
0
-
0
-
nS
These parameters are sampled but not 100% tested.
W24129A
Publication Release Date: July 1995
- 5 -
Revision A2
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS
D
OUT
T
CLZ
T
ACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS
D
OUT
T
AA
OE
T
AOE
T
OLZ
T
OH
CLZ
T
CHZ
T
T
ACS
T
OHZ
PDF 
ZIP