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Электронный компонент: W24257S-70L

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W24257
32K
8 CMOS STATIC RAM
Publication Release Date: May 2000
- 1 -
Revision A14
GENERAL DESCRIPTION
The W24257 is a slow speed, low power CMOS static RAM organized as 32768
8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.
FEATURES
Low power consumption:
-
Active: 325 mW (max.)
-
Standby: 75
W (max.) (LL-version)
150
W (max.) (L-version)
Access time: 70 nS (max.)
Single
+5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 28-pin 330 mil SOP,
standard type one TSOP (8 mm x 13.4 mm )
PIN CONFIGURATION
25
26
27
28
20
21
22
23
16
17
18
19
15
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
A13
CS
OE
WE
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A7
A6
A5
A12
A4
A3
A2
A1
A0
I/O2
I/O3
I/O1
V
SS
24
BLOCK DIAGRAM
A0
.
.
CS
A14
WE
I/O1
I/O8
OE
V
DD
V
SS
.
.
DATA I/O
DECODER
CONTROL
CORE
ARRAY
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0
-A14
Address Inputs
I/O1
-I/O8
Data Inputs/Outputs
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
W24257
- 2 -
TRUTH TABLE
CS
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H X X
Not
Selected
High
Z
I
SB
, I
SB
1
L
H
H
Output Disable
High Z
I
DD
L L H
Read
Data
Out
I
DD
L X L
Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to +70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER SYM.
TEST CONDITIONS
MIN. TYP.
MAX.
UNIT
Input Low Voltage
V
IL
- -0.5
-
+0.8
V
Input High Voltage
V
IH
- +2.2
-
V
DD
+0.5 V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-2 - +2
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD,
CS = V
IH
(min.) or OE = V
IH
(min.) or
WE = V
IL
(max.)
-2 - +
2
A
Output Low Voltage
V
OL
I
OL
= +4.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0 mA
2.4
-
-
V
Operating Power
Supply Current
I
DD
CS = V
IL
(min.),
I/O = 0 mA Cycle = min.,
Duty = 100%
- - 65 mA
Standby Power
Supply Current
I
SB
CS = V
IH
(min.)
Cycle = min., Duty = 100%
- - 3 mA
I
SB1
CS
V
DD
-0.2V
LL - -
15
A
L
-
-
30
A
Note: Typical characteristics are at V
DD
= 5V, T
A
= 25
C.
W24257
Publication Release Date: May 2000
- 3 -
Revision A14
CAPACITANCE
(V
DD
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 100 pF, I
OH
/I
OL
= -1 mA/4 mA
AC Test Loads and Waveform
90%
90%
5 nS
10%
5 nS
10%
R1 1000 ohm
5V
OUTPUT
R2
660 ohm
5 pF
R2
660 ohm
R1 1000 ohm
5V
OUTPUT
100 pF
Including
Jig and
Scope
3.0V
0V
Including
Jig and
Scope
)
(For T
CLZ
,
,
,
,
,
T
OLZ
T
CHZ
T
OHZ
T
WHZ
T
OW
W24257
- 4 -
AC Characteristics, continued
(V
DD
= 5V
10%, V
SS
= 0V, T
A
= 0 to 70
C)
Read Cycle
PARAMETER SYMBOL
W24257-70
UNIT
MIN.
MAX.
Read Cycle Time
T
RC
70 - nS
Address Access Time
T
AA
- 70
nS
Chip Select Access Time
T
ACS
- 70
nS
Output Enable to Output Valid
T
AOE
- 35
nS
Chip Selection to Output in Low Z
T
CLZ
* 10
- nS
Output Enable to Output in Low Z
T
OLZ
* 5
- nS
Chip Deselection to Output in High Z
T
CHZ
* - 30 nS
Output Disable to Output in High Z
T
OHZ
* - 30 nS
Output Hold from Address Change
T
OH
10 - nS
These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYMBOL
W24257-70
UNIT
MIN.
MAX.
Write Cycle Time
T
WC
70 - nS
Chip Selection to End of Write
T
CW
60 - nS
Address Valid to End of Write
T
AW
60 - nS
Address Setup Time
T
AS
0 -
nS
Write Pulse Width
T
WP
45 - nS
Write Recovery Time
CS, WE
T
WR
0 -
nS
Data Valid to End of Write
T
DW
30 - nS
Data Hold from End of Write
T
DH
0 -
nS
Write to Output in High Z
T
WHZ
* -
30 nS
Output Disable to Output in High Z
T
OHZ
* - 30 nS
Output Active from End of Write
T
OW
0 -
nS
These parameters are sampled but not 100% tested
W24257
Publication Release Date: May 2000
- 5 -
Revision A14
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS
D
OUT
T
CLZ
T
ACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS
D
OUT
T
AA
OE
T
AOE
T
OLZ
T
OH
CLZ
T
CHZ
T
T
ACS
T
OHZ