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Электронный компонент: W24L01Q-70LE

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W24L01
128K
8 CMOS STATIC RAM
Publication Release Date: January 2, 2002
- 1 - Revision A6
GENERAL DESCRIPTION
The W24L01 is a normal-speed, very low-power CMOS static RAM organized as 131072
8 bits that
operates on a wide voltage range from 2.7V to 3.6V power supply. The W24L01 family, W24L01-LE
and W24L01-LI, can meet the requirement of various operating temperature. This device is
manufactured using Winbond's high performance CMOS technology.
FEATURES
Low power consumption
Access time: 55 nS /70 nS
2.7V to 3.6V supply voltage
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 1.5V (min.)
Packaged in 32-pin 450 mil SOP, standard type
one TSOP (8 mm
20 mm), small type one

TSOP (8 mm
13.4 mm) and 48-pin CSP
PIN CONFIGURATIONS
BLOCK DIAGRAM
48-pin CSP TOP VIEW
1
2
3
4
5
6
A
A0
A1
CS2
A3
A6
A8
B
I/O5
A2
WE
A4
A7
I/O1
C
I/O6
NC
A5
I/O2
D
V
SS
V
CC
E
V
CC
V
SS
F
I/O7
NC
NC
I/O3
G
I/O8
OE
CS1
A16
A15
I/O4
H
A9
A10
A11
A12
A13
A14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
SOP
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
I/O4
I/O5
I/O6
I/O7
I/O8
CS
1
A10
OE
A1
1
A9
A
8
A1
3
WE
CS2
A1
5
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O8
A15
A12
A7
A6
A5
A4
V
CS2
WE
A13
A8
DD
A11
A9
A14
A16
V
SS
I/O3
I/O2
I/O1
NC
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A15
I/O CKT.
COLUMN DECODER
WE
OE
CLK GEN.
PRECHARGE CKT.
A13 A8 A1A0 A11A10
CS1
CS2
A16
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
I/O8
:
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A16
Address Inputs
I/O1
-
I/O8 Data Inputs/Outputs
CS
, CS2
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
NC
No Connection
W24L01
- 2 -
TRUTH TABLE
CS1
CS2
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H
X
X
X
Not Selected
High Z
I
SB
, I
SB
1
X
L
X
X
Not Selected
High Z
I
SB
, I
SB
1
L
H
H
H
Output Disable
High Z
I
DD
L
H
L
H
Read
Data Out
I
DD
L
H
X
L
Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +4.6
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
LL
0 to 70
LE
-20 to 85
Operating Temperature
LI
-40 to 85
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
SS
= 0V; T
A
(
C) = 0 to 70 for LL, -20 to 85 for LE, -40 to 85 for LI)
W24L01
UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP.*
MAX.
Input Low Voltage
V
IL
-
-0.2
-
+0.4
V
Input High Voltage
V
IH
-
+2.2
-
V
DD
+0.3
V
Input Leakage
Current
I
LI
V
IN
= V
SS
to V
DD
-1
-
+1
A
Output Leakage
Current
I
LO
VI/O = V
SS
to V
DD
,
CS1
= V
IH
(min.) or CS2 = V
IL
(max.) or
OE
= V
IH
(min.) or
WE
= V
IL
(max.)
-1
-
+1
A
Output Low Voltage
V
OL
I
OL
= +2.1 mA
-
-
0.4
V
Output Low Voltage
V
OH
IOH = -1.0 mA
2.2
-
-
V
W24L01
Publication Release Date: January 2, 2002
- 3 - Revision A6
Operating Characteristics, continued
W24L01
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.*
MAX.
UNIT
Operating Power
Supply Current
I
DD
CS1 = V
IL
(max.) and CS2 = V
IH
(min.) , I/O = 0 mA,
Cycle = min. Duty = 100%
-
25 (3V)
30 (3.3V)
40 (70 nS)
55 (55 nS)
mA
I
SB
CS1 = V
IH
(min.) or CS2 = V
IL
(max.), Cycle = min.
Duty = 100%
-
-
0.3
mA
LL
5
Standby Power
Supply Current
I
SB1
CS1
V
DD
-0.2V or
CS2
0.2V
LE/LI
-
2
7
A
Note: Typical parameter is measured under ambient temperature T
A
= 25
C
CAPACITANCE
(T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
8
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
10
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 2.2V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V, V
DD
= 3.0V
Output Load
See the drawing below
AC Test Loads and Waveform
90%
90%
5 nS
10%
5 nS
10%
OUTPUT
OUTPUT
2.2V
0V
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL
1 TTL
CLZ,
OLZ,
CHZ, OHZ,
WHZ, OW
(For T
T
T
T
T
T
)
W24L01
- 4 -
AC Characteristics, continued
(V
SS
= 0V; T
A
(
C) = 0 to 70 for LL, -20 to 85 for LE, -40 to 85 for LI)
Read Cycle
PARAMETER
SYM. MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
T
RC
55
-
70
-
nS
Address Access Time
T
AA
-
55
-
70
nS
Chip Select Access Time
T
ACS
-
55
-
70
nS
Output Enable to Output Valid
T
AOE
-
30
-
35
nS
Chip Selection to Output in Low Z
T
CLZ
*
10
-
10
-
nS
Output Enable to Output in Low Z
T
OLZ
*
5
-
5
-
nS
Chip Deselection to Output in High Z
T
CHZ
*
-
25
-
30
nS
Output Disable to Output in High Z
T
OHZ
*
-
25
-
30
nS
Output Hold from Address Change
T
OH
5
-
10
-
nS
These parameters are sampled but not 100% tested
Write Cycle
PARAMETER
SYM. MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
T
WC
55
-
70
-
nS
Chip Selection to End of Write
T
CW
50
-
60
-
nS
Address Valid to End of Write
T
AW
50
-
60
-
nS
Address Setup Time
T
AS
0
-
0
-
nS
Write Pulse Width
T
WP
40
-
55
-
nS
Write Recovery Time
CS1
, CS2, WE
T
WR
0
-
0
-
nS
Data Valid to End of Write
T
DW
30
-
30
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
20
-
25
nS
Output Disable to Output in High Z
T
OHZ
*
-
20
-
25
nS
Output Active from End of Write
T
OW
5
-
5
-
nS
These parameters are sampled but not 100% tested
W24L01
Publication Release Date: January 2, 2002
- 5 - Revision A6
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
D
OUT
CS1
T
CLZ
T
ACS
CHZ
T
CS2
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS1
T
AA
OE
T
AOE
T
OLZ
T
OH
T
ACS
D
OUT
CLZ
T
CHZ
T
T
OHZ
CS2