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Электронный компонент: W24L11STQ

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Preliminary W24L11
128K
8 CMOS STATIC RAM
Publication Release Date: October 1999
- 1 -
Revision A1
GENERAL DESCRIPTION
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072
8 bits that
operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using
Winbond's high performance CMOS technology.
FEATURES
Low power consumption:
-
Active: 144 mW (max.)
Access time: 70 nS
Single 3.3V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 600 mil DIP, 450 mil SOP,
standard type one, TSOP (8 mm
20 mm) ,
small type one and TSOP (8 mm
13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
A8
A9
WE
1
2
3
4
5
24
25
26
27
28
NC
A7
A6
A5
A12
A4
A3
A2
A1
6
7
8
9
20
21
22
23
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
10
11
12
13
16
17
18
19
A0
I/O2
I/O3
I/O1
14
15
I/O4
A13
V
A14
A16
32
31
30
29
A15
CS2
DD
SS
1
32-pin
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O8
A15
A12
A7
A6
A5
A4
V
CS2
WE
A13
A8
DD
A11
A9
NC
A14
A16
V
SS
WE
OE
PRECHARGE CKT.
A13
A1 A0
A10
CS1
A16
A14
A4
A3
A7
A6
A9
I/O1
:
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0
-
A16
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS1, CS2
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power
Supply
V
SS
Ground
NC No
Connection
Preliminary W24L11
- 2 -
TRUTH TABLE
CS1
CS2
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H X X X Not
Selected
High
Z
I
SB
, I
SB1
X L X X Not
Selected
High
Z
I
SB
, I
SB1
L H H H Output
Disable
High
Z
I
DD
L H L H Read
Data
Out
I
DD
L H X L Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +4.6
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to 70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 3.0V to 3.6V; V
SS
= 0V; T
A
(
C) = 0 to 70)
PARAMETER SYM.
TEST CONDITIONS
MIN. MAX. UNIT
Input Low Voltage
V
IL
- -0.5
+0.6
V
Input High Voltage
V
IH
- +2.0
V
DD
+0.5
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-1
+1
A
Output Leakage Current
I
LO
VI/O = V
SS
to V
DD
,
CS1
= V
IH
(min.) or
CS2 = V
IL
(max.) or
OE = V
IH
(min.) or
WE
= V
IL
(max.)
-1
+1
A
Output Low Voltage
V
OL
I
OL
= +2.1 mA
-
0.4
V
Output High Voltage
V
OH
I
OH
= -1.0 mA
2.2
-
V
Operating Power Supply
Current
I
DD
CS1 = V
IL
(max.) and
CS2 = V
IH
(min.), I/O = 0 mA,
Cycle = min. Duty = 100%
-
40
mA
Preliminary W24L11
Publication Release Date: October 1999
- 3 -
Revision A1
Operating Characteristics, continued
PARAMETER SYM.
TEST CONDITIONS
MIN. MAX. UNIT
Standby Power Supply
Current
I
SB
CS1 = V
IH
(min.) or
CS2 = V
IL
(max.)
Cycle = min. Duty = 100%
-
1
mA
I
SB1
CS1
V
DD
-0.2V or
LL - 50
A
CS2
0.2V
L -
100
Note: Typical parameter is measured under ambient temperature T
A
= 25
C and V
DD
= 3.3V
CAPACITANCE
(V
DD
= 3.3 V, T
A
= 25
C, f = 1 MHz)
PARAMETER SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC characteristics
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V
Output Load
See the drawing below
AC Test Loads and Waveform
90%
90%
5 nS
10%
5 nS
10%
OUTPUT
OUTPUT
3.0 V
0 V
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL
1 TTL
CLZ,
OLZ,
CHZ, OHZ,
WHZ, OW
(For T
T
T
T
T
T
)
Preliminary W24L11
- 4 -
AC Characteristics, continued
(V
DD
= 3.0V to 3.6 V; V
SS
= 0V; T
A
(
C) = 0 to 70)
Read Cycle
PARAMETER SYMBOL
W24L11-70L/LL
UNIT
MIN.
MAX.
Read Cycle Time
T
RC
70
-
nS
Address Access Time
T
AA
-
70
nS
Chip Select Access Time
T
ACS
-
70
nS
Output Enable to Output Valid
T
AOE
-
35
nS
Chip Selection to Output in Low Z
T
CLZ
* 10
-
nS
Output Enable to Output in Low Z
T
OLZ
* 5
-
nS
Chip Deselection to Output in High Z
T
CHZ
* -
30
nS
Output Disable to Output in High Z
T
OHZ
* -
30
nS
Output Hold from Address Change
T
OH
10
-
nS
These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYMBOL
W24L11-70L/LL
UNIT
MIN.
MAX.
Write Cycle Time
T
WC
70
-
nS
Chip Selection to End of Write
T
CW
55
-
nS
Address Valid to End of Write
T
AW
55
-
nS
Address Setup Time
T
AS
0
-
nS
Write Pulse Width
T
WP
50
-
nS
Write Recovery Time
CS1
, CS2, WE
T
WR
0
-
nS
Data Valid to End of Write
T
DW
45
-
nS
Data Hold from End of Write
T
DH
0
-
nS
Write to Output in High Z
T
WHZ
* -
25
nS
Output Disable to Output in High Z
T
OHZ
* -
25
nS
Output Active from End of Write
T
OW
5
-
nS
These parameters are sampled but not 100% tested
Preliminary W24L11
Publication Release Date: October 1999
- 5 -
Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
D
OUT
CS1
T
CLZ
T
ACS
CHZ
T
CS2
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS1
T
AA
OE
T
AOE
T
OLZ
T
OH
T
ACS
D
OUT
CLZ
T
CHZ
T
T
OHZ
CS2
Preliminary W24L11
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
T
WC
T
WR
WE
D
OUT
D
IN
T
WP
T
AS
T
OHZ
(1, 4)
T
DW
T
DH
T
AW
CS1
T
CW
CS2
Write Cycle 2
(OE = V
IL
Fixed)
WE
D
OUT
D
IN
T
AS
T
DH
T
WP
T
WHZ
DW
T
(2)
(3)
T
OW
T
OH
AW
T
(1, 4)
T
CW
T
WR
Address
T
WC
CS1
CS2
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from D
OUT
are the same as the data written to D
IN
during the write cycle.
3. D
OUT
provides the read data for the next address.
4. Transition is measured
500 mV from steady state with C
L
= 5 pF. This parameter is guaranteed but not 100% tested.
Preliminary W24L11
Publication Release Date: October 1999
- 7 -
Revision A1
DATA RETENTION CHARACTERISTICS
(T
A
(
C) = 0 to 70)
PARAMETER SYM.
TEST CONDITIONS
MIN.
TYP. MAX. UNIT
V
DD
for Data Retention
V
DR
CS1
V
DD
-0.2V or
CS2
0.2V
2.0 - - V
Data Retention Current
I
DDDR
CS1
V
DD
-0.2V or
CS2
0.2V, V
DD
= 3V
- - 50
A
Chip Deselect to Data
Retention Time
T
CDR
See data retention waveform
0
-
-
nS
Operation Recovery Time
T
R
T
RC
* - - nS
*
Read Cycle Time
DATA RETENTION WAVEFORM
T
CDR
- 0.2V
DD
V
V
DD
CS1
T
R
CS1
V
DR
2V
=
>
=
>
0.9
DD
V
0.9
DD
V
CS2
0V CS2 0.2V
<
=
<
=
Preliminary W24L11
- 8 -
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
OPERATING
VOLTAGE
(V)
OPERATING
TEMPERATURE
(
C)
STANDBY
CURRENT
MAX.(
A)
PACKAGE
W24L11-70LL
70
3.0V to 3.6V
0 to 70
50
600 mil DIP
W24L11S-70LL
70
3.0V to 3.6V
0 to 70
50
450 mil SOP
W24L11T-70LL
70
3.0V to 3.6V
0 to 70
50
Standard type one
TSOP
W24L11Q-70LL
70
3.0V to 3.6V
0 to 70
50
Small type one TSOP
W24L11-70L
70
3.0V to 3.6V
0 to 70
100
600 mil DIP
W24L11S-70L
70
3.0V to 3.6V
0 to 70
100
450 mil SOP
W24L11T-70L
70
3.0V to 3.6V
0 to 70
100
Standard type one
TSOP
W24L11Q-70L
70
3.0V to 3.6V
0 to 70
100
Small type one TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Preliminary W24L11
Publication Release Date: October 1999
- 9 -
Revision A1
PACKAGE DIMENSIONS
32-pin P-DIP
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.37
1.22
0.054
0.048
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.050
1.27
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.555
0.550
0.545
14.10
13.97
13.84
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.650
1.660
41.91
42.16
0
15
0.085
2.16
0.650
0.630
16.00
16.51
protrusion/intrusion.
4. Dimension B1 does not include dambar
5. Controlling dimension: Inches
15
0
Seating Plane
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
32
1
16
17
32-pin SOP Wide Body
1
17
32
16
y
e
D
S
Seating Plane
b
A
A
E H
L
L
E
E
1
c
e
1
1
e
A
2
See Detail F
Detail F
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
.
Notes:
4. Controlling dimension: Inches
5. General appearance spec should be based
on final visual inspection spec.
0.20
0.15
0.008
0.006
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
L
E
1
2
E
0.012
0.31
0.118
3.00
0.004
0.101
0.014
0.106
0.016
0.111
0.020
2.57
0.36
0.10
2.69
0.41
2.82
0.51
0.047
0.004
0
10
0.805
0.055
0.817
0.063
1.19
20.45
1.40
20.75
1.60
0.556
0.556
0.546
14.38
14.12
13.87
10
0
0.10
11.43
11.30
11.18
0.450
0.445
0.440
0.58
0.79
0.99
0.023
0.031
0.039
1.12
1.27
1.42
0.044
0.050
0.056
S
0.91
0.036
Preliminary W24L11
- 10 -
Package Dimensions, continued
32-pin Standard Type One TSOP
A
A
A
2
1
L
L
1
Y
c
E
H
D
D
b
e
M
0.10(0.004)
Min.
Nom.
Max.
Min.
Nom.
Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
H
D
Controlling dimension: Millimeters
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007
0.008
0.009
0.005 0.006
0.007
0.720
0.724
0.728
0.311
0.315
0.319
0.780
0.787
0.795
0.020
0.016
0.020
0.024
0.031
0.000
0.004
1
3
5
0.002
1.20
0.05
0.15
1.05
1.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20
0.23
0.15
0.17
18.40
18.50
8.00
8.10
20.00
20.20
0.50
0.50
0.60
0.80
0.10
3
5
Dimension in mm
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
1
32-pin Small Type One TSOP
A
A
A
2
1
L
L
1
Y
c
E
H
D
D
b
e
1
Controlling dimension: Millimeters
Min.
Dimension in mm
Nom. Max.
Min.
Nom.
Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
H
D
11.70
13.20
0.675
1.25
0.05
0.15
1.05
1.00
0.95
0.17
0.14
0.30
0.00
0.20
0.27
0.15
0.16
11.80 11.90
13.40 13.60
0.50
0.50
0.70
0.10
0.049
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.0056 0.0059 0.0062
0.461 0.465 0.469
7.90
8.00
8.10
0.311 0.315 0.319
0.520 0.528 0.536
0.020
0.012 0.020 0.028
0.027
0.000
0.004
0.002
0
3
5
0
3
5
Dimension in Inches
Preliminary W24L11
Publication Release Date: October 1999
- 11 -
Revision A1
VERSION HISTORY
VERSION DATE PAGE
DESCRIPTION
A1 Oct.
1999 -
Initial
Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.