W24L257A
32K
8 HIGH-SPEED CMOS STATIC RAM
Publication Release Date: December 1996
- 1 -
Revision A5
GENERAL DESCRIPTION
The W24L257A is a high-speed, low-power CMOS static RAM organized as 32768
8 bits that
operates on a single 3.3-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
High-speed access time: 12/15/20 nS (max.)
Low-power consumption:
-
Active: 200 mW (typ.)
Single
+
3.3V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 28-pin 300 mil SOJ,
skinny DIP and standard type one TSOP
(8 mm
13.4 mm)
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-DIP
28-pin
TSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
OE
A11
A9
A8
A13
WE
V
DD
A14
A12
A7
A6
A5
A4
A3
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
A1
A2
V
SS
BLOCK DIAGRAM
A0
.
.
CS
A14
WE
I/O1
I/O8
OE
ARRAY
V
DD
V
SS
.
.
DATA I/O
DECODER
CONTROL
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A14
Address Inputs
I/O1
-
I/O8
Data Inputs/Outputs
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
V
DD
Power Supply
V
SS
Ground
W24L257A
- 2 -
TRUTH TABLE
CS
OE
WE
MODE
I/O1
-
I/O8
V
DD
CURRENT
H
X
X
Not Selected
High Z
I
SB
, I
SB1
L
H
H
Output Disable
High Z
I
DD
L
L
H
Read
Data Out
I
DD
L
X
L
Write
Data In
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to V
SS
Potential
-0.5 to +4.6
V
Input/Output to V
SS
Potential
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to +150
C
Operating Temperature
0 to +70
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 3.3V
5%, V
SS
= 0V, Ta = 0 to 70
C)
PARAMETER
SYM
.
TEST CONDITIONS
MIN
.
TYP
.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.0
-
V
DD
+0.3
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-10
-
+10
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD,
CS = V
IH (min.)
or OE = V
IH (min.)
or WE = V
IL (max.)
-10
-
+ 10
A
Output Low Voltage
V
OL
I
OL
= +8.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0 mA
2.4
-
-
V
Operating Power
I
DD
CS = V
IL (max.),
I/O = 0 mA
12
-
-
150
mA
Supply Current
Cycle = min.
15
-
-
120
mA
Duty = 100%
20
-
-
100
mA
Standby Power
Supply Current
I
SB
CS = V
IH (min.),
Cycle = min.
Duty = 100%
-
-
20
mA
I
SB1
CS
V
DD
-0.2V
-
-
200
A
Note: Typical characteristics are at V
DD
= 3.3V, Ta = 25
C.
W24L257A
Publication Release Date: December 1996
- 3 -
Revision A5
CAPACITANCE
(V
DD
= 3.3V, Ta = 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
AC Test Loads and Waveform
90%
90%
3 nS
10%
3 nS
10%
R1 320 ohm
3.3V
OUTPUT
R2
350 ohm
5 pF
R2
350 ohm
R1 320 ohm
3.3V
OUTPUT
30 pF
Including
Jig and
Scope
3.0V
0V
Including
Jig and
Scope
)
(For T
CLZ
,
,
,
,
,
T
OLZ
T
CHZ
T
OHZ
T
WHZ
T
OW
W24L257A
- 4 -
AC Characteristics, continued
(V
DD
= 3.3V
5%, V
SS
= 0V, Ta = 0 to 70
C)
(1) Read Cycle
PARAMETER
SYM.
W24L257A-12
W24L257A-15
W24L257A-20
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
12
-
15
-
20
-
nS
Address Access Time
T
AA
-
12
-
15
-
20
nS
Chip Select Access Time
T
ACS
-
12
-
15
-
20
nS
Output Enable to Output Valid
T
AOE
-
6
-
8
-
10
nS
Chip Selection to Output in Low Z
T
CLZ
*
4
-
4
-
4
-
nS
Output Enable to Output in Low Z
T
OLZ
*
0
-
0
-
0
-
nS
Chip Deselection to Output in High Z
T
CHZ
*
-
6
-
7
-
10
nS
Output Disable to Output in High Z
T
OHZ
*
-
6
-
7
-
10
nS
Output Hold from Address Change
T
OH
3
-
3
-
3
-
nS
These parameters are sampled but not 100% tested
(2) Write Cycle
PARAMETER
SYM.
W24L257A-12
W24L257A-15
W24L257A-20
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
T
WC
12
-
15
-
20
-
nS
Chip Selection to End of Write
T
CW
10
-
13
-
17
-
nS
Address Valid to End of Write
T
AW
10
-
13
-
17
-
nS
Address Setup Time
T
AS
0
-
0
-
0
-
nS
Write Pulse Width
T
WP
10
-
10
-
12
-
nS
Write Recovery Time
CS
, WE
T
WR
1
-
1
-
1
-
nS
Data Valid to End of Write
T
DW
7
-
9
-
10
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
7
-
8
-
10
nS
Output Disable to Output in High Z
T
OHZ
*
-
7
-
8
-
10
nS
Output Active from End of Write
T
OW
0
-
0
-
0
-
nS
These parameters are sampled but not 100% tested
W24L257A
Publication Release Date: December 1996
- 5 -
Revision A5
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS
D
OUT
T
CLZ
T
ACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS
D
OUT
T
AA
OE
T
AOE
T
OLZ
T
OH
CLZ
T
CHZ
T
T
ACS
T
OHZ
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