W25P022A
64K
32 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
Publication Release Date: September 1996
- 1 -
Revision A1
GENERAL DESCRIPTION
The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM
organized as 65,536
32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium
TM
burst mode and linear burst mode. The mode to be
executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by
the FT pin. A snooze mode reduces power dissipation.
The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The
default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to V
DDQ
. The state of
pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data
output in a burst read cycle when the device is deselected by CE2/
CE3
. This mode supports 3-1-1-1-
1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables
data output within one cycle in a burst read cycle when the device is deselected by CE2/
CE3
. In this
mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation
High-speed access time: 6/7 nS (max.)
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
Pipelined/non-pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst mode
& linear burst mode
Supports both 2T/2T & 2T/1T mode
Packaged in 100-pin QFP or TQFP
BLOCK DIAGRAM
A(15:0)
DATA I/O
REGISTER
INPUT
REGISTER
CONTROL
LOGIC
REGISTE
R
64K X 32
CORE
ARRAY
CE(3:1)
BWE
CLK
OE
GW
ADSC
ADSP
ADV
LBO
BW(4:1)
I/O(32:1)
FT
ZZ
MS
W25P022A
Publication Release Date: September 1996
- 3 -
Revision A1
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
A0
-
A15
Input, Synchronous
Host Address
I/O1
-
I/O32
I/O, Synchronous
Data Inputs/Outputs
CLK
Input, Clock
Processor Host Bus Clock
CE1
, CE2,
CE3
Input, Synchronous
Chip Enables
GW
Input, Synchronous
Global Write
BWE
Input, Synchronous
Byte Write Enable from Cache Controller
BW1
-
BW4
Input, Synchronous
Host Bus Byte Enables used with BWE
OE
Input, Asynchronous
Output Enable Input
ADV
Input, Synchronous
Internal Burst Address Counter Advance
ADSC
Input, Synchronous
Address Status from chip set
ADSP
Input, Synchronous
Address Status from CPU
ZZ
Input, Asynchronous
Snooze Pin for Low-power State, internally pulled low
FT
Input, Static
Connected to V
SSQ
: Device operates in flow-through
(non-pipelined) mode.
Connected to V
DDQ
or unconnected: Device operates
in piplined mode.
LBO
Input, Static
Lower Address Burst Order
Connected to V
SSQ
: Device operates in linear mode.
Connected to V
DDQ
or unconnected: Device is in non-
linear mode.
MS
Input, Static
Mode Select for 2T/2T or 2T/1T
When unconnected or pulled low, device is in 2T/1T
mode; if pulled high (V
DDQ
), device enters 2T/2T
mode.
V
DDQ
I/O Power Supply
V
SSQ
I/O Ground
V
DD
Power Supply
V
SS
Ground
NC
No Connection
W25P022A
- 4 -
TRUTH TABLE
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-Out
Read
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-Out
Read
Begin Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
X
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled
synchronous
to the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set
up
the SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold timings
are met.
W25P022A
Publication Release Date: September 1996
- 5 -
Revision A1
FUNCTIONAL DESCRIPTION
The W25P022A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel
TM
systems and linear mode, which can
be controlled by the
LBO
pin. The burst cycles are initiated by ADSP or ADSC and the burst
counter is incremented whenever ADV is sampled low. The device can also be switched to non-
pipelined mode if necessary.
Burst Address Sequence
INTEL SYSTEM (LBO = V
DDQ
)
LINEAR MODE (LBO = V
SSQ
)
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
External Start Address
00
01
10
11
00
01
10
11
Second Address
01
00
11
10
01
10
11
00
Third Address
10
11
00
01
10
11
00
01
Fourth Address
11
10
01
00
11
00
01
10
The device supports several types of write mode operations. BWE and BW [4:1] support individual
byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [4:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
WRITE TABLE
READ/WRITE FUNCTION
GW
BWE
BW4
BW3
BW2
BW1
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write byte 1 I/O1
-
I/O8
1
0
1
1
1
0
Write byte 2 I/O9
-
I/O16
1
0
1
1
0
1
Write byte 2, byte 1
1
0
1
1
0
0
Write byte 3 I/O17
-
I/O24
1
0
1
0
1
1
Write byte 3, byte 1
1
0
1
0
1
0
Write byte 3, byte 2
1
0
1
0
0
1
Write byte 3, byte 2, byte 1
1
0
1
0
0
0
Write byte 4 I/O25
-
I/O32
1
0
0
1
1
1
Write byte 4, byte 1
1
0
0
1
1
0
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