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Электронный компонент: W25P240A

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W25P240A
64K
64 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
Publication Release Date: February 1998
- 1 -
Revision A4
GENERAL DESCRIPTION
The W25P240A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM
organized as 65,536
64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports Pentium
TM
burst mode.
FEATURES
Synchronous operation
Support 66/75 MHz bus speed
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
Internal burst counter supports Intel burst mode
Packaged in 100-pin QFP
BLOCK DIAGRAM
A(15:0)
DATA I/O
REGISTER
INPUT
REGISTER
CONTROL
LOGIC
64K X 64
CORE
ARRAY
CE
BWE
CLK
OE
GW
ADSC
ADSP
ADV
BW(8:1)
I/O(64:1)
W25P240A
- 2 -
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
80
79
78
77
76
75
74
73
72
71
70
69
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
C
L
K
/
G
W
/
O
E
/
A
D
S
C
/
A
D
S
P
/
A
D
V
100-pin
QFP MO-108
I/O 35
I/O 36
I/O 39
I/O 40
I/O 41
I/O 42
I/O 45
I/O 46
I/O 49
I/O 50
I/O 53
I/O 54
I/O 55
I/O 56
I/O 59
I/O 60
I/O 62
I/O 37
I/O 38
I/O 43
I/O 44
I/O 47
I/O 48
I/O 51
I/O 52
I/O 57
I/O 58
I/O 61
I/O 28
I/O 27
I/O 24
I/O 23
I/O 22
I/O 21
I/O 18
I/O 17
I/O 14
I/O 13
I/O 10
I/O 09
I/O 08
I/O 07
I/O 04
I/O 03
I/O 29
I/O 26
I/O 25
I/O 20
I/O 19
I/O 16
I/O 15
I/O 12
I/O 11
I/O 06
I/O 05
/
B
W
4
/
B
W
3
/
B
W
2
/
B
W
1
I
/
O
3
2
I
/
O
3
1
I
/
O
6
3
I
/
O
6
4
A
7
A
6
A
5
I
/
O
1
I
/
O
2
I/O 30
V
I
/
O
3
4
/
B
W
8
I
/
O
3
3
/
B
W
7
/
B
W
6
/
B
W
5
/
B
W
E
/
C
E
A
4
A
3
A
2
A
1
A
0
A
8
A
9
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
5
DD
V
SS
V
DD
V
SS
W25P240A
Publication Release Date: February 1998
- 3 -
Revision A4
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
A0
-
A15
Input, Synchronous
Host Address
I/O1
-
I/O64
I/O, Synchronous
Data Inputs/Outputs
CLK
Input, Clock
Processor Host Bus Clock
CE
Input, Synchronous
Chip Enables
GW
Input, Synchronous
Global Write
BWE
Input, Synchronous
Byte Write Enable from Cache Controller
BW1
-
BW8
Input, Synchronous
Host Bus Byte Enables used with
BWE
OE
Input, Asynchronous
Output Enable Input
ADV
Input, Synchronous
Internal Burst Address Counter Advance
ADSC
Input, Synchronous
Address Status from chip set
ADSP
Input, Synchronous
Address Status from CPU
V
DD
Power Supply
V
SS
Ground
FUNCTIONAL DESCRIPTION
The W25P240A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports only one burst address sequence for Intel
TM
systems. The burst cycles are
initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low.
Burst Address Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
External Start Address
00
01
10
11
Second Address
01
00
11
10
Third Address
10
11
00
01
Fourth Address
11
10
01
00
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
W25P240A
- 4 -
TRUTH TABLE
CYCLE
ADDRESS
USED
CE
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
0
X
X
Hi-Z
X
Begin Read
External
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
1
0
0
D-Out
Read
Suspend Read
Current
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
1
1
0
D-Out
Read
Begin Write
Current
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
1
1
X
Hi-Z
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to
the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set up the
SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold
timings
are met.
WRITE TABLE
READ/WRITE FUNCTION
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Read
1
1
X
X
X
X
X
X
X
X
Read
1
0
1
1
1
1
1
1
1
1
Write byte 1 I/O1
-
I/O8
1
0
1
1
1
1
1
1
1
0
Write byte 2 I/O9
-
I/O16
1
0
1
1
1
1
1
1
0
1
Write byte 2, byte 1
1
0
1
1
1
1
1
1
0
0
W25P240A
Publication Release Date: February 1998
- 5 -
Revision A4
Write Table, continued
READ/WRITE FUNCTION
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Write byte 3 I/O17
-
I/O24
1
0
1
1
1
1
1
0
1
1
Write byte 3, byte 1
1
0
1
1
1
1
1
0
1
0
Write byte 3, byte 2
1
0
1
1
1
1
1
0
0
1
Write byte 3, byte 2, byte 1
1
0
1
1
1
1
1
0
0
0
Write byte 4, I/O25
-
I/O32
1
0
1
1
1
1
0
1
1
1
Write byte 4, byte 1
1
0
1
1
1
1
0
1
1
0
Write byte 4, byte 2
1
0
1
1
1
1
0
1
0
1
Write byte 4, byte 2, byte 1
1
0
1
1
1
1
0
1
0
0
Write byte 4, byte 3
1
0
1
1
1
1
0
0
1
1
Write byte 4, byte 3, byte 1
1
0
1
1
1
1
0
0
1
0
Write byte 4, byte 3, byte 2
1
0
1
1
1
1
0
0
0
1
Write byte 4, byte 3, byte 2, byte 1
1
0
1
1
1
1
0
0
0
0
Write byte 5, I/O33
-
I/O40
1
0
1
1
1
0
1
1
1
1
Write byte 5, byte 1
1
0
1
1
1
0
1
1
1
0
Write byte 5, byte 2
1
0
1
1
1
0
1
1
0
1
Write byte 5, byte 2, byte 1
1
0
1
1
1
0
1
1
0
0
Write byte 5, byte 3
1
0
1
1
1
0
1
0
1
1
Write byte 5, byte 3, byte 1
1
0
1
1
1
0
1
0
1
0
Write byte 5, byte 3, byte 2
1
0
1
1
1
0
1
0
0
1
Write byte 5, byte 3, byte 2, byte 1
1
0
1
1
1
0
1
0
0
0
Write byte 5, byte 4
1
0
1
1
1
0
0
1
1
1
Write byte 5, byte 4, byte 1
1
0
1
1
1
0
0
1
1
0
Write byte 5, byte 4, byte 2
1
0
1
1
1
0
0
1
0
1
Write byte 5, byte 4, byte 2, byte 1
1
0
1
1
1
0
0
1
0
0
Write byte 5, byte 4, byte 3
1
0
1
1
1
0
0
0
1
1
Write byte 5, byte 4, byte 3, byte1
1
0
1
1
1
0
0
0
1
0
Write byte 5, byte 4, byte 3, byte2
1
0
1
1
1
0
0
0
0
1
Write byte 5, byte 4, byte 3, byte 2,
byte 1
1
0
1
1
1
0
0
0
0
0
Write byte 6
1
0
1
1
0
1
1
1
1
1
Write byte 6, byte1
1
0
1
1
0
1
1
1
1
0
Write byte 6, byte2
1
0
1
1
0
1
1
1
0
1
Write byte 6, byte2, byte1
1
0
1
1
0
1
1
1
0
0
..... and so on .....
...
...
...
...
...
...
...
...
...
...
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 2, byte 1
1
0
0
0
0
0
0
1
0
0
W25P240A
- 6 -
Write Table, continued
READ/WRITE FUNCTION
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Write byte 8, byte 7, byte 6,
byte 5, byte 4, byte 3
1
0
0
0
0
0
0
0
1
1
Write byte 8, byte 7, byte 6,
byte 5, byte 4, byte 3, byte 1
1
0
0
0
0
0
0
0
1
0
Write byte 8, byte 7, byte 6,
byte 5, byte 4, byte 3, byte 2
1
0
0
0
0
0
0
0
0
1
Write all bytes
1
0
0
0
0
0
0
0
0
0
Write all bytes
0
x
x
x
x
x
x
x
x
x
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Supply Voltage to Vss
-0.5 to 4.6
V
Input/Output to V
SS
Potential
V
SS
-0.5 to V
DD
+0.5
V
Allowable Power Dissipation
1.5
W
Storage Temperature
-65 to 150
C
Operating Temperature
0 to +55
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 3.15V to 3.6V, V
SS
= 0V, T
A
= 0 to 55
C)
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP
.
MAX.
UNIT
Input Low Voltage
V
IL
-
-0.5
-
+0.8
V
Input High Voltage
V
IH
-
+2.0
-
V
DD
+0.3
V
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-10
-
+10
A
Output Leakage
Current
I
LO
V
I/O
= V
SS
to V
DD,
and data I/O
pins in high-Z state defined in
truth table
-10
-
+ 10
A
Output Low Voltage
V
OL
I
OL
= +8.0 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -4.0 mA
2.4
-
-
V
Operating Current
I
DD
T
CYC
min., I/O = 0 mA
-
-
350
mA
Standby Current
I
SB
Unselected mode defined in
truth table, V
IN
, V
IO
= V
IH
(min.) /V
IL
(max.) T
CYC
min.
-
-
80
mA
Note: Typical characteristics are measured at V
DD
= 3.3V, T
A
= 25
C.
W25P240A
Publication Release Date: February 1998
- 7 -
Revision A4
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Input/Output Capacitance
C
I/O
V
OUT
= 0V
8
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
2 nS
Input and Output Timing Reference Level
1.5V
Output Load
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
AC Test Loads and Waveform
90%
90%
2 nS
10%
2 nS
10%
RL = 50 ohm
VL = 1.5V
OUTPUT
5 pF
R2
350 ohm
R1 320 ohm
3.3V
OUTPUT
30 pF
Including
Jig and
Scope
3.0V
0V
Including
Jig and
Scope
Zo = 50 ohm
(For
KHZ,
T
KLZ,
T
OHZ,
T
OLZ,
measurement)
T
W25P240A
- 8 -
AC Timing Characteristics
(V
DD
= 3.15V to 3.6V, V
SS
= 0V, T
A
= 0 to 55
C)
PARAMETER
SYMBOL
W25P240A-6
W25P240A-6A
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Add. Setup Time
T
AS
1.5
-
1.5
-
nS
Add. Hold Time
T
AH
1.5
-
1.5
-
nS
Write Data Setup Time
T
DS
2.5
-
2.5
-
nS
Write Data Hold Time
T
DH
0.5
-
0.5
-
nS
ADV
Setup Time
T
ADVS
2.5
-
2.5
-
nS
ADV
Hold Time
T
ADVH
0.5
-
0.5
-
nS
ADSP
Setup Time
T
ADSS
2.5
-
2.5
-
nS
ADSP
Hold Time
T
ADSH
0.5
-
0.5
-
nS
ADSC
Setup Time
T
ADCS
2.5
-
2.5
-
nS
ADSC
Hold Time
T
ADCH
0.5
-
0.5
-
nS
CE , Setup Time
T
CES
2.5
-
2.5
-
nS
CE , Hold Time
T
CEH
0.5
-
0.5
-
nS
GW
, BWE X Setup Time
T
WS
2.0
-
2.0
-
nS
GW
, BWE X Hold Time
T
WH
1.0
-
1.0
-
nS
Clock Cycle Time
T
CYC
13.3
-
15
-
nS
Clock High Pulse Width
T
KH
5
-
6
-
nS
Clock Low Pulse Width
T
KL
5
-
6
-
nS
Clock to Output Valid
T
KQ
-
6
-
7
nS
Clock to Output High-Z
T
KHZ
2
13.3
2
15
nS
Note
Clock to Output Low-Z
T
KLZ
0
-
0
-
nS
Note
Clock to Output Invalid
T
KX
2
-
2
-
nS
Note
Output Enable to Output Valid
T
OE
-
6
-
7
nS
Output Enable to Output High-Z
T
OHZ
-
6
-
7
nS
Note
Output Enable to Output Low-Z
T
OLZ
0
-
0
-
nS
Note
Output Enable to Output Invalid
T
OX
0
-
0
-
nS
Note: These parameters are sampled but not 100% tested.
W25P240A
Publication Release Date: February 1998
- 9 -
Revision A4
TIMING WAVEFORMS
Read Cycle Timing
Single Read
Burst Read
Unselected
T
CYC
CLK
T
ADSS
T
ADSH
T
KH
T
KL
ADSP is blocked by CE inactive
T
ADCS
T
ADCH
ADSC initiated read
T
ADVS
T
ADVH
T
AS
T
AH
RD1
RD2
RD3
T
WS
T
WH
T
WS
T
WH
T
CES
T
CEH
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE
Pipelined Read
Suspend Burst
3a
2d
2c
2b
2a
1a
T
OE
T
OHZ
T
OLZ
T
OX
T
KX
T
KHZ
T
KX
High-Z
High-Z
OE
Data-Out
Data-In
T
KLZ
T
KQ
DON'T CARE
UNDEFINED
CE masks ADSP
Unselected with CE
W25P240A
- 10 -
Timing Waveforms, continued
Write Cycle Timing
1a
Single Write
Burst Write
Unselected
T
CYC
CLK
T
ADSS
T
ADSH
T
KH
T
KL
ADSP is blocked by CE inactive
T
ADCS
T
ADCH
ADSC initiated write
T
ADVS
T
ADVH
T
AS
T
AH
WR3
T
WS
T
WH
T
WS
T
WH
T
CES
T
CEH
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE
OE
Data-Out
Data-In
2a
2b
2c
2d
3a
Write
to be pipelined during a writeback
GW allows processor address (and BE = BWE)
T
WS
T
WH
WR1
WR2
WR3
T
DS
T
DH
BW[8:1] are applied only to first cycle of WR2
ADV must be inactive for ADSP write
DON'T CARE
UNDEFINED
CE masks ADSP
Unselected with CE
WR1
WR2
W25P240A
Publication Release Date: February 1998
- 11 -
Revision A4
Timing Waveforms, continued
Read/Write Cycle Timing
1a
Single Read
Burst Read
Unselected
T
CYC
CLK
T
ADSS
T
ADSH
T
KH
T
KL
T
ADCS
T
ADCH
ADSC initiated read
T
ADVS
T
ADVH
Suspend Burst
T
AS
T
AH
RD1
WR1
RD2
T
WS
T
WH
T
WS
T
WH
T
CES
T
CEH
T
OE
T
OHZ
T
OLZ
T
OH
T
KHZ
T
KX
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE
OE
Data-Out
Data-In
T
KLZ
T
KQ
Single Write
WR1
T
WS
T
WH
CE masks ADSP
Unselected with CE
2d
2c
2a
2b
1a
T
KHZ
T
DS
T
DH
DON'T CARE
UNDEFINED
ADSP is blocked by CE inactive
W25P240A
- 12 -
ORDERING INFORMATION
PART NO.
SUPPORTABLE
BUS SPEED
(MHz)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
W25P240AF-6
75
350
80
100-pin QFP
W25P240AF-6A
66
350
80
100-pin QFP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W25P240A
Publication Release Date: February 1998
- 13 -
Revision A4
PACKAGE DIMENSIONS
100-pin QFP
E H
E
y
A
A
Seating Plane
L
L
1
See Detail F
H
D
D
b
e
2
1
C
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
0.08
0
7
0
0.003
1.60
0.95
17.40
0.80
17.20
0.65
17.00
0.063
0.037
0.921
0.685
0.031
0.913
0.677
0.025
0.905
0.669
0.65
20.10
14.10
0.20
0.40
2.87
20.00
14.00
2.72
19.90
13.90
0.10
0.20
2.57
0.791
0.555
0.008
0.016
0.113
0.787
0.551
0.107
0.026
0.783
0.547
0.004
0.008
0.101
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in inches
Dimension in mm
b
c
D
e
H
D
H
E
L
y
L
1
A
A
A
1
2
E
0.012
0.006
0.15
0.30
23.00
23.20
23.40
7
0.020
0.032
0.498
0.802
0.35
0.25
0.01
0.014
0.018
0.45
W25P240A
- 14 -
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
Dec. 1996
Initial Issued
A2
Mar. 1997
1, 8, 12
Change part no. from W25P240A-75/66 to W25P240A-6/7
A3
Aug. 1997
8
A.C. Timing Characteristics:
T
AS
from 2.5 to 1.5
T
AH
from 0.5 to 1.5
T
WS
from 2.5 to 2.0
T
WH
from 0.5 to 1.0
6, 8
Working temperature range from 70
-
0
C to 55
-
0
C
A4
Feb. 1998
8, 12
Part no. W25P240AX-"7" change to "6A"
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.