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Электронный компонент: W25P243AD-6

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W25P243A
64K
64 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
Publication Release Date: August 1999
- 1 - Revision A3
GENERAL DESCRIPTION
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536
64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium
TM
burst mode and linear burst mode. The mode to be
executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by
the FT pin. A snooze mode can reduce power dissipation.

W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/ CE3 .

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
Synchronous operation
High-speed access time: 4.5/5/6 nS (max.)
Single +3.3V power supply
Individual byte write capability
3.3V LVTTL compatible I/O
Clock-controlled and registered input
Asynchronous output enable
Pipelined data output capability
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
Support 2T/1T mode
Packaged in 128-pin QFP and TQFP
BLOCK DIAGRAM
A(15:0)
DATA I/O
REGISTER
INPUT
REGISTER
CONTROL
LOGIC
REGISTER
64K X 64
CORE
ARRAY
CE(3:1)
BWE
CLK
OE
GW
ADSC
ADSP
ADV
LBO
BW(8:1)
I/O(64:1)
ZZ
W25P243A
- 2 -
PIN CONFIGURATION
V
S
S
Q
/
L
B
O
A
1
5
A
1
4
A
1
3
V
D
D
V
S
S
A
1
2
A
1
1
A
1
0
A
9
R
S
V
A
8
A
7
A
6
A
5
A
4
A
3
V
D
D
V
S
S
A
2
A
1
A
0
Z
Z
V
D
D
Q
VDDQ
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
VSSQ
VDDQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
VSSQ
VDDQ
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
VSSQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
5
2
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
V
S
S
Q
V
D
D
Q
C
E
2
/
C
E
3
V
S
S
V
D
D
/
C
E
/
B
W
8
/
B
W
7
/
B
W
6
/
B
W
5
/
O
E
C
L
K
/
B
W
E
/
G
W
/
B
W
4
/
B
W
3
V
S
S
V
D
D
/
B
W
2
/
B
W
1
/
A
D
S
C
/
A
D
S
P
/
A
D
V
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
1
1
5
VSSQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
VSSQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
VSSQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
N
C
N
C
N
C
W25P243A
Publication Release Date: August 1999
- 3 - Revision A3
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
A0
-
A15
Input, Synchronous
Host address
I/O1
-
I/O64
I/O, Synchronous
Data Inputs/Outputs
CLK
Input, Clock
Processor host bus clock
CE1, CE2, CE3
Input, Synchronous
Chip enables
GW
Input, Synchronous
Global write
BWE
Input, Synchronous
Byte write enable from cache controller
BW1
-
BW8
Input, Synchronous
Host bus byte enables used with BWE
OE
Input, Asynchronous
Output enable input
ADV
Input, Synchronous
Internal burst address counter advance
ADSC
Input, Synchronous
Address status from Chip Set
ADSP
Input, Synchronous
Address status from CPU
ZZ
Input, Asynchronous
Snooze pin for low-power state, internal pull low
LBO
Input, Static
Lower address burst order
Connected to V
SS
: Device is in linear mode.
Connected to V
DD
or unconnected: Device is in non-
linear mode.
V
DDQ
I/O power supply
V
SSQ
I/O ground
V
DD
Power supply
V
SS
Ground
RSV
Reserved pin, don't use these pins
NC
No connection
W25P243A
- 4 -
FUNCTIONAL DESCRIPTION
The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel
TM
systems (Interleaved mode) and linear
mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC
and the burst counter is incremented whenever ADV is sampled low.
BURST ADDRESS SEQUENCE
INTEL SYSTEM ( LBO = V
DD
)
LINEAR MODE ( LBO = V
SS
)
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
External Start Address
00
01
10
11
00
01
10
11
Second Address
01
00
11
10
01
10
11
00
Third Address
10
11
00
01
10
11
00
01
Fourth Address
11
10
01
00
11
00
01
10
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-Out
Read
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-Out
Read
W25P243A
Publication Release Date: August 1999
- 5 - Revision A3
Truth Table, continued
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP ADSC
ADV
OE
DATA
WRITE*
Begin Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
X
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously
with the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup to
the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings
are met.
WRITE TABLE
READ/WRITE FUNCTION
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Read
1
1
X
X
X
X
X
X
X
X
Read
1
0
1
1
1
1
1
1
1
1
Write byte 1 I/O1
-
I/O8
1
0
1
1
1
1
1
1
1
0
Write byte 2 I/O9
-
I/O16
1
0
1
1
1
1
1
1
0
1
Write byte 2, byte 1
1
0
1
1
1
1
1
1
0
0
Write byte 3 I/O17
-
I/O24
1
0
1
1
1
1
1
0
1
1
Write byte 3, byte 1
1
0
1
1
1
1
1
0
1
0
Write byte 3, byte 2
1
0
1
1
1
1
1
0
0
1
Write byte 3, byte 2, byte 1
1
0
1
1
1
1
1
0
0
0
Write byte 4, I/O25
-
I/O32
1
0
1
1
1
1
0
1
1
1
Write byte 4, byte 1
1
0
1
1
1
1
0
1
1
0
Write byte 4, byte 2
1
0
1
1
1
1
0
1
0
1
Write byte 4, byte 2, byte 1
1
0
1
1
1
1
0
1
0
0
Write byte 4, byte 3
1
0
1
1
1
1
0
0
1
1
Write byte 4, byte 3, byte 1
1
0
1
1
1
1
0
0
1
0
Write byte 4, byte 3, byte 2
1
0
1
1
1
1
0
0
0
1
Write byte 4, byte 3, byte 2, byte 1
1
0
1
1
1
1
0
0
0
0
Write byte 5, I/O33
-
I/O40
1
0
1
1
1
0
1
1
1
1
Write byte 5, byte 1
1
0
1
1
1
0
1
1
1
0