W27C01
128K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: April 15, 2002
- 1 - Revision A2
GENERAL DESCRIPTION
The W27C01 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131,072 x 8 bits.
It requires only one supply in the range of 5.0V
5% in
normal read mode. The W27C01 provides an electrical chip erase function.
FEATURES
Single power supply voltage:
5.0V
5%
High speed access time: 70 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20
A (max.)
+12V erase/programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available
packages: 32-pin 600 mil DIP,
32-lead PLCC and 32-lead STSOP
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4
3
2
1
3
2
3
1
3
0
A14
A13
A8
A9
#OE
A11
Q7
29
28
27
26
25
24
23
22
21
32-lead PLCC
V
s
s
1
5
1
6
1
7
1
8
1
9
2
0
N
C
V
D
D
#CE
A10
A
1
5
A
1
6
Q
3
A7
A
1
2
V
p
p
#
P
G
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
Q0
Q1
Q2
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
32-lead STSOP
A15
A12
A7
A6
A5
A4
#PGM
A14
A13
A8
V
DD
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
NC
V SS
V
PP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q0
A0
A2
A3
A4
A5
A6
A7
A12
A15
A16
A1
Vpp
Vss
Q2
Q1
30
31
32
25
26
27
28
29
20
21
22
23
24
19
18
17
Q5
#OE
A10
Q7
Q6
A13
A8
A9
A11
#PGM
NC
A14
Q3
Q4
#CE
V
DD
32-pin
PDIP
BLOCK DIAGRAM
V
Vss
DD
V
PP
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
#CE
#OE
A0
.
.
A16
#PGM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A16
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#PGM
Program Enable
V
PP
Program/Erase Supply Voltage
V
DD
Power Supply
V
ss
Ground
NC
No Connection
W27C01
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C01 has two control functions and both of these produce data at
the outputs.
#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from #CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of #OE, if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27C01 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an
EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(12V), V
DD
= V
CE
(5V), #CE low, #OE high, A9 = V
HH
(12V), A0 low
,
and all other address pins low and data input pins high. Pulsing #PGM low starts the
erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
DD
= V
PE
(5V), #CE low, and #OE low,
#PGM
high
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V),
V
DD
= V
CP
(5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins
equal the desired inputs. Pulsing #PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed
with the desired data or not. Hence, after each byte is programmed, a program verify operation should
be performed. The program verify mode automatically ensures a substantial program margin. This mode
will be entered after the program operation if V
PP
= V
PP
(12V), #CE low, #OE low
,
and #PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the
#CE, the W27C01 may have common inputs.
Standby Mode
The standby mode significantly reduces V
DD
current. This mode is entered when #CE high. In standby
mode, all outputs are in a high impedance state, independent of #OE and #PGM.
W27C01
Publication Release Date: April 15, 2002
- 3 - Revision A2
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C01 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic
capacitor connected between its V
DD
and Vss. This high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7
F
electrolytic capacitor should be placed at the array's power supply connection between V
DD
and Vss.
The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
V
DD
= 5.0V
5%, Vpp = Vp
E
= V
HH
= 12V, V
CP
= V
PE
= 5V, X = V
IH
or V
IL
MODE
PINS
#CE
#OE #PGM A0 A9 V
DD
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
X
V
DD
V
DD
D
OUT
Output Disable
V
IL
V
IH
X
X
X
V
DD
V
DD
High Z
Standby (TTL)
V
IH
X
X
X
X
V
DD
V
DD
High Z
Standby (CMOS)
V
DD
0.3V
X
X
X
X
V
DD
V
DD
High Z
Program
V
IL
V
IH
V
IL
X
X
V
CP
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
V
CP
V
PP
D
OUT
Program Inhibit
V
IH
X
X
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
IL
V
PE
V
CP
V
PE
FF (Hex)
Erase Verify
V
IL
V
IL
V
IH
X
X
V
PE
V
PE
D
OUT
Erase Inhibit
V
IH
X
X
X
X
V
CP
V
PE
High Z
Product
Identifier-manufacturer
V
IL
V
IL
X
V
IL
V
HH
V
DD
V
DD
DA (Hex)
Product Identifier-device
V
IL
V
IL
X
V
IH
V
HH
V
DD
V
DD
01 (Hex)
W27C01
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Operation Temperature
0 to +70
C
Storage Temperature
-65 to +125
C
Voltage on all Pins with Respect to Ground Except V
DD,
V
PP
and
A9 Pins
-0.5 to V
DD
+0.5
V
Voltage on V
DD
Pin with Respect to Ground
-0.5 to +7.0
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
CAPACITANCE
(V
DD
= 5.0V
5%, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
READ OPERATION DC CHARACTERISTICS
(V
DD
= 5.0V
5%, T
A
= 0 to 70
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= 0V to V
DD
-5
-
5
A
Output Leakage
Current
I
LO
V
OUT
= 0V to V
DD
-10
-
10
A
Standby V
DD
Current
(TTL input)
I
SB
#CE = V
IH
-
-
1
mA
Standby V
DD
Current
(CMOS input)
I
SB
1 #CE = V
DD
0.2V
-
-
100
A
V
DD
Operating Current I
CC
#CE=V
IL,
I
OUT
= 0 mA,
f = 5 MHz
-
-
30
mA
V
PP
Operating Current
I
PP
V
PP
= V
DD
-
-
10
A
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.2
-
V
DD
+0.5
V
Output Low Voltage
V
OL
I
OL
= 1.6 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -0.1 mA
2.4
-
-
V
V
PP
Operating Voltage
V
PP
-
V
DD -
0.7
-
V
DD
V
W27C01
Publication Release Date: April 15, 2002
- 5 - Revision A2
Program/Erase DC Characteristics
(T
A
= 25
C, V
DD
= 5.0V
5%, V
HH
= 12V)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
DD
Program Current
I
CP
#CE = V
IL,
#OE =
V
IH,
#PGM = V
IL
-
-
30
mA
V
DD
Erase Current
I
CE
#CE = V
IL,
#OE = V
IH,
#PGM = V
IL
, A9 = V
HH
-
-
30
mA
V
PP
Program Current
I
PP
#CE = V
IL,
#OE =
V
IH,
#PGM = V
IL
-
-
30
mA
V
PP
Erase Current
I
PE
#CE = V
IL,
#OE = V
IH,
#PGM = V
IL
, A9 = V
HH
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
V
ID
-
11.5
12.0
12.5
V
A9 Erase Voltage
V
ID
-
11.75 12.0 14.25
V
V
PP
Program Voltage
V
PP
-
11.75 12.0 12.25
V
V
PP
Erase Voltage
V
PE
-
11.75 12.0 14.25
V
V
DD
Supply Voltage (Program)
V
CP
-
4.5
5.0
5.5
V
V
DD
Supply Voltage (Erase)
V
CE
-
4.5
5.0
5.5
V
V
DD
Supply Voltage (Erase
Verify)
V
PE
-
-
5.0
-
V
Note: V
DD
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
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