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Электронный компонент: W27C020PM-12

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Preliminary W27C020M
256K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: March 1999
- 1 -
Revision A1
GENERAL DESCRIPTION
The W27C020M is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 262144
8 bits that operates on a single 5 volt power supply. The W27C020M
provides an electrical chip erase function.The W27C020M is designed to be used in 3.3V I/O bus
interface enviornment.
FEATURES
High speed access time:
70/90/120 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
Output level : 3.3V compatible output
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available
packages: 32-pin 600 mil DIP and
PLCC
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4 3 2 1 3
2
3
1
3
0
A14
A13
A8
A9
OE
A11
Q7
29
28
27
26
25
24
23
22
21
32-pin PLCC
G
N
D
1
5
1
6
1
7
1
8
1
9
2
0
1
7
V
c
c
CE
A10
Q5
OE
A10
Q7
Q6
A13
A8
A9
A11
PGM
A17
Q0
A0
A2
A3
A4
A5
A6
A7
A12
A15
A16
A14
A1
Vcc
Vpp
A
1
5
A
1
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
30
31
32
25
26
27
28
29
20
21
22
23
24
19
18
17
Q3
Q4
GND
Q2
CE
Q1
Q
3
A7
A
1
2
V
p
p
/
P
G
M
A
32-pin DIP
BLOCK DIAGRAM
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
CE
OE
A0
.
PGM
V
GND
CC
V
PP
A17
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A17
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
PGM
Program Enable
V
PP
Program/Erase Supply Voltage
V
CC
Power Supply
GND
Ground
Preliminary W27C020M
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C020M has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE , if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C020M uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), CE low, OE high, A9 = V
ID
(14V), A0 low
,
and all other address pins low and data input pins high. Pulsing PGM low starts the
erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE low, and OE low
,
PGM high
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), CE low, OE high , the address pins equal the desired addresses, and the
input pins equal the desired inputs. Pulsing PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE low
,
OE low
,
and
PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the
CE, the W27C020M may have common inputs.
Preliminary W27C020M
Publication Release Date: March 1999
- 3 -
Revision A1
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE high . In standby
mode, all outputs are in a high impedance state, independent of OE and PGM .
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C020M provides two control inputs
for multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I
SB
), active current levels (I
CC
),
and transient current peaks produced by the falling and rising edges of CE. Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, V
CE
= 5V, V
ID
= 14V, X = V
IH
or V
IL
MODE
PINS
CE
OE
PGM
A0
A9
V
CC
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
X
V
CC
V
CC
D
OUT
Output Disable
V
IL
V
IH
X
X
X
V
CC
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
X
V
CC
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
X
V
CC
V
CC
High Z
Program
V
IL
V
IH
V
IL
X
X
V
CP
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
V
CC
V
PP
D
OUT
Program Inhibit
V
IH
X
X
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
IL
V
ID
V
CE
V
PE
FF (Hex)
Erase Verify
V
IL
V
IL
V
IH
X
X
V
CC
V
PE
D
OUT
Erase Inhibit
V
IH
X
X
X
X
V
CE
V
PE
High Z
Product Identifier-
manufacturer
V
IL
V
IL
X
V
IL
V
HH
V
CC
V
CC
DA (Hex)
Product Identifier-device
V
IL
V
IL
X
V
IH
V
HH
V
CC
V
CC
85 (Hex)
Preliminary W27C020M
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Operation Temperature
0 to +70
C
Storage Temperature
-65 to +125
C
Voltage on all Pins with Respect to Ground Except V
CC,
V
PP
and A9 Pins
-0.5 to V
CC
+0.5
V
Voltage on V
CC
Pin with Respect to Ground
-0.5 to +7
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Erase Characteristics
(T
A
= 25
C
5
C, V
CC
= 5.0V
5%, V
HH
= 14V)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Erase Current
I
CP
CE = V
IL,
OE = V
IH,
PGM = V
IL
, A9 = V
HH
-
-
30
mA
V
PP
Erase Current
I
PP
CE = V
IL,
OE = V
IH,
PGM = V
IL
, A9 = V
HH
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
V
OH2
I
OH
= -0.1 mA, V
CC
=
5V
-
-
3.8
V
A9 Erase Voltage
V
ID
-
13.75
14.0
14.25
V
V
PP
Erase Voltage
V
PE
-
13.75
14.0
14.25
V
V
CC
Supply Voltage (Erase)
V
CE
-
4.75
5.0
5.25
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
Preliminary W27C020M
Publication Release Date: March 1999
- 5 -
Revision A1
CAPACITANCE
(V
CC
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
70 nS
90/120 nS
Input Pulse Levels
0 to 3.0V
0.45V to 2.4V
Input Rise and Fall Times
5 nS
10 nS
Input and Output Timing Reference
Level
1.5V/1.5V
0.8V/2.0V
Output Load
C
L
= 30 pF,
I
OH
/I
OL
= -0.4 mA/2.1 mA
C
L
= 100 pF,
I
OH
/I
OL
= -0.4 mA/2.1 mA
AC Test Load and Waveforms
+1.3V
3.3K ohm
100 pF for 90/120 nS (Including Jig and Scope)
D
(IN914)
OUT
30 pF for 70 nS (Including Jig and Scope)
3.0V
0V
1.5V
Test Point
Test Point
1.5V
For 70 nS
2.4V
0.45V
2.0V
0.8V
2.0V
0.8V
Test Points
Test Points
Input/Outpu
t
For 90/120 nS