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Электронный компонент: W27E010-15

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W27E010
128K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: June 2000
- 1 - Revision A6
GENERAL DESCRIPTION
The W27E010 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 131072
8 bits that operates on a single 5 volt power supply. The W27E010
provides an electrical chip erase function.
FEATURES
High speed access time:
45/55/70/90/120 nS (max.)
Read operating current: 30 mA (typ.)
Erase/Programming operating current:
1 mA (typ.)
Standby current: 5
A (typ.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available
packages: 32-pin 600 mil DIP,
450 mil SOP and PLCC
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4 3
2
1
3
2
3
1
3
0
A14
A13
A8
A9
OE
A11
Q7
29
28
27
26
25
24
23
22
21
32-pin PLCC
G
N
D
1
5
1
6
1
7
1
8
1
9
2
0
N
C
V
c
c
CE
A10
Q5
OE
A10
Q7
Q6
A13
A8
A9
A11
PGM
NC
Q0
A0
A2
A3
A4
A5
A6
A7
A12
A15
A16
A14
A1
Vcc
Vpp
A
1
5
A
1
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
30
31
32
25
26
27
28
29
20
21
22
23
24
19
18
17
Q3
Q4
GND
Q2
CE
Q1
Q
3
A7
A
1
2
V
p
p
/
P
G
M
BLOCK DIAGRAM
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
CE
OE
A0
.
.
V
GND
CC
A16
PGM
V
PP
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A16
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
PGM
Program Enable
V
PP
Program/Erase Supply Voltage
V
CC
Power Supply
GND
Ground
NC
No Connection
W27E010
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E010 has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE , if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E010 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), CE = V
IL
, (0.8V or below
but higher than GND), OE = V
IH
(2V or above but lower than V
CC
), A9 = V
HH
(14V), A0 = V
IL,
and all
other address pins equal V
IL
and data input pins equal V
IH
. Pulsing PGM low starts the erase
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE = V
IL
, and OE =
V
IL,
PGM = V
IH.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), CE = V
IL
, OE = V
IH
, the address pins equal the desired addresses, and the
input pins equal the desired inputs. Pulsing PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE = V
IL,
OE = V
IL,
and
PGM = V
IH
.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
IH
, erasing or programming of non-target chips is inhibited, so that except for the
CE, the W27E010 may have common inputs.
W27E010
Publication Release Date: June 2000
- 3 - Revision A6
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE = V
IH
. In
standby mode, all outputs are in a high impedance state, independent of OE and PGM .
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E010 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I
SB
), active current levels (I
CC
),
and transient current peaks produced by the falling and rising edges of CE. Transient current
magnitudes depend on the device output's capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have
a 0.1
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, X=V
IH
or V
IL
MODE
PINS
CE
OE
PGM
A0
A9 V
CC
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
X
V
CC
V
CC
D
OUT
Output Disable
V
IL
V
IH
X
X
X
V
CC
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
X
V
CC
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
X
V
CC
V
CC
High Z
Program
V
IL
V
IH
V
IL
X
X
V
CP
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
V
CP
V
PP
D
OUT
Program Inhibit
V
IH
X
X
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
IL
V
PE
V
CC
V
PE
FF (Hex)
Erase Verify
V
IL
V
IL
V
IH
X
X
V
CC
V
PE
D
OUT
Erase Inhibit
V
IH
X
X
X
X
V
CP
V
PE
High Z
Product Identifier-
Manufacturer
V
IL
V
IL
X
V
IL
V
HH
V
CC
V
CC
DA (Hex)
Product Identifier-Device
V
IL
V
IL
X
V
IH
V
HH
V
CC
V
CC
01 (Hex)
W27E010
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Ambient Temperature with Power Applied
-55 to +125
C
Storage Temperature
-65 to +125
C
Voltage on all Pins with Respect to Ground Except V
CC,
V
PP
and A9 Pins
-0.5 to V
CC
+0.5
V
Voltage on V
CC
Pin with Respect to Ground
-0.5 to +7
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Erase Characteristics
(T
A
= 25
C
5
C, V
CC
= 5.0V
10%, V
HH
= 14V)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Erase Current
I
CP
CE = V
IL,
OE = V
IH,
PGM = V
IL
, A9 = V
HH
-
-
30
mA
V
PP
Erase Current
I
PP
CE = V
IL,
OE = V
IH,
PGM = V
IL
, A9 = V
HH
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Erase Voltage
V
ID
-
13.75
14.0
14.25
V
V
PP
Erase Voltage
V
PE
-
13.75
14.0
14.25
V
V
CC
Supply Voltage (Erase)
V
CE
-
4.5
5.0
5.5
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E010
Publication Release Date: June 2000
- 5 - Revision A6
CAPACITANCE
(V
CC
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0 to 3.0V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V/1.5V
Output Load
C
L
= 30 pF,
I
OH
/I
OL
= -0.4 mA/2.1 mA
AC Test Load and Waveforms
+1.3V
3.3K ohm
100 pF for 90/120 nS (Including Jig and Scope)
D
(IN914)
OUT
30 pF for 45/55/70 nS (Including Jig and Scope)
Inpu
t
3.0V
0V
1.5V
Test Point
Test Point
1.5V
Output
W27E010
- 6 -
READ OPERATION DC CHARACTERISTICS
(Vcc = 5.0V
10%)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= 0V to V
CC
-5
-
5
A
Output Leakage Current
I
LO
V
OUT
= 0V to V
CC
-10
-
10
A
Standby V
CC
Current
(TTL input)
I
SB
CE = V
IH
-
-
1.0
mA
Standby V
CC
Current
(CMOS input)
I
SB
1
CE = V
CC
0.2V
-
5
100
A
V
CC
Operating Current
I
CC
CE = V
IL
I
OUT
= 0 mA
f = 5 MHz
-
-
30
mA
V
PP
Operating Current
I
PP
V
PP
= V
CC
-
-
10
A
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.0
-
V
CC
+0.5
V
Output Low Voltage
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
V
PP
Operating Voltage
V
PP
-
V
CC -
0.7
-
V
CC
V
READ OPERATION AC CHARACTERISTICS
(V
CC
= 5.0V
10%, for 70, 90 and 120 nS; V
CC
= 5.0V
5% for 45, 55 nS, T
A
= 0 to 70
C)
PARAMETER
SYM. W27E010-45 W27E010-55 W27E010-70 W27E010-90 W27E010-12
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
T
RC
45
-
55
-
70
-
90
-
120
-
nS
Chip Enable Access Time
T
CE
-
45
-
55
-
70
-
90
-
120
nS
Address Access Time
T
ACC
-
45
-
55
-
70
-
90
-
120
nS
Output Enable Access
Time
T
OE
-
20
-
25
-
30
-
40
-
55
nS
OE High to High-Z Output
T
DF
-
20
-
20
-
25
-
25
-
30
nS
Output Hold from Address
Change
T
OH
0
-
0
-
0
-
0
-
0
-
nS
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E010
Publication Release Date: June 2000
- 7 - Revision A6
DC PROGRAMMING CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 25
C
5
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-
-
10
A
V
CC
Program Current
I
CP
CE = V
IL,
OE =
V
IH,
PGM = V
IL
-
-
30
mA
V
PP
Program Current
I
PP
CE = V
IL,
OE =
V
IH,
PGM = V
IL
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
V
ID
-
11.5
12.0
12.5
V
V
PP
Program Voltage
V
PP
-
11.75
12.0
12.25
V
V
CC
Supply Voltage (Program)
V
CP
-
4.5
5.0
5.5
V
AC PROGRAMMING/ERASE CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 25
C
5
C)
PARAMETER
SYM.
LIMITS
UNIT
MIN.
TYP.
MAX.
V
PP
Setup Time
T
VPS
2.0
-
-
S
Address Setup Time
T
AS
2.0
-
-
S
Data Setup Time
T
DS
2.0
-
-
S
PGM Program Pulse Width
T
PWP
95
100
105
S
PGM Erase Pulse Width
T
PWE
95
100
105
mS
Data Hold Time
T
DH
2.0
-
-
S
OE Setup Time
T
OES
2.0
-
-
S
Data Valid from OE
T
OEV
-
-
150
nS
OE High to Output High Z
T
DFP
0
-
130
nS
Address Hold Time after PGM High
T
AH
0
-
-
S
Address Hold Time (Erase)
T
AHE
2.0
-
-
S
CE Setup Time
T
CES
2.0
-
-
S
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E010
- 8 -
TIMING WAVEFORMS
AC Read Waveform
CE
Outputs
T
High Z
High Z
Valid Output
CE
T
OE
T
ACC
T
OH
T
DF
Address
Address Valid
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
OE
Erase Waveform
Address
Read
SID
Device
Read
SID
A9 = 12.0V
Others = V
IL
A0 = V
IL
Data
Chip Erase
A9 = 14.0V
Erase Verify
Address
Stable
T
AS
DA
01
Data All One
14.0V
5.0V
A0=VIH
5V
Read Verify
Blank Check
Manufacturer
Address
Stable
Address
Stable
Others=VIL
Others = V
IL
T
AS
T
AS
T
AHC
T
DS
T
DH
T
VPS
T
DFP
D
OUT
D
OUT
D
OUT
T
AH
T
ACC
V
IH
V
IL
V
PP
CE
OE
PGM
T
CE
T
OE
T
OE
T
OES
T
OEV
T
PWE
T
CES
T
OE
V
IH
V
IL
V
IH
V
IL
W27E010
Publication Release Date: June 2000
- 9 - Revision A6
Timing Waveforms, Continued
Programming Waveform
Address
Data
12.0V
5.0V
CE
Address Stable
Program
Read
Verify
Address Stable
Address Valid
Verify
Data In Stable
5V
Program
D
OUT
T
AH
D
OUT
D
OUT
T
DH
T
DS
T
VPS
T
CES
T
ACC
T
DFP
T
AS
V
IH
V
IL
V
IH
V
IL
V
PP
OE
T
OES
T
OEV
T
OE
V
IH
V
IL
PGM
T
PWP
V
IH
V
IL
W27E010
- 10 -
SMART PROGRAMMING ALGORITHM
Start
Address = First Location
Vcc = 5V
Vpp = 12V
X = 0
Increment X
X = 25?
Verify
One Byte
Last
Address?
Vcc = 5V
Vpp = 5V
Compare
All Bytes to
Original Data
Pass
Device
Increment
Address
No
Fail
Yes
Pass
Fail
Fail
Fail
Device
Verify
One Byte
Program One 100 S Pulse
No
Pass
Yes
Pass
W27E010
Publication Release Date: June 2000
- 11 - Revision A6
SMART ERASE ALGORITHM
Start
Vcc = 5V
Vpp = 14V
Increment X
Last
Address?
Vcc = 5V
Vpp = 5V
Compare
All Bytes to
FFs (HEX)
Pass
Device
Increment
Address
No
Fail
Fail
Fail
Device
X = 0
A9 = 14V; A0 = V
Chip Erase 100 mS Pulse
Address = First Location
Erase
Verify
X = 20?
No
Yes
Pass
Pass
Yes
IL
W27E010
- 12 -
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
POWER SUPPLY
CURRENT MAX.
(mA)
STANDBY V
CC
CURRENT MAX.
(
A)
PACKAGE
W27E010-45
45
30
100
600 mil DIP
W27E010-55
55
30
100
600 mil DIP
W27E010-70
70
30
100
600 mil DIP
W27E010-90
90
30
100
600 mil DIP
W27E010-12
120
30
100
600 mil DIP
W27E010S-45
45
30
100
450 mil SOP
W27E010S-55
55
30
100
450 mil SOP
W27E010S-70
70
30
100
450 mil SOP
W27E010S-90
90
30
100
450 mil SOP
W27E010S-12
120
30
100
450 mil SOP
W27E010P-45
45
30
100
32-pin PLCC
W27E010P-55
55
30
100
32-pin PLCC
W27E010P-70
70
30
100
32-pin PLCC
W27E010P-90
90
30
100
32-pin PLCC
W27E010P-12
120
30
100
32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
W27E010
Publication Release Date: June 2000
- 13 - Revision A6
PACKAGE DIMENSIONS
32-pin P-DIP
Seating Plane
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
32
1
16
17
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
Notes:
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
1.37
1.22
0.054
0.048
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.050
1.27
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.540
0.555
0.550
13.84
14.10
13.97
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.650
1.660
41.91
42.16
0
15
0.085
2.16
0.650
0.630
16.00
16.51
15
0
32-pin SO Wide Body
1
17
32
16
y
e
D
S
Seating Plane
b
A
A
E H
L
L
E
E
1
c
e
1
1
e
A
2
See Detail F
Detail F
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and are determined at the mold parting line.
.
Notes:
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
L
E
1
2
E
0.118
3.00
0
10
10
0
S
0.20
0.15
0.008
0.006
0.012
0.31
0.004
0.101
0.014
0.106
0.016
0.111
0.020
2.57
0.36
0.10
2.69
0.41
2.82
0.51
0.047
0.004
0.805
0.055
0.817
0.063
1.19
20.45
1.40
20.75
1.60
0.556
0.556
0.546
14.38
14.12
13.87
0.10
11.43
11.30
11.18
0.450
0.445
0.440
0.58
0.79
0.99
0.023
0.031
0.039
1.12
1.27
1.42
0.044
0.050
0.056
0.91
0.036
W27E010
- 14 -
Package Dimensions, Continued
32-Lead PLCC
L
c
1
b
2
A
H
E
E
e
b
D
H
D
y
A
A
1
Seating Plane
E
G
G
D
1
13
14
20
29
32
4
5
21
30
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final
visual inspection sepc.
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
1
2
E
b
1
G
D
3.56
0.50
H
D
G
E
0.020
0.140
2.80
2.67
2.93
0.71
0.66
0.81
0.41
0.46
0.56
0.20
0.25
0.35
13.89
13.97
14.05
11.35
11.43
11.51
1.27
12.45
12.95
13.46
0.530
0.510
0.490
0.050
0.453
0.450
0.447
0.553
0.550
0.547
0.014
0.010
0.008
0.022
0.018
0.016
0.032
0.026
0.028
0.115
0.105
0.110
1.12
1.42
0.044
0.056
0
10
10
0
9.91
10.41
10.92
14.86
14.99
15.11
12.32
12.45
12.57
1.91
2.29
0.004
0.095
0.090
0.075
0.495
0.490
0.485
0.595
0.590
0.585
0.430
0.410
0.390
0.10
2.41
W27E010
Publication Release Date: June 2000
- 15 - Revision A6
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A6
Jun. 2000
5
Modify Input Pulse Levels in AC Test Conditions
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou
t notice.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou
t notice.