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W27E257
32K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: January 1997
- 1 -
Revision A3
GENERAL DESCRIPTION
The W27E257 is a high-speed, low-power Electrically Erasable and Programmable Read Only
Memory organized as 32768
8 bits that operates on a single 5 volt power supply. The W27E257
provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the
W27E256.
FEATURES
High speed access time:
100/120/150 nS (max.)
Read operating current: 15 mA (typ.)
Erase/Programming operating current
1 mA (typ.)
Standby current: 5
A (typ.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 28-pin 600 mil DIP and
32-pin PLCC
PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
NC
Q0
5
6
7
8
9
10
11
12
13
1
4
4
3
2
1
3
2
3
1
3
0 29
28
27
26
25
24
23
22
21
32-pin
PLCC
Q
1
Q
2
N
C
Q
3
Q
4
Q
5
G
N
D
26
27
28
1
2
3
4
5
6
7
8
21
22
23
24
25
16
17
18
19
20
9
10
11
12
13
14
15
Q3
CE
Q7
Q6
Q5
Q4
A9
A11
OE
A10
A14
A13
A8
1
5
1
6
1
7
1
8
1
9
2
0
GND
Q2
Q1
A0
A1
A2
A3
A4
A5
A6
A7
A12
V
Q0
PP
V
CC
A
7
N
C
A
1
2
V
P
P
A
1
4
A
1
3
V
C
C
A8
A9
A11
NC
OE
A10
Q7
CE
Q6
28-pin
DIP
BLOCK DIAGRAM
CE
OE
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
A0
.
.
A14
V
GND
CC
VPP
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A14
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
V
PP
Program/Erase Supply Voltage
V
CC
Power Supply
GND
Ground
NC
No Connection
W27E257
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE , if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), OE = V
IH
(2V or above but
lower than V
CC
), A9 = V
HH
(14V), A0 = V
IL
(0.8V or below but higher than GND), and all other
address pins equal V
IL
and data input pins equal V
IH
. Pulsing CE low starts the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE = V
IH
, and OE =
V
IL
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), OE = V
IH
, the address pins equal the desired address, and the input pins
equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully
programmed with the desired data. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE = V
IH
,
and OE = V
IL
.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
IH
, erasing or programming of non-target chips is inhibited, so that except for the
CE and OE pins, the W27E257 may have common inputs.
W27E257
Publication Release Date: January 1997
- 3 -
Revision A3
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE = V
IH
. In
standby mode, all outputs are in a high impedance state, independent of OE .
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E257 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, X = V
IH
or V
IL
)
MODE
PINS
CE
OE
A0
A9
V
CC
V
PP
OUTPUTS
Read
V
IL
V
IL
X
X
V
CC
V
CC
D
OUT
Output Disable
V
IL
V
IH
X
X
V
CC
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
V
CC
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
V
CC
V
CC
High Z
Program
V
IL
V
IH
X
X
V
CP
V
PP
D
IN
Program Verify
V
IH
V
IL
X
X
V
CP
V
PP
D
OUT
Program Inhibit
V
IH
V
IH
X
X
V
CP
V
PP
High Z
Erase
V
IL
V
IH
V
IL
V
PE
V
CC
V
PE
D
IH
Erase Verify
V
IH
V
IL
X
X
V
CC
V
PE
D
OUT
Erase Inhibit
V
IH
V
IH
X
X
V
CP
V
PP
High Z
Product Identifier-manufacturer
V
IL
V
IL
V
IL
V
HH
V
CC
V
CC
DA (Hex)
Product Identifier-device
V
IL
V
IL
V
IH
V
HH
V
CC
V
CC
02 (Hex)
W27E257
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Ambient Temperature with Power Applied
-55 to +125
C
Storage Temperature
-65 to +125
C
Voltage on all pins with Respect to Ground Except V
PP,
A9
and V
CC
pins
-0.5 to V
CC
+0.5
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on V
CC
Pin with Respect to Ground
-0.5 to +7
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Erase Characteristics
(T
A
= 25
C
5
C, V
CC
= 5.0V
10%)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Erase Current
I
CP
CE = V
IL
-
-
30
mA
V
PP
Erase Current
I
PP
CE = V
IL
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
-
A9 Erase Voltage
V
ID
-
13.75
14
14.25
V
V
PP
Erase Voltage
V
PE
-
13.75
14
14.25
V
V
CC
Supply Voltage (Erase)
V
CE
-
4.5
5.0
5.5
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
CAPACITANCE
(V
CC
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
W27E257
Publication Release Date: January 1997
- 5 -
Revision A3
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0.45V to 2.4V
Input Rise and Fall Times
10 nS
Input and Output Timing Reference Level
0.8V/2.0V
Output Load
C
L
= 100 pF, I
OH
/I
OL
= -0.4 mA/2.1 mA
AC Test Load and Waveform
+1.3V
3.3K ohm
100 pF (Including Jig and Scope)
D
(IN914)
OUT
Input
2.4V
0.45V
2.0V
0.8V
2.0V
0.8V
Test Points
Test Points
Output