W27E512
64K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: June 2000
- 1 - Revision A9
GENERAL DESCRIPTION
The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 65536
8 bits that operates on a single 5 volt power supply. The W27E512
provides an electrical chip erase function.
FEATURES
High speed access time:
45/55/70/90/120/150 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current
30 mA (max.)
Standby current: 1 mA (max.)
Single 5V power supply
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available p
ackages: 28-pin 600 mil DIP, 330 mil
SOP, TSOP and 32-pin PLCC
PIN CONFIGURATIONS
26
27
28
1
2
3
4
5
6
7
8
21
22
23
24
25
16
17
18
19
20
9
10
11
12
13
14
15
Q3
CE
Q7
Q6
Q5
Q4
A9
A11
OE/Vpp
A10
A14
A13
A8
GND
Q2
Q1
A0
A1
A2
A3
A4
A5
A6
A7
A12
Q0
V
CC
28-pin
DIP
A15
A6
A5
A4
A3
A2
A1
A0
NC
Q0
5
6
7
8
9
10
11
12
13
1
4
4 3 2 1 3
2
3
1
3
0 29
28
27
26
25
24
23
22
21
32-pin
PLCC
Q
1
Q
2
N
C
Q
3
Q
4
Q
5
G
N
D
1
5
1
6
1
7
1
8
1
9
2
0
A
7
N
C
A
1
2
A
1
4
A
1
3
V
C
C
A8
A9
A11
NC
OE/Vpp
A10
Q7
CE
Q6
A
1
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-pin
TSOP
Q3
CE
Q7
Q6
Q5
Q4
A10
GND
Q2
Q1
A0
A1
A2
Q0
A9
A11
OE/Vpp
A14
A13
A8
A3
A4
A5
A6
A7
A12
V
CC
A15
BLOCK DIAGRAM
CE
OE/V
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
A0
.
.
GND
V
CC
PP
A15
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
-
A15
Address Inputs
Q0
-
Q7
Data Inputs/Outputs
CE
Chip Enable
OE /V
PP
Output Enable, Program/Erase
Supply Voltage
V
CC
Power Supply
GND
Ground
NC
No Connection
W27E512
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E512 has two control functions, both of which produce data
at the outputs. CE is for power control and chip select. OE /V
PP
controls the output buffer to gate data
to the output pins. When addresses are stable, the address access time (T
ACC
) is equal to the delay
from CE to output (T
CE
), and data are available at the outputs T
OE
after the falling edge of OE /V
PP
,
if T
ACC
and T
CE
timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when OE /V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), A9 = V
PE
(14V), A0
low, and all other address pins low and data input pins high. Pulsing CE low starts the erase
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V
CC
=
V
CE
(3.75V), CE low, and OE /V
PP
low.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when OE /V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), the address pins equal the desired addresses, and the input pins equal the
desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if OE /V
PP
low
and CE low.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the
CE and OE/V
PP
pins, the W27E512 may have common inputs.
W27E512
Publication Release Date: June 2000
- 3 - Revision A9
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE high. In standby
mode, all outputs are in a high impedance state, independent of OE /V
PP
.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E512 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
F electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, V
CE
= 5V, X = V
IH
or V
IL
)
MODE
PINS
CE
OE/V
PP
A0
A9
V
CC
OUTPUTS
Read
V
IL
V
IL
X
X
V
CC
D
OUT
Output Disable
V
IL
V
IH
X
X
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
V
CC
High Z
Program
V
IL
V
PP
X
X
V
CP
D
IN
Program Verify
V
IL
V
IL
X
X
V
CC
D
OUT
Program Inhibit
V
IH
V
PP
X
X
V
CP
High Z
Erase
V
IL
V
PE
V
IL
V
PE
V
CE
D
IH
Erase Verify
V
IL
V
IL
X
X
3.75
D
OUT
Erase Inhibit
V
IH
V
PE
X
X
V
CE
High Z
Product Identifier-manufacturer
V
IL
V
IL
V
IL
V
HH
V
CC
DA (Hex)
Product Identifier-device
V
IL
V
IL
V
IH
V
HH
V
CC
08 (Hex)
W27E512
- 4 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Ambient Temperature with Power Applied
-55 to +125
C
Storage Temperature
-65 to +125
C
Voltage on all Pins with Respect to Ground Except
OE /V
PP,
A9 and V
CC
Pins
-0.5 to V
CC
+0.5
V
Voltage on OE /V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Voltage V
CC
Pin with Respect to Ground
-0.5 to +7
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Erase Characteristics
(T
A
= 25
C
5
C, V
CC
= 5.0V
10%)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Erase Current
I
CP
CE = V
IL,
OE /V
PP
= V
PE
-
-
30
mA
V
PP
Erase Current
I
PP
CE = V
IL,
OE /V
PP
= V
PE
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
-
A9 Erase Voltage
V
ID
-
13.25
14
14.25
V
V
PP
Erase Voltage
V
PE
-
13.25
14
14.25
V
V
CC
Supply Voltage (Erase)
V
CE
-
4.5
5.0
5.5
V
V
CC
Supply Voltage
(Erase Verify)
V
CE
-
3.5
3.75
4.0
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E512
Publication Release Date: June 2000
- 5 - Revision A9
CAPACITANCE
(V
CC
= 5V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
0 to 3.0V
Input Rise and Fall Times
5 nS
Input and Output Timing Reference Level
1.5V/1.5V
Output Load
C
L
= 30 pF,
I
OH
/I
OL
= -0.4 mA/2.1 mA
AC Test Load and Waveforms
+1.3V
3.3K ohm
100 pF for 90/120/150 nS (Including Jig and Scope)
D
(IN914)
OUT
30 pF for 45/55/70 nS (Including Jig and Scope)
Input
3.0V
0V
1.5V
Test Point
Test Point
1.5V
Output
W27E512
- 6 -
READ OPERATION DC CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 0 to 70
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= 0V to V
CC
-5
-
5
A
Output Leakage
Current
I
LO
V
OUT
= 0V to V
CC
-10
-
10
A
Standby V
CC
Current
(TTL input)
I
SB
CE = V
IH
-
-
1.0
mA
Standby V
CC
Current
(CMOS input)
I
SB1
CE = V
CC
0.2V
-
5
100
A
V
CC
Operating Current
I
CC
CE = V
IL
I
OUT
= 0 mA
f = 5 MHz
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.0
-
V
CC
+0.5
V
Output Low Voltage
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
READ OPERATION AC CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 0 to 70
C)
PARAMETER
SYM. W27E512-45 W27E512-55 W27E512-70 W27E512-90 W27E512-12 W27E512-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
T
RC
45
-
55
-
70
-
90
-
120
-
150
-
nS
Chip Enable
Access Time
T
CE
-
45
-
55
-
70
-
90
-
120
-
150
nS
Address Access
Time
T
ACC
-
45
-
55
-
70
-
90
-
120
-
150
nS
Output Enable
Access Time
T
OE
-
20
-
25
-
30
-
40
-
55
-
60
nS
OE
/VPP High to
High-Z Output
T
DF
-
20
-
20
-
30
-
30
-
30
-
50
nS
Output Hold from
Address Change
T
OH
0
-
0
-
0
-
0
-
0
-
0
-
nS
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E512
Publication Release Date: June 2000
- 7 - Revision A9
DC PROGRAMMING CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 25
C
5
C)
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MIN.
TYP.
MAX.
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10
-
10
A
V
CC
Program Current
I
CP
CE
= V
IL
,
OE /V
PP
= V
PP
-
-
30
mA
V
PP
Program Current
I
PP
CE = V
IL
,
OE
/V
PP
= V
PP
-
-
30
mA
Input Low Voltage
V
IL
-
-0.3
-
0.8
V
Input High Voltage
V
IH
-
2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
V
ID
-
11.5
12.0
12.5
V
V
PP
Program Voltage
V
PP
-
11.75
12.0
12.25
V
V
CC
Supply Voltage (Program)
V
CP
-
4.5
5.0
5.5
V
AC PROGRAMMING/ERASE CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 25
C
5
C)
PARAMETER
SYM.
LIMITS
UNIT
MIN. TYP. MAX.
OE /V
PP
Pulse Rise Time
T
PRT
50
-
-
nS
Data Setup Time
T
DS
2.0
-
-
S
CE Program Pulse Width
T
PWP
95
100
105
S
CE Erase Pulse Width
T
PWE
95
100
105
mS
Data Hold Time
T
DH
2.0
-
-
S
OE /V
PP
Setup Time
T
OES
2.0
-
-
S
OE /V
PP
Hold Time
T
OEH
2.0
-
-
S
Data Valid from
CE
T
DV1
25
-
1
S
Data Valid from Address Change
T
DV2
25
-
1
S
CE High to Output High Z
T
DFP
0
-
130
nS
Address Setup Time
T
AS
2.0
-
-
S
Address Hold Time
T
AH
0
-
-
S
Address Hold Time after CE High (Erase)
T
AHC
2.0
-
-
S
OE
/V
PP
Valid after
CE
High
T
VS
2.0
-
-
S
OE
/V
PP
Recovery Time
T
VR
2.0
-
-
S
Address Access Time during Erase Verify (V
CC
= 3.75V)
T
ACV
-
-
250
nS
Output Enable Access Time during Erase Verify (V
CC
= 3.75V)
T
OEV
-
-
150
nS
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
W27E512
- 8 -
TIMING WAVEFORMS
AC Read Waveform
OE/Vpp
Outputs
High Z
High Z
Valid Output
T
OE
T
ACC
T
OH
T
DF
V
IH
V
IL
Address
CE
Address Valid
T
CE
V
IL
V
IH
V
IH
V
IL
Erase Waveform
Address
Data
Vcc
V
IH
V
IL
5V
Read
Company
SID
Read
Device
SID
A9=12.0V
Chip Erase
A9= 14.0V
Blank Check
Read Verify
Address Valid
T
ACC
T
ACC
DA
08
Data All One
T
AS
T
AHC
T
ACV
D
OUT
T
ACV
T
ACC
T
DS
T
DH
T
VCS
3.75V
Erase Verify
OE/Vpp
CE
V
IH
V
IH
V
IL
V
IL
14.0V
T
OE
T
OE
T
OES
T
PRT
T
OEH
T
OEV
V
IH
T
OE
V
IH
T
CE
T
VS
T
PWE
T
VR
Address Valid
Address Valid
Address Valid
Always=V
IL
IL
Others=V
IL
IL
Others=V
IL
A0=VIH
D
OUT
D
OUT
Others=V
A0=V
=250 nS
=250 nS
=150 nS
W27E512
Publication Release Date: June 2000
- 9 - Revision A9
Timing Waveforms, continued
Programming Waveform
Address
Data
OE/Vpp
CE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
12.0V
V
IH
V
IL
Program
Program
Verify
Address Stable
Address
Valid
Read
Verify
Data
Out
Data
Out
Data In Stable
Data In
Stable
T
AS
T
AH
T
AS
T
AH
T
OH
T
DS
T
DH
T
DS
T
DH
T
DV1
T
DV2
T
DFP
T
ACC
T
OH
T
OE
T
CE
V
IL
V
IL
T
VR
T
OEH
T
PWP
T
T
PRT
CE should not be toggled
during program verify period
OES
Address
Valid
Address
Stable
Address
Stable
W27E512
- 10 -
SMART PROGRAMMING ALGORITHM 1
Start
Address = First Location
Vcc = 5.0V
OE/Vpp = 12V
Program One 100 S Pulse
Last
Address?
Address = First Location
X = 0
Verify
Byte
Program One 100 S Pulse
Vcc = 5.0V
OE/Vpp = V
IL
Compare
All Bytes to
Data
Original
Device
Passed
Pass
Yes
Increment
Address
No
Increment
Address
Last
Address?
No
Pass
Yes
Increment X
Fail
X = 25 ?
No
Device
Yes
Fail
Failed
W27E512
Publication Release Date: June 2000
- 11 - Revision A9
SMART PROGRAMMING ALGORITHM 2
Start
Address = First Location
Vcc = 5.0V
Program One 100 S Pulse
Compare
All Bytes to
Data
Original
Device
Passed
Pass
Increment
Address
No
Increment X
Fail
Device
Failed
X = 0
PP
X = 25?
Yes
Last Address
?
Yes
No
Pass
Fail
Fail
Pass
OE/V = 12V
OE/V = V
PP
IL
Verify One Byte
OE/V = V
PP
IL
Verify One Byte
W27E512
- 12 -
SMART ERASE ALGORITHM
Start
Vcc = 5V
OE/Vpp = 14V
Increment X
Last
Address?
Vcc = 5V
OE/Vpp = V
Compare
All Bytes to
FFs (HEX)
Pass
Device
Increment
Address
No
Fail
Fail
Fail
Device
X = 0
A9 = 14V; A0 = V
Chip Erase 100 mS Pulse
Address = First Location
Erase
Verify
X = 20 ?
No
Yes
Pass
Pass
Yes
IL
Vcc = 3.75V
OE/Vpp = V
IL
IL
W27E512
Publication Release Date: June 2000
- 13 - Revision A9
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (
A)
PACKAGE
W27E512-45
45
30
100
600 mil DIP
W27E512-55
55
30
100
600 mil DIP
W27E512-70
70
30
100
600 mil DIP
W27E512-90
90
30
100
600 mil DIP
W27E512-12
120
30
100
600 mil DIP
W27E512-15
150
30
100
600 mil DIP
W27E512S-45
45
30
100
300 mil SOP
W27E512S-55
55
30
100
300 mil SOP
W27E512S-70
70
30
100
300 mil SOP
W27E512S-90
90
30
100
300 mil SOP
W27E512S-12
120
30
100
300 mil SOP
W27E512S-15
150
30
100
300 mil SOP
W27E512Q-45
45
30
100
28-pin TSOP
W27E512Q-55
55
30
100
28-pin TSOP
W27E512Q-70
70
30
100
28-pin TSOP
W27E512Q-90
90
30
100
28-pin TSOP
W27E512Q-12
120
30
100
28-pin TSOP
W27E512Q-15
150
30
100
28-pin TSOP
W27E512P-45
45
30
100
32-pin PLCC
W27E512P-55
55
30
100
32-pin PLCC
W27E512P-70
70
30
100
32-pin PLCC
W27E512P-90
90
30
100
32-pin PLCC
W27E512P-12
120
30
100
32-pin PLCC
W27E512P-15
150
30
100
32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W27E512
- 14 -
PACKAGE DIMENSIONS
28-pin P-DIP
Seating Plane
1. Dimensions D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
1.63
1.47
0.064
0.058
Notes:
Symbol
Min. Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.060
1.52
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.540
0.550
0.545
13.72
13.97
13.84
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.460
1.470
37.08
37.34
0
15
0.090
2.29
0.650
0.630
16.00
16.51
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
15
0
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
28
1
15
14
28-pin SO Wide Body
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimensions D & E include mold mismatch
and determined at the mold parting line.
.
0.25
0.20
0.010
0.008
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
0.014
0.36
0.112
2.85
0.004
0.093
0.014
0.098
0.016
0.103
0.020
2.36
0.36
0.10
2.49
0.41
2.62
0.51
0.059
0.004
0
10
0.713
0.067
0.733
0.075
1.50
18.11
1.70
18.62
1.91
0.477
0.465
0.453
12.12
11.81
11.51
0
10
0.10
8.53
8.41
8.28
0.336
0.331
0.326
0.71
0.91
1.12
0.028
0.036
0.044
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
1.12
1.27
1.42
0.044
0.050
0.056
1.19
0.047
2
1
A
28
15
14
1
e
S
E
H
b
Seating Plane
A A
y
L
L
e
c
See Detail F
D
E
E
1
1
e
Detail F
A
b
c
D
e
H
E
L
y
A
A
L
E
1
2
E
S
W27E512
Publication Release Date: June 2000
- 15 - Revision A9
Package Dimensions, continued
28-pin Standard Type One TSOP
A
A
A
2
1
L
L
1
Y
c
E
H
D
D
b
e
Controlling dimension: Millimeters
Min.
Dimension In Inches
Nom.
Max.
Min.
Nom.
Max.
Symbol
1.20
0.05
0.15
1.05
1.00
0.95
0.17
0.10
11.70
7.90
13.20
0.50
0.00
0
0.20
0.27
0.15
0.21
11.80
11.90
8.00
8.10
13.40
13.60
0.55
0.60
0.70
0.25
0.10
3
5
0.047
0.006
0.041
0.040
0.035
0.007
0.008
0.011
0.004
0.006
0.008
0.461
0.465
0.469
0.311
0.315
0.319
0.520
0.528
0.536
0.022
0.020
0.024
0.028
0.010
0.000
0.004
0
3
5
0.002
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
H
D
Dimension In mm
1
32-pin PLCC
L
c
1
b
2
A
H
E
E
e
b
D H
D
y
A
A
1
Seating Plane
E
G
G
D
1
13
14
20
29
32
4
5
21
30
Notes:
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
1
2
E
b
1
G
D
3.56
0.50
2.80
2.67
2.93
0.71
0.66
0.81
0.41
0.46
0.56
0.20
0.25
0.35
13.89
13.97
14.05
11.35
11.43
11.51
1.27
H
D
G
E
12.45
12.95
13.46
9.91
10.41
10.92
14.86
14.99
15.11
12.32
12.45
12.57
1.91
2.29
0.004
0.095
0.090
0.075
0.495
0.49
0
0.485
0.595
0.590
0.585
0.430
0.410
0.390
0.530
0.510
0.490
0.050
0.453
0.450
0.447
0.553
0.550
0.547
0.014
0.010
0.008
0.022
0.018
0.016
0.032
0.026
0.028
0.115
0.105
0.110
0.020
0.140
1. Dimension D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final visual
inspection spec.
1.12
1.42
0.044
0.056
0
10
10
0
0.10
2.41
W27E512
- 16 -
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A6
Apr. 1997
1, 13, 14
Add SOP package
A7
Feb. 1998
1, 2, 3, 5, 6, 13 Add 45/55 nS bining
A8
Nov. 1999
2, 3
Modify function description ( V
IL
and V
IH
):
V
IL
Low. V
IH
High.
4
Modify A9 and V
PP
Erase Voltage (V
ID
and V
PP
):
from 13.75V (min) to 13.25V (min)
6
Modify V
CC
description
A9
Jun. 2000
5
Modify Input Pulse Levels in AC Test Conditions
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou t notice.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou t notice.
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