W27L01

128K

× 8 ELECTRICALLY ERASABLE EPROM

Publication Release Date: February 20, 2003

- 1 -

Revision A3

1. GENERAL DESCRIPTION

The W27L01 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131,072

× 8 bits. It requires only one supply in the range of 3.3V ± 10% in

normal read mode. The W27L01 provides an electrical chip erase function.

2. FEATURES

Single power supply voltage:

3.3V

±10%

High speed access time:

70/90 nS (max.)

Read operating current: 15 mA (max.)

Erase/Programming operating current:

30 mA (max.)

Standby current: 20

µA (max.)

+12V erase/programming voltage

Fully static operation

All inputs and outputs directly TTL/CMOS

compatible

Three-state outputs

Available

packages: 32-lead PLCC, 32-lead

STSOP and 32-lead TSOP.

3. PIN CONFIGURATIONS

A6
A5

A3
A2

5
6

7
8
9

10
11

12
13

4 3 2 1 3

A14

A13
A8
A9

#OE

A11

29
28
27
26

25
24
23
22
21

32-lead PLCC

#CE

A10

1
2
3
4
5

6
7
8
9

10
11
12

14
15

#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3

32-lead STSOP

A15
A12

A7
A6

A5
A4

#PGM

A14

A13

A11

32
31
30
29
28
27
26
25
24

22
21
20
19
18
17

A16

V SS

32-lead TSOP/

4. BLOCK DIAGRAM

Vss

CONTROL

OUTPUT

BUFFER

DECODER

CORE

ARRAY

#CE

#OE

A16

#PGM

5. PIN DESCRIPTION

SYMBOL DESCRIPTION
A0

- A16

Address Inputs

- Q7

Data Inputs/Outputs

#CE

Chip Enable

#OE

Output Enable

#PGM

Program Enable

Program/Erase Supply Voltage

Power Supply

Vss Ground

NC No

Connection

W27L01

- 2 -

6. FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27L01 has two control functions and both of these produce data at
the outputs.
#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T

ACC

) is equal to the delay from #CE to output

), and data are available at the outputs T

after the falling edge of #OE, if T

ACC

and T

timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27L01 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an
EPROM writer with a special erase algorithm.
Erase mode is entered when V

is raised to V

(12V), V

= V

(5V), #CE low, #OE high, A9 = V

(12V), A0 low

and all other address pins low and data input pins high. Pulsing #PGM low starts the

erase operation.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V

= V

(5V), #CE low, and #OE low,

#PGM

high

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V

is raised to V

(12V),

= V

(5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins

equal the desired inputs. Pulsing #PGM low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed
with the desired data or not. Hence, after each byte is programmed, a program verify operation should
be performed. The program verify mode automatically ensures a substantial program margin. This mode
will be entered after the program operation if V

= V

(12V), #CE low, #OE low

and #PGM high.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the
#CE, the W27L01 may have common inputs.

Standby Mode

The standby mode significantly reduces V

current. This mode is entered when #CE high. In standby

mode, all outputs are in a high impedance state, independent of #OE and #PGM.

W27L01

Publication Release Date: February 20, 2003

- 3 -

Revision A3

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27L01 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I

), active current levels (I

), and

transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1

µF ceramic

capacitor connected between its V

and Vss. This high frequency, low inherent-inductance capacitor

should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7

µF

electrolytic capacitor should be placed at the array's power supply connection between V

and Vss.

The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

Table of Operating Modes

= 3.3V

±10%, Vpp = Vp

= V

= 12V, V

= V

= 5V, X = V

or V

PINS

MODE

#CE

#OE

#PGM A0 A9 V

OUTPUTS

Read V

X X X

OUT

Output Disable

X X X

High Z

Standby (TTL)

X X X

High Z

Standby (CMOS)

±0.3V

High Z

Program V

X X V

Program Verify

X X V

OUT

Program Inhibit

High Z

Erase V

FF (Hex)

Erase Verify

X X V

OUT

Erase Inhibit

High Z

Product
Identifier-Manufacturer

X V

DA (Hex)

Product Identifier-Device

X V

01 (Hex)

W27L01

- 4 -

7. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING

UNIT

Operation Temperature

0 to +70

°C

Storage Temperature

-65 to +125

°C

Voltage on all Pins with Respect to Ground Except V

, V

and A9 Pins

-0.5 to V

+0.5

Voltage on V

Pin with Respect to Ground

-0.5 to +7.0

Voltage on V

Pin with Respect to Ground

-0.5 to +14.5

Voltage on A9 Pin with Respect to Ground

-0.5 to +14.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Capacitance

= 3.3V

±10%, T

= 25

° C, f = 1 MHz)

PARAMETER SYMBOL

CONDITIONS MAX. UNIT

Input Capacitance

= 0V

Output Capacitance

OUT

= 0V

Read Operation DC Characteristics

= 3.3V

±10%, T

= 0 to 70

° C)

LIMITS

PARAMETER SYM.

CONDITIONS

MIN. TYP. MAX.

UNIT

Input Load Current

= 0V to V

-5 - 5

µA

Output Leakage Current

OUT

= 0V to V

-10 - 10

µA

Standby V

Current

(TTL input)

#CE = V

200

µA

Standby V

Current

(CMOS input)

SB1

#CE = V

±0.2V

- - 20

µA

Operating Current

#CE = V

, I

OUT

= 0 mA,

f = 5 MHz

- - 15

Operating Current

= V

- - 10

µA

Input Low Voltage

-0.3 - 0.6 V

Input High Voltage

- 2.0

+0.5

Output Low Voltage

= 1.6 mA

0.4

Output High Voltage

= -0.1 mA

2.4

Operating Voltage

- V

-0.7

W27L01

Publication Release Date: February 20, 2003

- 5 -

Revision A3

Program/Erase DC Characteristics

= 25

° C , V

= 5.0V

±10%, V

= 12V)

LIMITS

PARAMETER

SYM.

CONDITIONS

MIN. TYP. MAX.

UNIT

Input Load Current

= V

or V

-10 - 10

µA

Program Current

#CE = V

IL,

#OE =

IH,

#PGM = V

- - 30

Erase Current

#CE = V

IL,

#OE = V

IH,

#PGM = V

, A9 = V

- - 30

Program Current

#CE = V

IL,

#OE =

IH,

#PGM = V

- - 30

Erase Current

#CE = V

IL,

#OE = V

IH,

#PGM = V

, A9 = V

- - 30

Input Low Voltage

- -0.3

0.8

Input High Voltage

2.4 - 5.5 V

Output Low Voltage (Verify)

= 2.1 mA

0.45

Output High Voltage (Verify)

= -0.4 mA

2.4

A9 Silicon I.D. Voltage

11.5 12.0 12.5 V

A9 Erase Voltage

- 11.75

12.0

14.25

Program Voltage

- 11.75

12.0

12.25

Erase Voltage

- 11.75

12.0

14.25

Supply Voltage

(Program)

4.5 5.0 5.5 V

Supply Voltage (Erase)

4.5 5.0 5.5 V

Supply Voltage (Erase

Verify)

- 5.0 - V

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

W27L01

Publication Release Date: February 20, 2003

- 7 -

Revision A3

Read Operation AC Characteristics

= 3.3V

±10%, T

= 0 to 70

° C)

W27L01-70 W27L01-90

PARAMETER SYM.

MIN. MAX. MIN. MAX.

UNIT

Read Cycle Time

70 - 90 - nS

Chip Enable Access Time

- 70 - 90 nS

Address Access Time

ACC

- 70 - 90 nS

Output Enable Access Time

- 30 - 40 nS

#OE High to High-Z Output

- 25 - 25 nS

Output Hold from Address Change

0 - 0 - nS

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

AC Programming/Erase Characteristics

= 5.0V

±10%, T

= 25

° C)

LIMITS

PARAMETER

SYMBOL

MIN. TYP. MAX.

UNIT

Setup Time

VPS

2.0 - -

µS

Address Setup Time

2.0 - -

µS

Data Setup Time

2.0 - -

µS

#PGM Program Pulse Width

PWP

95 100 105

µS

#PGM Erase Pulse Width

PWE

95 100 105 mS

Data Hold Time

2.0 - -

µS

#OE Setup Time

OES

2.0 - -

µS

Data Valid from #OE

OEV

- -

150

#OE High to Output High Z

DFP

0 -

130

Address Hold Time after #PGM High

0 - -

µS

Address Hold Time (Erase)

AHE

2.0 - -

µS

#CE Setup Time

CES

2.0 - -

µS

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

W27L01

- 8 -

8. TIMING WAVEFORMS

AC Read Waveform

#CE

Outputs

High Z

Valid Output

ACC

Address

Address Valid

#OE

Erase Waveform

Address

Read

SID

Device

Read

SID

A9 = 12.0V

Others = V

A0 = V

Data

Chip Erase

A9 = 12.0V

Erase Verify

Address

Stable

Data All One

12.0V

5.0V

A0=VIH

Read Verify

Blank Check

Manufacturer

Address

Stable

Address

Stable

Others=VIL

Others = V

AHC

VPS

DFP

OUT

ACC

#CE

#OE

#PGM

OES

OEV

PWE

CES

= VDD

W27L01

- 12 -

11. ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY V

CURRENT MAX.

(

µA)

PACKAGE

W27L01P-70 70 15

32-Lead

PLCC

W27L01P-90 90 15

32-Lead

PLCC

W27L01Q-70 70 15

32-Lead

STSOP

W27L01Q-90 90 15

32-Lead

STSOP

W27L01T-70 70 15

32-Lead

TSOP

W27L01T-90 90 15

32-Lead

TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

W27L01

Publication Release Date: February 20, 2003

- 13 -

Revision A3

12. PACKAGE DIMENSIONS

32-Lead PLCC

D H

Seating Plane

Notes:

1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final

visual inspection sepc.

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

b
c

A
A

3.56

0.50

0.020

0.140

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.95

13.46

0.530

0.510

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

1.12

1.42

0.044

0.056

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.490

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.10

2.41

32-Lead STSOP (8 x 14 mm)

Min.

Dimension in Inches

Nom. Max. Min. Nom. Max.

Symbol

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.10

0.50

0.00

0.22

0.27

-----

0.21

12.40

8.00

14.00

0.50

0.60

0.70

0.80

0.10

0.047

0.006

0.041

0.040

0.035

0.007

0.009

0.010

0.004

-----

0.008

0.488

0.315

0.551

0.020

0.024

0.028

0.031

0.000

0.004

0.002

A
A

b
c

Dimension in mm

A
A

W27L01

- 14 -

Package Dimensions, continued

32-Lead TSOP (8 x 20 mm)

0.10(0.004)

Min.

Nom.

Max.

Min.

Nom.

Max.

Symbol

Note:

Controlling dimension: Millimeters

Dimension in Inches

0.047

0.006

0.041

0.039

0.037

0.007

0.008

0.009

0.005

0.006

0.007

0.720

0.724

0.728

0.311

0.315

0.319

0.780

0.787

0.795

0.020

0.016

0.020

0.024

0.031

0.000

0.004

0.002

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.12

18.30

7.90

19.80

0.40

0.00

0.20

0.23

0.15

0.17

18.40

18.50

8.00

8.10

20.00

20.20

0.50

0.60

0.80

0.10

Dimension in mm

W27L01

Publication Release Date: February 20, 2003

- 15 -

Revision A3

13. VERSION HISTORY

VERSION DATE PAGE

DESCRIPTION

Apr. 2001

Initial Issued

May 31, 2002

1, 5, 13

Modify Icc parameter from 10 mA to 15 mA

1, 13, 14 Add in DIP package

2, 3, 4, 6 Correct the Vcv(V

) as V

) under Erase Inhibit Mode

Modify the Pin of V

from V

In the

Erase Verify

Mode

Modify T

= 25

°C ±5°C to 25°C

Modify Erase Waveform

All

Delete V

= 5.0V

±10%

Feb. 20, 2003 1, 13, 14 Add in TSOP(8 x 20 mm) package

1, 12, 13 Delete DIP package

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

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