ChipFind - документация

Электронный компонент: W27L02Q-70

Скачать:  PDF   ZIP
W27L02
256K
8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: February 20, 2003
- 1 -
Revision A3
1. GENERAL DESCRIPTION
The W27L02 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 3.3V
10% in
normal read mode. The W27L02 provides an electrical chip erase function.
2. FEATURES
Wide range for power supply voltage:
3.3V
10%
High speed access time: 70/90 nS (max.)
Read operating current: 15 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20
A (max.)
+12V erase/programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available
packages: 32-lead PLCC and 32-lead
STSOP
3. PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4 3 2 1 3
2
3
1
3
0
A14
A13
A8
A9
#OE
A11
Q7
29
28
27
26
25
24
23
22
21
32-lead PLCC
V
s
s
1
5
1
6
1
7
1
8
1
9
2
0
A
1
V
D
D
#CE
A10
A
1
5
A
1
6
Q
3
A7
A
1
2
V
p
p
#
P
G
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
Q0
Q1
Q2
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
32-lead STSOP
A15
A12
A7
A6
A5
A4
#PGM
A14
A13
A8
V
DD
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A17
V SS
V
PP
7
4. BLOCK DIAGRAM
V
Vss
DD
V
PP
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
.
#CE
#OE
A0
.
.
A17
#PGM
5. PIN DESCRIPTION
SYMBOL DESCRIPTION
A1
- A17 Address Inputs
Q0
- Q7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#PGM
Program Enable
V
PP
Program/Erase Supply Voltage
V
DD
Power Supply
Vss Ground
NC No
Connection
W27L02
- 2 -
6. FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L02 has two control functions and both of these produce data at
the outputs.
#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from #CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of #OE, if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27L02 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an
EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise V
PP
to V
PE
(12V), V
DD
= V
CE
(5V), #CE low,
#OE high, A9 = V
HH
(12V), and all other address pins are kept at fixed low or high. Pulsing #PGM low
starts the erase operation. The other way is somewhat like flash, by programming two consecutive
commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex)
to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the #PGM pulse
widths of these two commands are different: One is 100
S, while the other is 100 mS. Please refer to
the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
DD
= V
PE
(5V), #CE low, and #OE low,
#PGM
high
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V),
V
DD
= V
CP
(5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins
equal the desired inputs. Pulsing #PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed
with the desired data or not. Hence, after each byte is programmed, a program verify operation should
be performed. The program verify mode automatically ensures a substantial program margin. This mode
will be entered after the program operation if V
PP
= V
PP
(12V), #CE low, #OE low
,
and #PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the
#CE, the W27L02 may have common inputs.
W27L02
Publication Release Date: February 20, 2003
- 3 -
Revision A3
Standby Mode
The standby mode significantly reduces V
DD
current. This mode is entered when #CE high. In standby
mode, all outputs are in a high impedance state, independent of #OE and #PGM.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L02 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
F ceramic
capacitor connected between its V
DD
and Vss. This high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7
F
electrolytic capacitor should be placed at the array's power supply connection between V
DD
and Vss.
The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
Table of Operating Modes
V
DD
= 3.3V
10%, Vpp = Vp
E
= V
HH
= 12V, V
CP
= V
PE
= V
CE
= 5V, X = V
IH
or V
IL
PINS
MODE
#CE
#OE
#PGM
A0 A9
OTER
ADDR
V
DD
V
PP
OUTPUTS
Read V
IL
V
IL
X X X X V
DD
V
DD
D
OUT
Output Disable
V
IL
V
IH
X X X X V
DD
V
DD
High Z
Standby (TTL)
V
IH
X X X
X X
V
DD
V
DD
High Z
Standby (CMOS)
V
DD
0.3V
X
X
X
X
X
V
DD
V
DD
High Z
Program V
IL
V
IH
V
IL
X X X V
CP
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X X X V
CP
V
PP
D
OUT
Program Inhibit
V
IH
X
X
X
X
X
V
CP
V
PP
High Z
Erase1 V
IL
V
IH
V
IL
V
IL
V
PE
V
CE
V
PE
FF (Hex)
V
IL
V
IH
V
IL
First command:
Addr. = 5555 (hex)
V
CE
V
CP
AA (Hex)
Erase2
Second command:
Addr. = 2AAA (hex)
V
CE
V
CP
10 (Hex)
Erase Verify
V
IL
V
IL
V
IH
X
X X
V
PE
V
PP
D
OUT
Erase Inhibit
V
IH
X
X
X
X
X
V
CE
V
PE
High Z
Product Identifier -
Manufacturer
V
IL
V
IL
X V
IL
V
HH
X
V
DD
V
DD
DA (Hex)
Product Identifier -
Device
V
IL
V
IL
X V
IH
V
HH
X
V
DD
V
DD
85 (Hex)
W27L02
- 4 -
8. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING
UNIT
Operation Temperature
0 to +70
C
Storage Temperature
-65 to +125
C
Voltage on all Pins with Respect to Ground Except V
DD,
V
PP
and A9 Pins
-0.5 to V
DD
+0.5 V
Voltage on V
DD
Pin with Respect to Ground
-0.5 to +7.0
V
Voltage on V
PP
Pin with Respect to Ground
-0.5 to +14.5
V
Voltage on A9 Pin with Respect to Ground
-0.5 to +14.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Capacitance
(V
DD
= 3.3V
10%, T
A
= 25
C, f = 1 MHz)
PARAMETER SYMBOL
CONDITIONS
MAX.
UNIT
Input Capacitance
C
IN
V
IN
= 0V
6
pF
Output Capacitance
C
OUT
V
OUT
= 0V
12
pF
Read Operation DC Characteristics
(V
DD
= 3.3V
10%, T
A
= 0 to 70
C)
LIMITS
PARAMETER SYM.
CONDITIONS
MIN. TYP. MAX.
UNIT
Input Load Current
I
LI
V
IN
= 0V to V
DD
-5 - 5
A
Output Leakage Current
I
LO
V
OUT
= 0V to V
DD
-10 - 10
A
Standby V
DD
Current
(TTL input)
I
SB
#CE = V
IH
-
-
200
A
Standby V
DD
Current
(CMOS input)
I
SB
1 #CE = V
DD
0.2V
- - 20
A
V
DD
Operating Current
I
CC
#CE = V
IL,
I
OUT
= 0 mA,
f = 5 MHz
- - 15 mA
V
PP
Operating Current
I
PP
V
PP
= V
DD
- - 10
A
Input Low Voltage
V
IL
- -0.3
-
0.6
V
Input High Voltage
V
IH
- 2.0
-
V
DD
+0.5 V
Output Low Voltage
V
OL
I
OL
= 1.6 mA
-
-
0.4
V
Output High Voltage
V
OH
I
OH
= -0.1 mA
2.4
-
-
V
V
PP
Operating Voltage
V
PP
- V
DD -
0.7 -
V
DD
V
W27L02
Publication Release Date: February 20, 2003
- 5 -
Revision A3
Electrical Chericteristics, continued
Program/Erase DC Characteristics
(T
A
= 25
C , V
DD
= 3.3V
10%, V
HH
= 12V)
LIMITS
PARAMETER
SYM.
CONDITIONS
MIN. TYP. MAX.
UNIT
Input Load Current
I
LI
V
IN
= V
IL
or V
IH
-10 - 10
A
V
DD
Program Current
I
CP
#CE = V
IL,
#OE =
V
IH,
#PGM = V
IL
- - 30
mA
V
DD
Erase Current
I
CE
#CE = V
IL,
#OE = V
IH,
#PGM = V
IL
, A9 = V
HH
- - 30
mA
V
PP
Program Current
I
PP
#CE = V
IL,
#OE =
V
IH,
#PGM = V
IL
- - 30
mA
V
PP
Erase Current
I
PE
#CE = V
IL,
#OE = V
IH,
#PGM = V
IL
, A9 = V
HH
- - 30
mA
Input Low Voltage
V
IL
- -0.3
-
0.8
V
Input High Voltage
V
IH
- 2.4
-
5.5
V
Output Low Voltage (Verify)
V
OL
I
OL
= 2.1 mA
-
-
0.45
V
Output High Voltage (Verify)
V
OH
I
OH
= -0.4 mA
2.4
-
-
V
A9 Silicon I.D. Voltage
V
ID
- 11.5
12.0
12.5
V
A9 Erase Voltage
V
ID
- 11.75
12.0
14.25
V
V
PP
Program Voltage
V
PP
- 11.75
12.0
12.25
V
V
PP
Erase Voltage
V
PE
- 11.75
12.0
14.25
V
V
DD
Supply Voltage
(Program)
V
CP
- 4.5
5.0
5.5
V
V
DD
Supply Voltage (Erase)
V
CE
- 4.5
5.0
5.5
V
V
DD
Supply Voltage (Erase
Verify)
V
PE
- -
5.0
-
V
Note: V
DD
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.