W27L520

64K

8 ELECTRICALLY ERASABLE EPROM

Publication Release Date: July 26, 2001

- 1 - Revision A5

GENERAL DESCRIPTION

The W27L520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory
organized as 65,536

8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data

lines. To cooperate with the MCU, this device could save the external TTL component, also cost and
space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to 5.5V in normal read mode. The
W27L520 provides an electrical chip erase function. It will be a great convenient when you need to
change/update the contents in the device.

FEATURES

High speed access time: 70/90 nS (max.)

Read operating current: 8/20 mA (max.)

Erase/Programming operating current

30 mA (max.)

Standby current: 20/100

A (max.)

Unregulated battery power supply range,

3.0V to 3.6V and 4.5V to 5.5V

+13V erase and programming voltage

High Reliability CMOS Technology

2K V ESD Protection

200 mA Latchup Immunity

Fully static operation

All inputs and outputs directly LVTTL/CMOS

compatible

Three-state outputs

Available packages: 20-pin TSSOP and 20-pin

SOP

PIN CONFIGURATIONS

AD2

AD0

AD7

GND

AD6

AD4

AD1

AD3

AD5

A11

A13

A15

#OE/VPP

ALE

A14

A12

TSSOP

Top View

A10

AD5

AD0

A10

AD1

AD3

ALE

A14

A12

GND

AD6

AD4

AD2

A11

A13

A15

SOP

Top View

#OE/VPP

VDD

AD7

BLOCK DIAGRAM

ALE

#OE / V

CONTROL

GND

AD7 - AD0

OUTPUT
BUFFER

DECODER

A15 - A8

MEMORY

ARRAY

PIN DESCRIPTION

SYMBOL

DESCRIPTION

AD0

AD7 Address/Data Inputs/Outputs

A15

Address Inputs

ALE

Address Latch Enable

#OE/VPP Output Enable, Program/Erase

Supply Voltage

Power Supply

GND

Ground

W27L520

- 2 -

FUNCTIONAL DESCRIPTION

Read Mode

Unlike conventional UVEPROMs, which has #CE and #OE two control functions, the W27L520 has one
#OE/V

and one ALE (Address Latch Enable) control functions. The ALE makes lower address A[7:0]

to be latched in the chip when it goes from high to low, so that the same bus can be used to output data
during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed. #OE/V

controls the

output buffer to gate data to the output pins. When addresses are stable, the address access time (T

ACC

)

is equal to the delay from ALE to output (T

), and data are available at the outputs T

after the falling

edge of #OE/V

, if T

ACC

and T

timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27L520 uses electrical erasure. Generally, the chip can be erased within 100 mS by using
an EPROM writer with a special erase algorithm.

There are two ways to enter Erase mode. One is to raise #OE/V

to V

(13V), V

= V

(6.5V), A9 =

(13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low or

high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex).
Be careful to note that the ALE pulse widths of these two commands are different: One is 50

S, while

the other is 100 mS. Please refer to the Smart Erase Algorithm 1 & 2.

Erase Verify Mode

The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.

Program Mode

Programming is the only way to change cell data from "1" to "0." The program mode is entered when
#OE/V

is raised to V

(13V), V

= V

(6.5V), the address pins equal the desired addresses, and

the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.

Program Verify Mode

The device will enter the Program Verify Mode automatically after Program Mode. Only power down the
device can force the device enter Normal Read Mode again.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
ALE and #OE/V

pins, the W27L520 may have common inputs.

W27L520

Publication Release Date: July 26, 2001

- 3 - Revision A5

Standby Mode

The standby mode significantly reduces V

current. This mode is entered when ALE and #OE/V

keep high. In standby mode, all outputs are in a high impedance state.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I

), active current levels (I

), and

transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes
depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection
will suppress transient voltage peaks. Each device should have a 0.1

F ceramic capacitor connected

between its V

and GND. This high frequency, low inherent-inductance capacitor should be placed as

close as possible to the device. Additionally, for every eight devices, a 4.7

F electrolytic capacitor

should be placed at the array's power supply connection between V

and GND. The bulk capacitor will

overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

= 13V, V

= 12V, V

= 6.5V, V

= 3.3V or 5.0V, V

= 5.0V, X = V

or V

)

MODE

PIN

ALE #OE/V

OTHER ADDRESS

AD[7:0]

Address Latch Enable

A[7:0]

Read

OUT

Output Disable

IL/

High Z

Standby

A[7:0]

Program

Erase 1

A8&A11 = V

, A9 = V

A10 = V

, Others = X

Erase 2

First command:

Addr. = 5555 (hex)

AA(hex)

Second command:

Addr. = 2AAA (hex)

10(hex)

Product
Identifier-manufacturer

A8 = V

, A9 = V

, Others = X V

DA(Hex)

Product Identifier-device

A8 = V

, A9 = V

, Others = X V

1F(Hex)

W27L520

- 4 -

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Ambient Temperature with Power Applied

-55 to +125

Storage Temperature

-65 to +150

Voltage on all Pins with Respect to Ground Except
#OE/V

PP,

A9 and V

Pins

-2.0 to +7.0

Voltage on #OE/V

Pin with Respect to Ground

-2.0 to +7.0

Voltage on A9 Pin with Respect to Ground

-2.0 to +7.0

Voltage V

Pin with Respect to Ground

-2.0 to +14.0

Notes:

1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is V

+0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.

DC Erase Characteristics

= 25

C, V

= 6.5V

0.25V)

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN. TYP.

MAX.

Input Load Current

= V

or V

-10

Erase Current

ALE = V

IH,

#OE/V

= V

A8 & A11 = V

, A9 = V

A10 = V

, Others = X

Erase Current

ALE = V

IH,

#OE/V

= V

A8 & A11 = V

, A9 = V

A10 = V

, Others = X

Input Low Voltage

-0.3

0.8

Input High Voltage

2.4

VDD +0.3

Output Low Voltage
(Verify)

= 2.1 mA

0.45

Output High Voltage
(Verify)

= -0.4 mA

2.4

A9 SID Voltage

= 5V

10%

11.5

12.5

A9 Erase Voltage

12.75 13

13.25

Erase Voltage

12.75 13

13.25

Supply Voltage

(Erase & Erase Verify)

6.25

6.5

6.75

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

W27L520

Publication Release Date: July 26, 2001

- 5 - Revision A5

CAPACITANCE

= 3.0V to 3.6V or 4.5V to 5.5V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

MAX.

UNIT

Input Capacitance

= 0V

Output Capacitance

OUT

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0V/3V

Input Rise and Fall Times

10 nS

Input and Output Timing Reference Level

1.5V/1.5V

Output Load

= 100 pF, I

= -0.4 mA/2.1 mA

AC Test Load and Waveforms

+1.3V

3.3K ohm

100 pF (Including Jig and Scope)

(IN914)

OUT

1.5V

Test Points

Input

Output

W27L520

- 6 -

READ OPERATION DC CHARACTERISTICS

= 3.0V to 3.6V or 4.5V to 5.5V, T

= 0 to 70

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX

Input Load Current

= 0V to V

-5

Output Leakage Current

OUT

= 0V to V

-5

VDD = 3.0V to 3.6V

Standby V

Current

(CMOS input)

VDD = 4.5V to 5.5V

ALE = V

0.3V, #OE/VPP

= V

0.3V All

others inputs =
GND/ V

0.3V

100

VDD = 3.0V to 3.6V

Operating Current

VDD = 4.5V to 5.5V

ALE = VIL,
IOUT = 0 mA
f = 5 MHz

Input Low Voltage

-0.6

0.8

Input High Voltage

2.0

+0.3

Output Low Voltage

= 2.1 mA

0.4

Output High Voltage

= -0.4 mA

2.4

READ OPERATION AC CHARACTERISTICS

= 3.0V to 3.6V or 4.5V to 5.5V, T

= 0 to 70

PARAMETER

SYM.

W27L520-70

W27L520-90

UNIT

MIN.

MAX.

MIN.

MAX.

Address Latch Enable Access Time

Address Latch Enable Width

ALE

Address Access Time

ACC

Address Setup Time

Address Hold Time

Output Enable Access Time

#OE/VPP High to High-Z Output

Output Hold from Address Change

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

W27L520

Publication Release Date: July 26, 2001

- 7 - Revision A5

DC PROGRAMMING CHARACTERISTICS

= 6.5V

0.25V, T

= 25

PARAMETER

SYM.

CONDITIONS

LIMITS

UNIT

MIN. TYP.

MAX.

Input Load Current

= V

or V

-10

Program Current

ALE = V

#OE

= V

Program Current

ALE = V

#OE/V

= V

Input Low Voltage

-0.3

0.8

Input High Voltage

2.4

+0.5

Output Low Voltage (Verify)

= 2.1 mA

0.45

Output High Voltage (Verify)

= -0.4 mA

2.4

A9 Silicon I.D. Voltage

= 5V

10%

11.5

12.0

12.5

Program Voltage

12.75 13.0

13.25

Supply Voltage (Program)

6.25

6.5

6.75

AC PROGRAMMING/ERASE CHARACTERISTICS

= 6.5V

0.25V, T

= 25

PARAMETER

SYM.

LIMITS

UNIT

MIN.

TYP.

MAX.

#OE/V

Pulse Rise Time

PRT

Address Latch Enable Width

ALE

500

ALE Program Pulse Width

PPW

47.5

52.5

ALE Erase Pulse Width

EPW

100

105

ALE Erase Pulse Width 1

EPW1

47.5

52.5

ALE Erase Pulse Width 2

EPW2

100

105

Latched Address Setup Time

LAS

100

Latched Address Hold Time

LAH

100

Address Setup Time

2.0

Address Hold Time

#OE/V

Setup Time

OES

2.0

#OE/V

Hold Time

OEH

2.0

Data Setup Time

2.0

Data Hold Time

2.0

Data Valid from #OE/V

Low during Erase Verify

EOE

150

Data Valid from #OE/V

Low during Program Verify

POE

150

#OE/V

High to Output High Z

DFP

130

#OE/V

High Voltage Delay After ALE Low

2.0

#OE/V

Recovery Time

2.0

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

W27L520

Publication Release Date: July 26, 2001

- 9 - Revision A5

Timing Waveforms, continued

Erase Waveform 1

#OE/Vpp

13.0V

PRT

ALE

Address Valid

A[15:8]

A9 = 12.0V

A9 = 13.0V

Others = V

or V

A8 = V

Others = V

or V

A8, A11 = V

A10 = V

AD[7:0]

OUT

Add

EPW

OES

OEH

EOE

Read
Company
SID

Chip Erase

Erase (Verify)

Read
Device
SID

V = 6.5V

V = 3.3 or 5.0V

V = 6.5V

Erase Waveform 2

#OE/Vpp

13.0V

PRT

ALE

A[15:8]

A9=12.0
V

Others=V

or V

A8=V

AD[7:0]

Address Valid

EOE

Read
Company
SID

Command 1

Command 2

Read
Device
SID

OES

OEH

RPT

OES

ALE

LAS

LAH

EPW1

Erase Verify

Chip Erase

EPW2

A[15:8] = 55

A[15:8] = 2A

V =5.0V

V =6.5V

OUT

Add

Note: First command Address = 5555(hex) with Data = AA(hex)

Second command Address = 2AAA(hex) with Data = 10(hex)

W27L520

- 14 -

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

OPERATING

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (

PACKAGE

W27L520W-70*

8/20

20/100

173mil TSSOP

W27L520W-90*

8/20

20/100

173mil TSSOP

W27L520S-70*

8/20

20/100

300mil SOP

W27L520S-90*

8/20

20/100

300mil SOP

Notes:

1. The Part No is preliminary and might be changed after project is consoled.

2. Winbond reserves the right to make changes to its products without prior notice.

3. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

W27L520

Publication Release Date: July 26, 2001

- 15 - Revision A5

PACKAGE DIMENSIONS

20-pin TSSOP

Dimension in mm

Dimension in Inches

Min.

Nom. Max.

Symbol

0.002

0.09

0.043

0.006

0.18

0.256 BSC

1.10

0.15

0.50

0.70

0.028

0.020

4.30

4.48

0.169

0.176

0.003

0.007

0.65 BSC

0.05

Min.

Nom. Max.

6.40

6.60

0.260

0.252

6.25

6.50

0.256

0.246

0.18

0.30

0.012

0.007

20-pin SOP

Dimension in mm

Dimension in Inches

Min.

Nom. Max.

Symbol

0.003

0.229

0.105

0.012

0.330

1.27 BSC

2.67

0.305

0.381

0.889

0.035

0.015

7.39

7.60

0.291

0.299

0.009

0.013

0.50 BSC

0.076

Min.

Nom. Max.

12.6

13.0

0.513

0.497

9.98

10.7

0.420

0.393

0.330

0.508

0.020

0.013

0.092

2.34

W27L520

- 16 -

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Sep. 1999

Initial Issued

Jun. 2000

3, 4, 9, 11 Specify V

, V

CE,

and V

description

Change V

as V

Change V

as V

6, 7, 8, 9, 10 Change V

as V

DE,

as V

DP,

as V

HH,

as I

1, 6, 14

Add 90 nS bin

AC Test Condition: Change Input pulse level to 0V/3V;
Input and Output Timing Reference Level to 1.5V/1.5V

Delete Two-line Output Control section

Modify Storage Temperature Rating from -65 to +125

C to

-65 to +150

Modify Output Leakage Current from

A to

Add in ESD/Latchup information

Modify DC Characteristics

Sep. 2000

Correct Erase Waveform

Modify Address Latch Enable Mode: X -> Ain;

Modify Output Disable Mode: V

-> V

;

Modify Standby Mode: Ain -> X;

Typo Correction

Nov. 2000

1, 3, 5, 6

Add in 5V specification

1, 6, 14

Delete 70 nS bin

Jul. 2001

1, 6, 14

Add 70 nS bin

W27L520

Publication Release Date: July 26, 2001

- 17 - Revision A5

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886 -3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886 -2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886 -2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852 -27513100
FAX: 852 -27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886 -3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886 -2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886 -2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852 -27513100
FAX: 852 -27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W27L520-90

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W27L520-90