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Электронный компонент: W29C020C90BN

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W29C020C
256K
8 CMOS FLASH MEMORY
Publication Release Date: February 18, 2002
- 1 - Revision A4
GENERAL DESCRIPTION
The W29C020C is a 2-megabit, 5-volt only CMOS flash memory organized as 256K
8 bits. The
device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt
V
PP
is not required. The unique cell architecture of the W29C020C results in fast write (erase/program)
operations with extremely low current consumption compared to other comparable 5-volt flash memory
products. The device can also be written (erased and programmed) by using standard EPROM
programmers.
FEATURES
Single 5-volt write (erase and program)
operations
Fast page-write operations
-
128 bytes per page
-
Page write (erase/program) cycle: 10 mS
(max.)
-
Effective byte-write (erase/program) cycle
time: 39
S
-
Optional software-protected data write
Fast chip-erase operation: 50 mS
Two 8 KB boot blocks with lockout
Whole chip cycling: 10K (typ.)
Read access time: 70/90/120 nS
Twenty-year data retention
Software and hardware data protection
Low power consumption
-
Active current: 25 mA (typ.)
-
Standby current: 20
A (typ.)
Automatic write (erase/program) timing with
internal V
PP
generation
End of write (erase/program) detection
-
Toggle bit
-
Data polling
Latched address and data
All inputs and outputs directly TTL compatible
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, 32-pin
TSOP, and 32-pin PLCC
W29C020C
- 2 -
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
NC
A16
A15
A12
V
#WE
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
DD
A17
32-pin
DIP
5
6
7
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
D
Q
2
G
N
D
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
A
1
2
A
1
6
N
C
V
D
D
#
W
E
A
1
5
A
1
7
32-pin
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin
TSOP
A15
A12
A7
A6
A5
A4
V
#WE
A14
A13
A8
DD
A11
A9
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A17
DECODER
CORE
ARRAY
CONTROL
OUTPUT
BUFFER
#CE
#OE
#WE
A0
A17
.
.
.
DQ0
DQ7
.
.
8K Byte Boot Block (Optional)
8K Byte Boot Block (Optional)
V
V
DD
SS
PIN DESCRIPTION
SYMBOL
PIN NAME
A0
-
A17
Address Inputs
DQ0
-
DQ7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
V
DD
Power Supply
GND
Ground
NC
No Connection
W29C020C
Publication Release Date: February 18, 2002
- 3 - Revision A4
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C020C is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C020C is written (erased/programmed) on a page basis. Every page contains 128 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.
Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T
BLC
) of 200
S
after the initial byte-load cycle, the W29C020C will stay in the page load cycle. Additional bytes can
then be loaded consecutively. The page load cycle will be terminated and the internal write
(erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify the
page address. All bytes that are loaded into the page buffer must have the same page address. A0 to
A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading
is not required.
In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously
into the memory array. Before the completion of the internal write cycle, the host is free to perform
other tasks such as fetching data from other locations in the system to prepare to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a specific
address) to be performed before the data load operation. The three-byte load command sequence
begins the page load cycle, without which the write operation will not be activated. This write scheme
provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during
system power-up and power-down.
The W29C020C is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required. For information about specific codes, see the Command Codes for Software Data Protection
in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams
below.
W29C020C
- 4 -
Hardware Data Protection
The integrity of the data stored in the W29C020C is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The write and read operation are inhibited when V
DD
is less than
2.5V.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
reaches its sense level, the device will automatically timeout for 5
mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One of
them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The
first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command
sequence.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout); other memory
locations can be changed by the regular programming method. Once the boot block programming
lockout feature is activated, the chip erase function will be disabled. In order to detect whether the boot
block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the
product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for
specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the
last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if
the output data is "FE hex," the lockout feature is deactivated and the block can be programmed.
To return to normal operation, perform a three-byte command sequence to exit the identification mode.
For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C020C includes a data polling feature to indicate the end of a write cycle. When the
W29C020C is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.
DQ7 will show the true data. See the #OE Polling Timing Diagram.
W29C020C
Publication Release Date: February 18, 2002
- 5 - Revision A4
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C020C provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's
and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is
then ready for the next operation. See Toggle Bit Timing Diagram.
Product Identification
The product ID operation outputs the manufacturer code and device code. The programming
equipment automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed through software or by hardware operation. In
the software access mode, a six-byte command sequence can be used to access the product ID. A
read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001
hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte
command sequence.
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
TABLE OF OPERATING MODES
Operating Mode Selection
Operating Range: 0 to 70
C (Ambient Temperature), V
DD
= 5V
10 %, V
SS
= 0V, V
HH
= 12V
MODE
PINS
#CE
#OE
#WE
ADDRESS
DQ.
Read
V
IL
V
IL
V
IH
A
IN
Dout
Write
V
IL
V
IH
V
IL
A
IN
Din
Standby
V
IH
X
X
X
High Z
Write Inhibit
X
V
IL
X
X
High Z/D
OUT
X
X
V
IH
X
High Z/D
OUT
Output Disable
X
V
IH
X
X
High Z
5-Volt Software Chip
Erase
V
IL
V
IH
V
IL
A
IN
D
IN
Product ID
V
IL
V
IL
V
IH
A0 = V
IL
; A1
-
A17 = V
IL
;
A9 = V
HH
Manufacturer Code DA
(Hex)
V
IL
V
IL
V
IH
A0 = V
IH
; A1
-
A17 = V
IL
;
A9 = V
HH
Device Code
45 (Hex)
W29C020C
- 6 -
Command Codes for Software Data Protection
BYTE SEQUENCE
TO ENABLE PROTECTION
TO DISABLE PROTECTION
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555H
AAH
5555H
AAH
1 Write
2AAAH
55H
2AAAH
55H
2 Write
5555H
A0H
5555H
80H
3 Write
-
-
5555H
AAH
4 Write
-
-
2AAAH
55H
5 Write
-
-
5555H
20H
Software Data Protection Acquisition Flow
Software Data Protection
Enable Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 20
to
address 5555
Software Data Protection
Disable Flow
Sequentially load
up to 128 bytes
of page data
Pause 10 mS
Exit
Pause 10 mS
Exit
(Optional page-load
operation)
Notes for software program code:
Data Format: DQ7
-
DQ0 (Hex)
Address Format: A14
-
A0 (Hex)
W29C020C
Publication Release Date: February 18, 2002
- 7 - Revision A4
Command Codes for Software Chip Erase
BYTE SEQUENCE
ADDRESS
DATA
0 Write
5555H
AAH
1 Write
2AAAH
55H
2 Write
5555H
80H
3 Write
5555H
AAH
4 Write
2AAAH
55H
5 Write
5555H
10H
Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Exit
Notes for software chip erase:
Data Format: DQ7
-
DQ0 (Hex)
Address Format: A14
-
A0 (Hex)
W29C020C
- 8 -
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE
ALTERNATE PRODUCT (7)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION EXIT
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555
AA
5555H
AAH
5555H
AAH
1 Write
2AAA
55
2AAAH
55H
2AAAH
55H
2 Write
5555
90
5555H
80H
5555H
F0H
3 Write
-
-
5555H
AAH
-
-
4 Write
-
-
2AAAH
55H
-
-
5 Write
-
-
5555H
60H
-
-
Pause 10
S
Pause 10
S
Pause 10
S
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
Entry (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 60
to
address 5555
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Read address = 00000
data = DA
Read address = 00001
data = 45
Read address = 00002
data = FF/FE
(4)
Read address = 3FFF2
data = FF/FE
(5)
Product
Identification
Exit (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 S
Normal Mode
(6)
(2)
(2)
Pause 10 S
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7
-
DQ0 (Hex); Address Format: A14
-
A0 (Hex)
(2) A1
-
A16 = V
IL
; manufacture code is read for A0 = V
IL
; device code is read for A0 = V
IH
.
(3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if
power down.
(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is
inactivated and the block can be programmed.
(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new
designs, Winbond recommends that the 3 byte command code sequence be used.
W29C020C
Publication Release Date: February 18, 2002
- 9 - Revision A4
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE
BOOT BLOCK LOCKOUT FEATURE SET
ON FIRST 8K ADDRESS BOOT BLOCK
BOOT BLOCK LOCKOUT FEATURE SET
ON LAST 8K ADDRESS BOOT BLOCK
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555H
AAH
5555H
AAH
1 Write
2AAAH
55H
2AAAH
55H
2 Write
5555H
80H
5555H
80H
3 Write
5555H
AAH
5555H
AAH
4 Write
2AAAH
55H
2AAAH
55H
5 Write
5555H
40H
5555H
40H
6 Write
00000H
00H
3FFFFH
FFH
Pause 10
S
Pause 10
S
Boot Block Lockout Enable Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause 10 mS
Load data 00
to
address 00000
Boot Block Lockout
Feature Set on First 8K
Address Boot Block
Boot Block Lockout
Feature Set on Last 8K
Address Boot Block
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause 10 mS
Load data FF
to
address 3FFFF
Notes for boot block lockout enable:
1. Data Format: DQ7
-
DQ0 (Hex)
2. Address Format: A14
-
A0 (Hex)
3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.
W29C020C
- 10 -
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
D.C. Voltage on Any Pin to Ground Potential Except A9
-0.5 to V
DD
+1.0
V
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-1.0 to V
DD
+1.0
V
Voltage on A9 and OE Pin to Ground Potential
-0.5 to 12.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 5.0V
10
%
, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
#CE = #OE = V
IL
, #WE = V
IH
,
all DQs open
Address inputs = V
IL
/V
IH
,
at f = 5 MHz
-
-
50
Power Supply Current
I
CC
#CE = #OE = V
IL
, #WE = V
IH
,
all DQs open
Address inputs = V
IL
/V
IH
,
at f = 2 MHz
-
-
30
mA
Standby V
DD
Current
(TTL input)
I
SB
1
#CE = V
IH
, all DQs open
Other inputs = V
IL
/V
IH
-
2
3
mA
Standby V
DD
Current
(CMOS input)
I
SB
2 #CE = V
DD
-0.3V, all DQs open
-
20
100
A
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-
-
10
A
Output Leakage Current I
LO
V
IN
= V
SS
to V
DD
-
-
10
A
Input Low Voltage
V
IL
-
-
-
0.8
V
Input High Voltage
V
IH
-
2.0
-
-
V
Output Low Voltage
V
OL
I
OL
= 2.0 mA
-
-
0.45
V
Output High Voltage
V
OH1
I
OH
= -400
A
2.4
-
-
V
Output High Voltage
CMOS
V
OH2
I
OH
= -100
A; V
DD
= 4.5V
4.2
-
-
V
W29C020C
Publication Release Date: February 18, 2002
- 11 - Revision A4
Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
Power-up to Read Operation
T
PU
. READ
100
S
Power-up to Write Operation
T
PU
. WRITE
5
mS
CAPACITANCE
(V
DD
= 5.0V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
DQ Pin Capacitance
C
DQ
V
DQ
= 0V
12
pF
Input Pin Capacitance
C
IN
V
IN
= 0V
6
pF
AC CHARACTERISTICS
AC Test Conditions
(V
DD
= 5.0V
10 % for 90 nS and 120 nS; V
DD
= 5.0V
5 % for 70 nS)
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise/Fall Time
<5 nS
Input/Output Timing Level
1.5V/1.5V
Output Load
1 TTL Gate and C
L
= 100 pF for 90/120 nS
C
L
= 30 pF for 70 nS
AC Test Load and Waveform
+5V
1.8K
1.3K
D
OUT
100 pF for 90/120 nS
30 pF for 70 nS
(Including Jig and Scope)
Input
3V
0V
Test Point
Test Point
1.5V
1.5V
Output
W29C020C
- 12 -
AC Characteristics, continued
Read Cycle Timing Parameters
(V
DD
= 5.0V
10 % for 90 nS and 120 nS; V
DD
= 5.0V
5 % for 70 nS, V
SS
= 0V, T
A
= 0 to 70
C)
PARAMETER
SYM. W29C020C-70 W29C020C-90 W29C020C-12 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
T
RC
70
-
90
-
120
-
nS
Chip Enable Access Time
T
CE
-
70
-
90
-
120 nS
Address Access Time
T
AA
-
70
-
90
-
120 nS
Output Enable Access Time
T
OE
-
35
-
40
-
50
nS
#CE High to High-Z Output
T
CHZ
-
25
-
25
-
30
nS
#OE High to High-Z Output
T
OHZ
-
25
-
25
-
30
nS
Output Hold from Address change
T
OH
0
-
0
-
0
-
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Write Cycle (erase and program)
T
WC
-
-
10
mS
Address Setup Time
T
AS
0
-
-
nS
Address Hold Time
T
AH
50
-
-
nS
#WE and #CE Setup Time
T
CS
0
-
-
nS
#WE and #CE Hold Time
T
CH
0
-
-
nS
#OE High Setup Time
T
OES
0
-
-
nS
#OE High Hold Time
T
OEH
0
-
-
nS
#CE Pulse Width
T
CP
70
-
-
nS
#WE Pulse Width
T
WP
70
-
-
nS
#WE High Width
T
WPH
100
-
-
nS
Data Setup Time
T
DS
50
-
-
nS
Data Hold Time
T
DH
0
-
-
nS
Byte Load Cycle Time
T
BLC
-
-
200
S
Note: All AC timing signals observe the following guideline for determining setup and hold times:
Reference level is V
IH
for high-level signal and V
IL
for low-level signal.
W29C020C
Publication Release Date: February 18, 2002
- 13 - Revision A4
AC Characteristics, continued
#DATA Polling Characteristics
(1)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Data Hold Time
T
DH
10
-
-
nS
#OE Hold Time
T
OEH
10
-
-
nS
#OE to Output Delay
(2)
T
OE
-
-
-
nS
Write Recovery Time
T
WR
0
-
-
nS
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See T
OE
spec in A.C. Read Cycle Timing Parameters
.
Toggle Bit Characteristics
(1)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Data Hold Time
T
DH
10
-
-
nS
#OE Hold Time
T
OEH
10
-
-
nS
#OE to Output Delay
(2)
T
OE
-
-
-
nS
#OE High Pulse
T
OEHP
150
-
-
nS
Write Recovery Time
T
WR
0
-
-
nS
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See T
OE
spec in A.C. Read Cycle Timing Parameters
.
TIMING WAVEFORMS
Read Cycle Timing Diagram
Address A17-0
DQ7-0
Data Valid
Data Valid
High-Z
#CE
#OE
#WE
T
RC
V
IH
T
OE
T
CE
T
OH
T
AA
T
CHZ
T
OHZ
High-Z
W29C020C
- 14 -
Timing Waveforms, continued
#WE Controlled Write Cycle Timing Diagram
Address A17-0
DQ7-0
Data Valid
Internal write starts
#CE
#OE
#WE
T
AS
T
CS
T
OES
T
AH
T
WC
T
CH
T
OEH
T
WPH
T
WP
T
DS
T
DH
#CE Controlled Write Cycle Timing Diagram
High Z
Data Valid
Internal Write Starts
Address A17-0
#CE
#OE
#WE
T
AS
T
AH
T
WC
T
OEH
T
DH
T
DS
T
CP
T
OES
DQ7-0
T
WPH
T
CS
T
CH
W29C020C
Publication Release Date: February 18, 2002
- 15 - Revision A4
Timing Waveforms, continued
Page Write Cycle Timing Diagram
Address A17-0
Byte 0
Byte 1
Byte 2
Byte N-1
Byte N
Internal Write Start
DQ7-0
#CE
#OE
#WE
T
WC
T
BLC
T
WPH
T
WP
#DATA Polling Timing Diagram
Address A15-0
DQ7
#WE
#OE
#CE
T
DH
T
OEH
T
OE
HIGH-Z
T
WR
W29C020C
- 16 -
Timing Waveforms, continued
Toggle Bit Timing Diagram
DQ6
#WE
#OE
#CE
T
DH
T
OE
HIGH-Z
T
WR
T
OEH
Page Write Timing Diagram Software Data Protection Mode
5555
5555
AA
55
A0
Three-byte sequence for
software data protection mode
Byte/page load
cycle starts
Internal write starts
Word N
(last word)
Word 0
SW2
SW1
SW0
Address A15-0
DQ7-0
#CE
#OE
#WE
2AAA
T
WP
T
WPH
T
BLC
Word N-1
T
WC
W29C020C
Publication Release Date: February 18, 2002
- 17 - Revision A4
Timing Waveforms, continued
Reset Software Data Protection Timing Diagram
SW2
SW1
SW0
Address A15-0
DQ7-0
SW3
SW4
SW5
Internal programming starts
Six-byte sequence for resetting
software data protection mode
T
WC
T
WP
T
WPH
T
BLC
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
20
#CE
#OE
#WE
Software Chip Erase Timing Diagram
SW2
SW1
SW0
Address A15-0
DQ7-0
SW3
SW4
SW5
Internal erasing starts
Six-byte code for 5V-only software
chip erase
T
WC
T
WP
T
WPH
T
BLC
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
10
#CE
#OE
#WE
W29C020C
- 18 -
ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
POWER
SUPPLY
CURRENT
MAX. (mA)
STANDBY
V
DD
CURRENT
MAX. (
A)
PACKAGE CYCLING HARDWARE
SID READ
FUNCTION
W29C020C-70B
70
50
100
600 mil DIP
10K
Y
W29C020C-90B
90
50
100
600 mil DIP
10K
Y
W29C020C-12B
120
50
100
600 mil DIP
10K
Y
W29C020CT70B
70
50
100
Type one TSOP
10K
Y
W29C020CT90B
90
50
100
Type one TSOP
10K
Y
W29C020CT12B
120
50
100
Type one TSOP
10K
Y
W29C020CP70B
70
50
100
32-pin PLCC
10K
Y
W29C020CP90B
90
50
100
32-pin PLCC
10K
Y
W29C020CP12B
120
50
100
32-pin PLCC
10K
Y
W29C020C90BN
90
50
100
600 mil DIP
10K
N
W29C020C12BN
120
50
100
600 mil DIP
10K
N
W29C020CT90N
90
50
100
Type one TSOP
10K
N
W29C020CT12N
120
50
100
Type one TSOP
10K
N
W29C020CP90N
90
50
100
32-pin PLCC
10K
N
W29C020CP12N
120
50
100
32-pin PLCC
10K
N
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. In Hardware SID Read column: Y = with SID read function; N = without SID read function.
W29C020C
Publication Release Date: February 18, 2002
- 19 - Revision A4
HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin TSOP W29C020CT70B
1
st
line: Winbond logo
2
nd
line: the part number: W29C020CT70B
3
rd
line: the lot number
4
th
line: the tracking code: 149 O B SA
149: Packages made in '01, week 49
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
SA: Process code
W29C020CT70B
2138977A-A12
149OBSA
W29C020C
- 20 -
PACKAGE DIMENSIONS
32-pin P-DIP
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
6.General appearance spec. should be based on
final visual inspection spec.
.
1.37
1.22
0.054
0.048
Notes:
Symbol
Min. Nom. Max.
Max.
Nom.
Min.
Dimension in inches
Dimension in mm
A
B
c
D
e
A
L
S
A
A
1
2
E
0.050
1.27
0.210
5.33
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.41
0.25
3.94
0.46
4.06
0.56
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.20
3.05
0.25
3.30
0.36
3.56
0.555
0.550
0.545
14.10
13.97
13.84
17.02
15.24
14.99
15.49
0.600
0.590
0.610
2.29
2.54
2.79
0.090
0.100
0.110
B
1
1
e
E
1
a
1.650
1.660
41.91
42.16
0
15
0.085
2.16
0.650
0.630
16.00
16.51
protrusion/intrusion.
4.Dimension B1 does not include dambar
5.Controlling dimension: Inches.
15
0
Seating Plane
e
A
2
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
32
1
16
17
32-pin TSOP
A
A
A
2
1
L
L
1
Y
c
E
H
D
D
b
e
M
0.10(0.004)
Min.
Nom.
Max.
Min.
Nom.
Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
H
D
Note:
Controlling dimension: Millimeters
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007
0.008
0.009
0.005
0.006
0.007
0.720
0.724
0.728
0.311
0.315
0.319
0.780
0.787
0.795
0.020
0.016
0.020
0.024
0.031
0.000
0.004
1
3
5
0.002
1.20
0.05
0.15
1.05
1.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20
0.23
0.15
0.17
18.40
18.50
8.00
8.10
20.00
20.20
0.50
0.50
0.60
0.80
0.10
3
5
Dimension in mm
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
__
W29C020C
Publication Release Date: February 18, 2002
- 21 - Revision A4
Package Dimensions, continued
32-pin PLCC
L
c
1
b
2
A
H
E
E
e
b
D H
D
y
A
A
1
Seating Plane
E
G
G
D
1
13
14
20
29
32
4
5
21
30
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on final
visual inspection sepc.
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in Inches
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
1
2
E
b
1
G
D
3.56
0.50
2.80
2.67
2.93
0.71
0.66
0.81
0.41
0.46
0.56
0.20
0.25
0.35
13.89
13.97
14.05
11.35
11.43
11.51
1.27
H
D
G
E
12.45
12.95
13.46
9.91
10.41
10.92
14.86
14.99
15.11
12.32
12.45
12.57
1.91
2.29
0.004
0.095
0.090
0.075
0.495
0.490
0.485
0.595
0.590
0.585
0.430
0.410
0.390
0.530
0.510
0.490
0.050
0.453
0.450
0.447
0.553
0.550
0.547
0.014
0.010
0.008
0.022
0.018
0.016
0.032
0.026
0.028
0.115
0.105
0.110
0.020
0.140
1.12
1.42
0.044
0.056
0
10
10
0
0.10
2.41
W29C020C
- 22 -
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
May 1999
-
Initial Issued
A2
Apr. 2000
12
Change Byte Load Cycle Time from 150
S to 200
S
A3
Dec. 2000
5, 18
Add in Hardware SID Read function note
A4
Feb. 18, 2002
10
Add in one more Test Condition in Power Supply
Current (Icc): f = 2 MHz
4
Modify V
DD
Power Up/Down Detection description
19
Add HOW TO READ THE TOP MARKING
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.