W29C040

512K

8 CMOS FLASH MEMORY

Publication Release Date: May 1999

- 1 -

Revision A5

GENERAL DESCRIPTION

The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K

8 bits.

The device can be written (erased and programmed) in-system with a standard 5V power supply. A
12-volt V

is not required. The unique cell architecture of the W29C040 results in fast write (erase/

program) operations with extremely low current consumption compared to other comparable 5-volt
flash memory products. The device can also be written (erased and programmed) by using standard
EPROM programmers.

FEATURES

Single 5-volt write (erase and program)
operations

Fast page-write operations

256 bytes per page

Page write (erase/program) cycle: 5 mS
(typ.)

Effective byte-write (erase/program) cycle
time: 19.5

Optional software-protected data write

Fast chip-erase operation: 50 mS

Two 16 KB boot blocks with lockout

Typical page write (erase/program) cycles:
1K/10K (typ.)

Read access time: 90/120 nS

Ten-year data retention

Software and hardware data protection

Low power consumption

Active current: 25 mA (typ.)

Standby current: 20

A (typ.)

Automatic write (erase/program) timing with

internal V

generation

End of write (erase/program) detection

Toggle bit

Data polling

Latched address and data

All inputs and outputs directly TTL compatible

JEDEC standard byte-wide pinouts

Available packages: TSOP and PLCC

W29C040

- 2 -

PIN CONFIGURATIONS

DQ0

D
Q
1

D
Q
2

G
N
D

D
Q
3

D
Q
4

D
Q
5

D
Q
6

A14

A13

A11

OE
A10

DQ7

1
2

1
6

V
C
C

W
E

1
5

1
7

32-pin
PLCC

DQ0

DQ1

DQ2

GND

OE
A10

CE
DQ7
DQ6

DQ5

DQ4
DQ3

32-pin

TSOP

A15
A12

A7
A6
A5

A14

A13

A11

A18

A16

A17

1
8

BLOCK DIAGRAM

DECODER

CORE

ARRAY

CONTROL

OUTPUT

BUFFER

A18

DQ0

DQ7

.
.

16K Byte Boot Block (Optional)

PIN DESCRIPTION

SYMBOL

PIN NAME

A18

Address Inputs

DQ0

DQ7

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Power Supply

GND

Ground

W29C040

Publication Release Date: May 1999

- 3 -

Revision A5

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C040 is controlled by CE and OE , both Chip of which have to be low

for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the

chip is de-selected and only standby power will be consumed. OE is the output control and is used to

gate data from the output pins. The data bus is in high impedance state when either CE or OE is
high.

Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE ,

whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever
occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

BLC

) of

200

S after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes

can then be loaded consecutively. The page load cycle will be terminated and the internal write
(erase/program) cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify
the page address. All bytes that are loaded into the page buffer must have the same page address.
A0 to A7 specify the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written
simultaneously into the memory array. The typical write (erase/program) time is 5 mS. The entire
memory array can be written in 10.4 seconds. Before the completion of the internal write cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.

The W29C040 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection

W29C040

- 4 -

will remain enabled unless the disable commands are issued. A power transition will not reset the
software

data protection feature. To reset the device to unprotected mode, a six byte command sequence is
required. For information about specific codes, see the Command Codes for Software Data
Protection in the Table of Operating Modes. For information about timing waveforms, see the timing
diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C040 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The write operation is inhibited when V

is less than 2.5V.

(3) Write Inhibit Mode: Forcing

OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reach its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.
The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command
sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will be disabled. In order to detect
whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes)
or "7FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming
lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the
block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification
mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C040 includes a data polling feature to indicate the end of a write cycle. When the
W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the DATA Polling Timing Diagram.

W29C040

Publication Release Date: May 1999

- 5 -

Revision A5

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C040 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating
0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device
is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex"
outputs the device code "46 hex." The product ID operation can be terminated by a three-byte
command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70

C (Ambient Temperature), V

= 5V

10%, V

= 0V, V

= 12V

MODE

PINS

ADDRESS

DQ.

Read

Dout

Write

Din

Standby

High Z

Write Inhibit

High Z/D

OUT

High Z/D

OUT

Output Disable

High Z

Product ID

A0 = V

; A1

A18 = V

;

A9 = V

Manufacturer Code DA
(Hex)

A0 = V

; A1

A18 = V

;

A9 = V

Device Code
46 (Hex)

W29C040

- 6 -

Command Codes for Software Data Protection

BYTE SEQUENCE

TO ENABLE PROTECTION

TO DISABLE PROTECTION

ADDRESS

DATA

ADDRESS

DATA

0 Write

5555H

AAH

5555H

AAH

1 Write

2AAAH

55H

2AAAH

55H

2 Write

5555H

A0H

5555H

80H

3 Write

5555H

AAH

4 Write

2AAAH

55H

5 Write

5555H

20H

Software Data Protection Acquisition Flow

Software Data Protection

Enable Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data A0

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 20

address 5555

Software Data Protection

Disable Flow

Sequentially load

up to 256 bytes

of page data

Pause 10 mS

Exit

Pause 10 mS

Exit

(Optional page-load

operation)

Notes for software program code:
Data Format: DQ7

DQ0 (Hex)

Address Format: A14

A0 (Hex)

W29C040

- 8 -

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (7)

IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS

DATA

ADDRESS

DATA

ADDRESS

DATA

0 Write

5555

5555H

AAH

5555H

AAH

1 Write

2AAA

2AAAH

55H

2AAAH

55H

2 Write

5555

5555H

80H

5555H

F0H

3 Write

5555H

AAH

4 Write

2AAAH

55H

5 Write

5555H

60H

Pause 10

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 60

address 5555

Pause 10 uS

Product

Identification

and Boot Block

Lockout Detection

Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 46

Read address = 00002

data = FF/FE

(4)

Read address = 7FFF2

data = FF/FE

(5)

Product

Identification

Exit (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data F0

address 5555

Pause 10 uS

Normal Mode

(6)

(2)

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7

DQ0 (Hex); Address Format: A14

A0 (Hex)

(2) A1

A18 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond to first 16K/last 16K) lockout detection

mode if power down.

(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is

inactivated and the block can be programmed.

(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

W29C040

Publication Release Date: May 1999

- 9 -

Revision A5

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

BOOT BLOCK LOCKOUT FEATURE SET

ON FIRST 16K ADDRESS BOOT BLOCK

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 16K ADDRESS BOOT BLOCK

ADDRESS

DATA

ADDRESS

DATA

0 Write

5555H

AAH

5555H

AAH

1 Write

2AAAH

55H

2AAAH

55H

2 Write

5555H

80H

5555H

80H

3 Write

5555H

AAH

5555H

AAH

4 Write

2AAAH

55H

2AAAH

55H

5 Write

5555H

40H

5555H

40H

6 Write

00000H

00H

3FFFFH

FFH

Pause 10 mS

Boot Block Lockout Enable Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 40

address 5555

Pause 10 mS

Load data 00

address 00000

Boot Block Lockout

Feature Set on First 16K

Address Boot Block

Boot Block Lockout

Feature Set on Last 16K

Address Boot Block

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 40

address 5555

Pause 10 mS

Load data FF

address 3FFFF

Notes for boot block lockout enable:
1. Data Format: DQ7

DQ0 (Hex)

2. Address Format: A14

A0 (Hex)

3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp.

W29C040

- 10 -

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to Vss Potential

-0.5 to +7.0

Operating Temperature

0 to +70

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential Except A9

-0.5 to V

+1.0

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

-1.0 to V

+1.0

Voltage on A9 and OE Pin to Ground Potential

-0.5 to 12.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

Operating Characteristics

= 5.0V

, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN.

TYP.

MAX.

Power Supply Current

CE = OE = V

, WE = V

all DQs open

Address inputs = V

at f = 5 MHz

Standby V

Current

(TTL input)

CE = V

, all DQs open

Other inputs = V

Standby V

Current

(CMOS input)

CE = V

-0.3V, all DQs

open

100

Input Leakage Current

= GND to V

Output Leakage Current

= GND to V

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

= 2.0 mA

0.45

Output High Voltage

OH1

= -400

2.4

Output High Voltage

CMOS

OH2

= -100

A; V

= 4.5V

4.2

W29C040

Publication Release Date: May 1999

- 11 -

Revision A5

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

100

Power-up to Write Operation

. WRITE

CAPACITANCE

= 5.0V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

CONDITIONS

MAX.

UNIT

DQ Pin Capacitance

= 0V

Input Pin Capacitance

= 0V

AC CHARACTERISTICS

AC Test Conditions

= 5.0V

for 90,120 nS

PARAMETER

CONDITIONS

Input Pulse Levels

0V to 3V

Input Rise/Fall Time

<5 nS

Input/Output Timing Level

1.5V/1.5V

Output Load

1 TTL Gate and C

= 100 pF for 90/120/150 nS

AC Test Load and Waveform

+5V

1.8K

1.3K

OUT

100 pF for 90/120 nS
(Including Jig and Scope)

Input

Test Point

1.5V

Output

W29C040

- 12 -

AC Characteristics, continued

Read Cycle Timing Parameters

= 5.0V

for 90,120 and 150 nS, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

W29C040-90

W29C040-12

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

120

Chip Enable Access Time

120

Address Access Time

120

Output Enable Access Time

CE High to High-Z Output

CHZ

OE High to High-Z Output

OHZ

Output Hold from Address change

Byte/Page-write Cycle Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Write Cycle (erase and program)

Address Setup Time

Address Hold Time

WE and CE Setup Time

WE and CE Hold Time

OE High Setup Time

OES

OE High Hold Time

OEH

CE Pulse Width

WE Pulse Width

WE High Width

WPH

100

Data Setup Time

Data Hold Time

Byte Load Cycle Time

BLC

150

Notes:

All AC timing signals observe the following guideline for determining setup and hold times:

(1) High level signal's reference level is V

(2) Low level signal's reference level is V

W29C040

Publication Release Date: May 1999

- 13 -

Revision A5

AC Characteristics, continued

DATA Polling Characteristics

(1)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Data Hold Time

OE Hold Time

OEH

OE to Output Delay

(2)

Write Recovery Time

Notes:
(1) These parameters are characterized and not 100% tested.

(2) See T

spec in A.C. Read Cycle Timing Parameters

Toggle Bit Characteristics

(1)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Data Hold Time

OE Hold Time

OEH

OE to Output Delay

(2)

OE High Pulse

OEHP

150

Write Recovery Time

Notes:
(1) These parameters are characterized and not 100% tested.

(2) See T

spec in A.C. Read Cycle Timing Parameters

TIMING WAVEFORMS

Read Cycle Timing Diagram

Address A18-0

DQ7-0

Data Valid

High-Z

CHZ

OHZ

High-Z

W29C040

- 18 -

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER

SUPPLY CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (

PACKAGE

CYCLING

W29C040T-90

100

Type one TSOP

W29C040T-12

120

100

Type one TSOP

W29C040P-90

100

32-pin PLCC

W29C040P-12

120

100

32-pin PLCC

W29C040T-90B

100

Type one TSOP

10K

W29C040T-12B

120

100

Type one TSOP

10K

W29C040P-90B

100

32-pin PLCC

10K

W29C040P-12B

120

100

32-pin PLCC

10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

W29C040

Publication Release Date: May 1999

- 19 -

Revision A5

PACKAGE DIMENSIONS

32-pin PLCC

D H

Seating Plane

1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.

4. General appearance spec. should be based on final
visual inspection sepc.

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.95

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.490

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.510

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

Notes:

b
c
D

L
y

A
A

40-pin TSOP

A
A

0.10 (0.004)

Dimension in mm

Dimension in Inches

Min.

Nom. Max.

Symbol

Controlling dimension: Millimeters

0.05

18.3

9.90

19.8

0.50

0.00

18.4

20.0

0.50

0.60

0.8

1.20

0.15

18.5

10.10

20.2

0.70

0.10

0.047

0.006

1.00

0.95

1.05

0.041

0.039

0.037

0.17

0.22

0.27

0.007 0.009

0.011

0.10

0.15

0.20

0.004 0.006 0.008

0.72

0.724 0.728

0.390 0.394 0.398

0.780 0.787 0.795

0.020

0.020 0.024

0.028

0.031

0.000

0.004

0.002

Min.

Nom. Max.

W29C040

- 20 -

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Apr. 1997

Initial Issued

Nov. 1997

4, 8

Correct the address from 3FFF2 to 7FFF2

Correct the boot block from 8K to 16K

Modify page write cycle timing diagram waveform

1, 18

Delete cycling 100K item

Add. pause 10 mS

Add. pause 50 mS

Correct the time from 10 mS to 10

June 1998

Correct power-on delay from 5 mS to 10 mS

Correct T

PU.

WRITE (Typ.) from 5 mS to 10 mS

Oct. 1998

Correct 40-pin TSOP package drawing by 32-pin TSOP

Correct the address from 3FFFF to 7FFFF

May 1999

1, 12, 18

Modify TACC:

90/120/150 nS

90/120 nS binning

1, 2, 18, 19

Modify package:

PDIP/SOP/PLCC/TSOP

PLCC/TSOP

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

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