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Электронный компонент: W29C040P-90K

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W29C040
512K
8 CMOS FLASH MEMORY
Publication Release Date: May 6, 2002
- 1 - Revision A9
GENERAL DESCRIPTION
The W29C040 is a 4-megabit, 5-volt only CMOS page mode Flash Memory organized as 512K
8
bits. The device can be written (erased and programmed) in-system with a standard 5V power supply.
A 12-volt V
PP
is not required. The unique cell architecture of the W29C040 results in fast write (erase/
program) operations with extremely low current consumption (compared to other comparable 5-volt
flash memory products.) The device can also be erased and programmed by using standard EPROM
programmers.
FEATURES
Single 5-volt write (erase and program)
operations
Fast page-write operations
-
256 bytes per page
-
Page write (erase/program) cycle: 5 mS
(typ.)
-
Effective byte-write (erase/program) cycle
time: 19.5
S
-
Optional software-protected data write
Fast chip-erase operation: 50 mS
Two 16 KB boot blocks with lockout
Page write (erase/program) cycles: 50K (typ.)
Read access time: 70/90/120 nS
Ten-year data retention
Software and hardware data protection
Low power consumption
-
Active current: 25 mA (typ.)
-
Standby current: 20
A (typ.)
Automatic write (erase/program) timing with
internal V
PP
generation
End of write (erase/program) detection
-
Toggle bit
-
Data polling
Latched address and data
All inputs and outputs directly TTL compatible
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, TSOP
and PLCC
W29C040
- 2 -
PIN CONFIGURATIONS
5
6
7
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
D
Q
2
V
s
s
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
A
1
2
A
1
6
V
D
D
#
W
E
A
1
5
A
1
7
32-pin
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin
TSOP
A15
A12
A7
A6
A5
A4
V
#WE
A14
A13
A8
DD
A11
A9
A18
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A17
A
1
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
Vss
A7
A6
A5
A4
A3
A2
A1
A0
A16
A15
A12
V
#WE
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
DD
A17
32-pin
DIP
A18
BLOCK DIAGRAM
DECODER
CORE
ARRAY
CONTROL
OUTPUT
BUFFER
#CE
#OE
#WE
A0
A18
.
.
.
DQ0
DQ7
.
.
16K Byte Boot Block (Optional)
16K Byte Boot Block (Optional)
V
V
DD
SS
PIN DESCRIPTION
SYMBOL
PIN NAME
A0
-
A18
Address Inputs
DQ0
-
DQ7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
V
DD
Power Supply
V
SS
Ground
W29C040
Publication Release Date: May 6, 2002
- 3 - Revision A9
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C040 is controlled by #CE and #OE, both Chip of which have to be low
for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the
chip is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high.
Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.
Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T
BLC
) of 200
S
after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes can then
be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program)
cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify the page address.
All bytes that are loaded into the page buffer must have the same page address. A0 to A7 specify the
byte address within the page. The bytes may be loaded in any order; sequential loading is not required.
In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written simultaneously
into the memory array. The typical write (erase/program) time is 5 mS. The entire memory array can be
written in 10.4 seconds. Before the completion of the internal write cycle, the host is free to perform
other tasks such as fetching data from other locations in the system to prepare to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a specific
address) to be performed before the data load operation. The three-byte load command sequence
begins the page load cycle, without which the write operation will not be activated. This write scheme
provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during
system power-up and power-down.
The W29C040 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
W29C040
- 4 -
required. For information about specific codes, see the Command Codes for Software Data Protection
in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams
below.
Hardware Data Protection
The integrity of the data stored in the W29C040 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The write and read operation are inhibited when V
DD
is less than
2.5V.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reach its sense level, the device will automatically time-out 10
mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.
The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command
sequence.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout); a regular
programming method can change other memory locations. Once the boot block programming lockout
feature is activated, the chip erase function will be disabled. In order to detect whether the boot block
feature is set on the two 16K blocks, users can perform a six-byte command sequence: enter the
product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for
specific code), and then read from address "00002 hex" (for the first 16K bytes) or "7FFF2 hex" (for the
last 16K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated;
if the output data is "FE hex," the lockout feature is inactivated and the block can be programmed.
To return to normal operation, perform a three-byte command sequence to exit the identification mode.
For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C040 includes a data polling feature to indicate the end of a write cycle. When the W29C040
is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load
cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show
the true data. See the #DATA Polling Timing Diagram.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C040 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's
W29C040
Publication Release Date: May 6, 2002
- 5 - Revision A9
and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is
then ready for the next operation. See Toggle Bit Timing Diagram.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex"
outputs the device code "46 hex." The product ID operation can be terminated by a three-byte
command sequence.
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
TABLE OF OPERATING MODES
Operating Mode Selection
Operating Range: 0 to 70
C for normal products, -40 to 85
C for W29C040xxxxK, V
DD
= 5V
10 %, V
SS
= 0V, V
HH
= 12V
MODE
PINS
#CE #OE #WE
ADDRESS
DQ.
Read
V
IL
V
IL
V
IH
A
IN
Dout
Write
V
IL
V
IH
V
IL
A
IN
Din
Standby
V
IH
X
X
X
High Z
Write Inhibit
X
V
IL
X
X
High Z/D
OUT
X
X
V
IH
X
High Z/D
OUT
Output Disable
X
V
IH
X
X
High Z
Product ID
V
IL
V
IL
V
IH
A0 = V
IL
; A1
-
A18 = V
IL
;
A9 = V
HH
Manufacturer Code DA
(Hex)
V
IL
V
IL
V
IH
A0 = V
IH
; A1
-
A18 = V
IL
;
A9 = V
HH
Device Code
46 (Hex)