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Электронный компонент: W29C043-12

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Preliminary W29C043
512K
8 CMOS FLASH MEMORY
Publication Release Date: July 22, 2002
- 1 - Revision A1
1. GENERAL DESCRIPTION
The W29C043 is a 4-megabit, 5-volt only CMOS page mode Flash Memory organized as 512K
8
bits. The device can be written (erased and programmed) in-system with a standard 5V power supply.
A 12-volt V
PP
is not required. The unique cell architecture of the W29C043 results in fast write (erase/
program) operations with extremely low current consumption (compared to other comparable 5-volt
flash memory products.) The device can also be erased and programmed by using standard EPROM
programmers.
2. FEATURES
Single 5-volt write (erase and program)
operations
Fast page-write operations
-
256 bytes per page
-
Page write (erase/program) cycle: 5 mS (typ.)
-
Effective byte-write (erase/program) cycle
time: 19.5
S
-
Optional software-protected data write
Fast chip-erase operation: 50 mS
Two 16 KB boot blocks with lockout
Page write (erase/program) cycles: 50K (typ.)
Ten-year data retention
Software and hardware data protection
Low power consumption
-
Active current: 25 mA (typ.)
-
Standby current: 20
A (typ.)
Automatic write (erase/program) timing with
internal V
PP
generation
End of write (erase/program) detection
-
Toggle bit
-
Data polling
Latched address and data
All inputs and outputs directly TTL compatible
JEDEC standard byte-wide pinouts
3. BLOCK DIAGRAM
DECODER
CORE
ARRAY
CONTROL
OUTPUT
BUFFER
#CE
#OE
#WE
A0
A18
.
.
.
DQ0
DQ7
.
.
16K Byte Boot Block (Optional)
16K Byte Boot Block (Optional)
V
V
DD
SS
4. PIN DESCRIPTION
SYMBOL
PIN NAME
A0
-
A18
Address Inputs
DQ0
-
DQ7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
V
DD
Power Supply
V
SS
Ground
Preliminary W29C043
- 2 -
5. FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C043 is controlled by #CE and #OE, both Chip of which have to be low
for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the
chip is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high.
Refer to the read cycle timing waveforms for further details.
Page Write Mode
The W29C043 is written (erased/programmed) on a page basis. Every page contains 256 bytes of
data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the
device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device.
Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T
BLC
) of 200
S
after the initial byte-load cycle, the W29C043 will stay in the page load cycle. Additional bytes can then
be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program)
cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify the page address.
All bytes that are loaded into the page buffer must have the same page address. A0 to A7 specify the
byte address within the page. The bytes may be loaded in any order; sequential loading is not required.
In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written simultaneously
into the memory array. The typical write (erase/program) time is 5 mS. The entire memory array can be
written in 10.4 seconds. Before the completion of the internal write cycle, the host is free to perform
other tasks such as fetching data from other locations in the system to prepare to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a three-byte command sequence (with specific data to a specific
address) to be performed before the data load operation. The three-byte load command sequence
begins the page load cycle, without which the write operation will not be activated. This write scheme
provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during
system power-up and power-down.
The W29C043 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte command sequence cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required. For information about specific codes, see the Command Codes for Software Data Protection
in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams
below.
Preliminary W29C043
Publication Release Date: July 22, 2002
- 3 - Revision A1
Hardware Data Protection
The integrity of the data stored in the W29C043 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The program and read operation are inhibited when V
DD
is less
than 2.5V.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reach its sense level, the device will automatically time-out 10
mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.
The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command
sequence.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout); a regular
programming method can change other memory locations. Once the boot block programming lockout
feature is activated, the chip erase function will be disabled. In order to detect whether the boot block
feature is set on the two 16K blocks, users can perform a six-byte command sequence: enter the
product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for
specific code), and then read from address "00002 hex" (for the first 16K bytes) or "7FFF2 hex" (for the
last 16K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated;
if the output data is "FE hex," the lockout feature is inactivated and the block can be programmed.
To return to normal operation, perform a three-byte command sequence to exit the identification mode.
For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C043 includes a data polling feature to indicate the end of a write cycle. When the W29C043
is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load
cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show
the true data. See the #DATA Polling Timing Diagram.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W29C043 provides another method for determining the end of a write
cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's
and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is
then ready for the next operation. See Toggle Bit Timing Diagram.
Preliminary W29C043
- 4 -
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex"
outputs the device code "46 hex." The product ID operation can be terminated by a three-byte
command sequence.
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
6. TABLE OF OPERATING MODES
Operating Mode Selection
Operating Range: 0 to 70
C for normal products, -40 to 85
C for W29C043xxxxK, V
DD
= 5V
10
%
, V
SS
= 0V, V
HH
= 12V
PINS
MODE
#CE #OE #WE
ADDRESS
DQ.
Read
V
IL
V
IL
V
IH
A
IN
Dout
Write
V
IL
V
IH
V
IL
A
IN
Din
Standby
V
IH
X
X
X
High Z
X
V
IL
X
X
High Z/D
OUT
Write Inhibit
X
X
V
IH
X
High Z/D
OUT
Output Disable
X
V
IH
X
X
High Z
V
IL
V
IL
V
IH
A0 = V
IL
; A1
-
A18 = V
IL
;
A9 = V
HH
Manufacturer Code DA
(Hex)
Product ID
V
IL
V
IL
V
IH
A0 = V
IH
; A1
-
A18 = V
IL
;
A9 = V
HH
Device Code
46 (Hex)
Preliminary W29C043
Publication Release Date: July 22, 2002
- 5 - Revision A1
Command Codes for Software Data Protection
TO ENABLE PROTECTION
TO DISABLE PROTECTION
BYTE SEQUENCE
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555H
AAH
5555H
AAH
1 Write
2AAAH
55H
2AAAH
55H
2 Write
5555H
A0H
5555H
80H
3 Write
-
-
5555H
AAH
4 Write
-
-
2AAAH
55H
5 Write
-
-
5555H
20H
Software Data Protection Acquisition Flow
Software Data Protection
Enable Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 20
to
address 5555
Software Data Protection
D isable Flow
Sequentially load
up to 256 bytes
of page data
W a it for 10 mS or
Exit
W ait for 10 m S
Exit
(Optional page-load
operation)
toggle/polling
completed
Notes for software program code:
Data Format: DQ7
-
DQ0 (Hex)
Address Format: A14
-
A0 (Hex)
Preliminary W29C043
- 6 -
Command Codes for Software Chip Erase
BYTE SEQUENCE
ADDRESS
DATA
0 Write
5555H
AAH
1 Write
2AAAH
55H
2 Write
5555H
80H
3 Write
5555H
AAH
4 Write
2AAAH
55H
5 Write
5555H
10H
Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
W ait for 50 mS or
Exit
toggle/polling
completed
Notes for software chip erase:
Data Format: DQ7
-
DQ0 (Hex)
Address Format: A14
-
A0 (Hex)
Preliminary W29C043
Publication Release Date: July 22, 2002
- 7 - Revision A1
Command Codes for Product Identification and Boot Block Lockout Detection
ALTERNATE PRODUCT (7)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION EXIT
BYTE
SEQUENCE
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555
AA
5555H
AAH
5555H
AAH
1 Write
2AAA
55
2AAAH
55H
2AAAH
55H
2 Write
5555
90
5555H
80H
5555H
F0H
3 Write
-
-
5555H
AAH
-
-
4 Write
-
-
2AAAH
55H
-
-
5 Write
-
-
5555H
60H
-
-
Pause 10
S
Pause 10
S
Pause 10
S
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Identification
Entry (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 60
to
address 5555
Pause 10 uS
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Read address = 00000
data = DA
Read address = 00001
data = 46
Read address = 00002
data = FF/FE
(4)
Read address = 7FFF2
data = FF/FE
(5)
Product
Identification
Exit (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 uS
Normal Mode
(6)
(2)
(2)
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7
-
DQ0 (Hex); Address Format: A14
-
A0 (Hex)
(2) A1
-
A18 = V
IL
; manufacture code is read for A0 = V
IL
; device code is read for A0 = V
IH
.
(3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond to first 16K/last 16K) lockout detection mode
if power down.
(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is
inactivated and the block can be programmed.
(6) The device returns to standard operation mode.
(7) This product supports both the JEDEC standard 3 bytes command code sequence and original 6 byte command code sequence. For new
designs, Winbond recommends that the 3 bytes command code sequence be used.
Preliminary W29C043
- 8 -
Command Codes for Boot Block Lockout Enable
BOOT BLOCK LOCKOUT FEATURE SET
ON FIRST 16K ADDRESS BOOT BLOCK
BOOT BLOCK LOCKOUT FEATURE SET
ON LAST 16K ADDRESS BOOT BLOCK
BYTE SEQUENCE
ADDRESS
DATA
ADDRESS
DATA
0 Write
5555H
AAH
5555H
AAH
1 Write
2AAAH
55H
2AAAH
55H
2 Write
5555H
80H
5555H
80H
3 Write
5555H
AAH
5555H
AAH
4 Write
2AAAH
55H
2AAAH
55H
5 Write
5555H
40H
5555H
40H
6 Write
00000H
00H
7FFFFH
FFH
Pause 10 mS
Pause 10 mS
Boot Block Lockout Enable Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
W ait for 10 m S
Load data 00
to
address 00000
Boot Block Lockout
Feature Set on First 16K
Address Boot Block
Boot Block Lockout
Feature Set on Last 16K
Address Boot Block
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Load data FF
to
address 7FFFF
W ait for 10 m S
Notes for boot block lockout enable:
1. Data Format: DQ7
-
DQ0 (Hex)
2. Address Format: A14
-
A0 (Hex)
3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp.
Preliminary W29C043
Publication Release Date: July 22, 2002
- 9 - Revision A1
Data Polling Acquisition Flow
Byte Program
Initiated
Read DQ7
Is DQ7=
true data?
Write
Completed
No
Yes
Data Polling
Data Toggle Acquisition Flow
Byte Program/
Sector Erase
Initiated
Read byte
Read same
byte
Does DQ6
match?
Write
Completed
No
Yes
Toggle Bit
Preliminary W29C043
- 10 -
7. DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage to V
SS
Potential
-0.5 to +7.0
V
Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
D.C. Voltage on Any Pin to Ground Potential Except A9
-0.5 to V
DD
+1.0
V
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-1.0 to V
DD
+1.0
V
Voltage on A9 and #OE Pin to Ground Potential
-0.5 to 12.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(V
DD
= 5.0V
10
%
, V
SS
= 0V, T
A
= 0 to 70
C for normal products, -40 to 85
C for W29C043xxxxK )
LIMITS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX.
UNIT
Power Supply Current
I
CC
#CE = #OE = V
IL
, #WE = V
IH
,
all DQs open
Address inputs = V
IL
/V
IH
,
at f = 5 MHz
-
-
50
mA
Standby V
DD
Current
(TTL input)
I
SB
1
#CE = V
IH
, all DQs open
Other inputs = V
IL
/V
IH
-
2
3
mA
Standby V
DD
Current
(CMOS input)
I
SB
2
#CE = V
DD
-0.3V, all DQs
open
-
20
100
A
Input Leakage Current
I
LI
V
IN
= V
SS
to V
DD
-
-
10
A
Output Leakage Current
I
LO
V
IN
= V
SS
to V
DD
-
-
10
A
Input Low Voltage
V
IL
-
-
-
0.8
V
Input High Voltage
V
IH
For DIP pkg
2.2
-
-
V
Output Low Voltage
V
OL
I
OL
= 2.0 mA
-
-
0.45
V
Output High Voltage
V
OH1
I
OH
= -400
A
2.4
-
-
V
Output High Voltage
CMOS
V
OH2
I
OH
= -100
A; V
DD
= 4.5V
4.2
-
-
V
Preliminary W29C043
Publication Release Date: July 22, 2002
- 11 - Revision A1
Power-up Timing
PARAMETER
SYMBOL
TYPICAL
UNIT
Power-up to Read Operation
T
PU
. READ
100
S
Power-up to Write Operation
T
PU
. WRITE
10
mS
Capacitance
(V
DD
= 5.0V, T
A
= 25
C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MAX.
UNIT
DQ Pin Capacitance
C
DQ
V
DQ
= 0V
12
pF
Input Pin Capacitance
C
IN
V
IN
= 0V
6
pF
8. AC CHARACTERISTICS
AC Test Conditions
(V
DD
= 5.0V
10
%
for 70, 90,120 nS)
PARAMETER
CONDITIONS
Input Pulse Levels
0V to 3V
Input Rise/Fall Time
<5 nS
Input/Output Timing Level
1.5V/1.5V
Output Load
1 TTL Gate and C
L
= 100 pF for 90/120 nS
C
L
= 30 pF for 70 nS
AC Test Load and Waveform
+5V
1.8K
1.3K
D
OUT
100 pF for 90/120nS
30 pF for 70nS
(Including Jig and Scope)
Input
3V
0V
Test Point
Test Point
1.5V
1.5V
Output
Preliminary W29C043
- 12 -
AC Characteristics, continued
Read Cycle Timing Parameters
(V
DD
= 5.0V
10
%
V
SS
= 0V, T
A
= 0 to 70
C for normal products, -40 to 85
C for W29C043xxxxK)
W29C043-70 W29C043-90 W29C043-12
PARAMETER
SYM.
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
T
RC
70
-
90
-
120
-
nS
Chip Enable Access Time
T
CE
-
70
-
90
-
120
nS
Address Access Time
T
AA
-
70
-
90
-
120
nS
Output Enable Access Time
T
OE
-
35
-
40
-
50
nS
#CE High to High-Z Output
T
CHZ
-
20
-
25
-
30
nS
#OE High to High-Z Output
T
OHZ
-
20
-
25
-
30
nS
Output Hold from Address Change T
OH
0
-
0
-
0
-
nS
Byte/Page-write Cycle Timing Parameters
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Write Cycle (erase and program)
T
WC
-
-
10
mS
Address Setup Time
T
AS
0
-
-
nS
Address Hold Time
T
AH
50
-
-
nS
#WE and #CE Setup Time
T
CS
0
-
-
nS
#WE and #CE Hold Time
T
CH
0
-
-
nS
#OE High Setup Time
T
OES
0
-
-
nS
#OE High Hold Time
T
OEH
0
-
-
nS
#CE Pulse Width
T
CP
70
-
-
nS
#WE Pulse Width
T
WP
70
-
-
nS
#WE High Width
T
WPH
100
-
-
nS
Data Setup Time
T
DS
50
-
-
nS
Data Hold Time
T
DH
0
-
-
nS
Byte Load Cycle Time
T
BLC
-
-
200
S
Notes:
All AC timing signals observe the following guideline for determining setup and hold times:
(1) High level signal's reference level is V
IH
(2) Low level signal's reference level is V
IL
Preliminary W29C043
Publication Release Date: July 22, 2002
- 13 - Revision A1
AC Characteristics, continued
#DATA Polling Characteristics
(1)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Data Hold Time
T
DH
10
-
-
nS
#OE Hold Time
T
OEH
10
-
-
nS
#OE to Output Delay
(2)
T
OE
-
-
-
nS
Write Recovery Time
T
WR
0
-
-
nS
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See T
OE
spec in A.C. Read Cycle Timing Parameters
.
Toggle Bit Characteristics
(1)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Data Hold Time
T
DH
10
-
-
nS
#OE Hold Time
T
OEH
10
-
-
nS
#OE to Output Delay
(2)
T
OE
-
-
-
nS
#OE High Pulse
T
OEHP
150
-
-
nS
Write Recovery Time
T
WR
0
-
-
nS
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See T
OE
spec in A.C. Read Cycle Timing Parameters
.
9. TIMING WAVEFORMS
Read Cycle Timing Diagram
Address A18-0
DQ7-0
Data Valid
Data Valid
High-Z
#CE
#OE
#WE
T
RC
V
IH
T
OE
T
CE
T
OH
T
AA
T
CHZ
T
OHZ
High-Z
Preliminary W29C043
- 14 -
Timing Waveforms, continued
#WE Controlled Write Cycle Timing Diagram
Address A18-0
DQ7-0
Data Valid
Internal write starts
T
AS
T
CS
T
OES
T
AH
T
WC
T
CH
T
OEH
T
WPH
T
WP
T
DS
T
DH
#CE
#OE
#WE
#CE Controlled Write Cycle Timing Diagram
High Z
Data Valid
Internal Write Starts
Address A18-0
T
AS
T
AH
T
WC
T
OEH
T
DH
T
DS
T
CP
T
OES
DQ7-0
T
WPH
T
CS
T
CH
#CE
#OE
#WE
Preliminary W29C043
Publication Release Date: July 22, 2002
- 15 - Revision A1
Timing Waveforms, continued
Page Write Cycle Timing Diagram
Address A18-0
Byte 0
Byte 1
Byte 2
Byte N-1
Byte N
Internal Write Start
DQ7-0
T
WC
T
BLC
T
WPH
T
WP
#CE
#OE
#WE
#DATA Polling Timing Diagram
Address A18-0
DQ7
T
DH
T
OEH
T
OE
HIGH-Z
T
WR
#CE
#OE
#WE
Preliminary W29C043
- 16 -
Timing Waveforms, continued
Toggle Bit Timing Diagram
DQ6
#WE
#OE
#CE
T
DH
T
OE
HIGH-Z
T
WR
T
OEH
Page Write Timing Diagram Software Data Protection Mode
5555
5555
AA
55
A0
Three-byte sequence for
software data protection mode
Byte/page load
cycle starts
Internal write starts
Byte N
(Last Byte)
Byte 0
SW2
SW1
SW0
Address A18-0
DQ7-0
2AAA
T
WP
T
WPH
T
BLC
Byte N-1
T
WC
#CE
#OE
#WE
Preliminary W29C043
Publication Release Date: July 22, 2002
- 17 - Revision A1
Timing Waveforms, continued
Reset Software Data Protection Timing Diagram
SW2
SW1
SW0
Address A18-0
DQ7-0
SW3
SW4
SW5
Internal programming starts
Six-byte sequence for resetting
software data protection mode
T
WC
T
WP
T
WPH
T
BLC
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
20
#CE
#OE
#WE
5 Volt-only Software Chip Erase Timing Diagram
SW2
SW1
SW0
Address A18-0
DQ7-0
SW3
SW4
SW5
Internal erasing starts
Six-byte code for 5V-only software
chip erase
T
WC
T
WP
T
WPH
T
BLC
5555
2AAA
5555
5555
2AAA
5555
AA
55
80
AA
55
10
#CE
#OE
#WE
Preliminary W29C043
- 18 -
10. ORDERING INFORMATION
PART NO.
ACCESS
TIME
(nS)
POWER SUPPLY
CURRENT
MAX. (mA)
OPERATING
TEMP.
(
C)
PACKAGE
CYCLING
(K)
(
MIN.)
W29C043
50
0 to 70
10
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
Preliminary W29C043
Publication Release Date: July 22, 2002
- 19 - Revision A1
11. BONDING PAD DIAGRAM
X
Y
9
A3
25
OEB
A13 A8
28
29
30
WEB
32
VDD
33
13
14
19
20
21
DQ0 DQ1
15
DQ2
DQ5 DQ6 DQ7
22
11
A1
A0
12
23
A10
V
SS
16
24
CEB
DQ4
SB8036
31
A17A14
2
A16
3
A15
A12
4
A18
1
5
A7
4
A6
6
7
A5
A9
DQ3
26
A11
8
A4
10
A2
V
SS
17 18
27
VDD
34
PAD NO.
X
Y
1
-1272.44
2913.82
2
-1428.54
2913.82
3
-1584.64
2913.82
4
-1740.74
2913.82
5
-1896.84
2913.82
6
-2052.94
2913.82
7
-2209.04
2913.82
8
-2413.21
2825.08
9
-2413.29
-2743.41
10
-2238.63
-2914.10
11
-2082.53
-2914.10
12
-1926.43
-2914.10
13
-1712.99
-2902.64
14
-1548.64
-2902.64
15
-1384.29
-2902.64
16
90.95
-2898.30
17
215.95
-2898.30
18
1180.39
-2902.64
19
1344.74
-2902.64
20
1509.09
-2902.64
21
1673.44
-2902.64
22
1837.78
-2902.64
23
2070.34
-2914.10
24
2226.44
-2914.10
25
2413.10
-2743.41
26
2413.10
2784.70
27
2215.50
2913.82
28
2059.40
2913.82
29
1903.30
2913.82
30
1747.20
2913.82
31
1591.10
2913.82
32
1435.00
2913.82
33
145.36
2904.76
34
15.36
2904.76
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to V
DD
or left floating in the PCB layout.
Preliminary W29C043
- 20 -
12. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
July 22, 2002
-
Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.