W29EE512

64K

8 CMOS FLASH MEMORY

Publication Release Date: February 18, 2002

- 1 - Revision A7

GENERAL DESCRIPTION

The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K

8 bits. The device

can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

is not

required. The unique cell architecture of the W29EE512 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.

FEATURES

Single 5-volt program and erase operations

Fast page-write operations

128 bytes per page

Page program cycle: 10 mS (max.)

Effective byte-program cycle time: 39

Optional software-protected data write

Fast chip-erase operation: 50 mS

Read access time: 70/90/120 nS

Typical page program/erase cycles: 1K/10K

Ten-year data retention

Software and hardware data protection

Low power consumption

Active current: 50 mA (max.)

Standby current: 100

A (max.)

Automatic program timing with internal V

generation

End of program detection

Toggle bit

Data polling

Latched address and data

TTL compatible I/O

JEDEC standard byte-wide pinouts

Available packages: 32-pin PLCC, TSOP and
VSOP

W29EE512

- 2 -

PIN CONFIGURATIONS

DQ0

D
Q

G
N
D

D
Q

A14

A13

A11

A10

DQ7

1
2

V
C
C

W
E

1
5

32-pin
PLCC

9
10

DQ0

DQ1

DQ2

GND

A10

DQ7

DQ6
DQ5

DQ4
DQ3

32-pin
TSOP

A15
A12

A7
A6

A14

A13

A11

DQ0

DQ1

DQ2

GND

A10

DQ7

DQ6
DQ5

DQ4
DQ3

32-pin
VSOP

2
1

1
9

1
8

A15
A12

A7
A6

A14

A13

A11

BLOCK DIAGRAM

CONTROL

OUTPUT
BUFFER

DECODER

CORE

ARRAY

#CE

#OE

#WE

A15

DQ0

DQ7

PIN DESCRIPTION

SYMBOL

PIN NAME

A15

Address Inputs

DQ0

DQ7

Data Inputs/Outputs

#CE

Chip Enable

#OE

Output Enable

#WE

Write Enable

Power Supply

GND

Ground

No Connection

W29EE512

Publication Release Date: February 18, 2002

- 3 - Revision A7

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE512 is controlled by #CE

and #OE, both of which have to be low for

the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE

is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either #CE or #OE

is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing #CE and #WE low and #OE

high. The write procedure

consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device. Step 2 is an internal programming cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

BLC

) of 200

S, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can

then be loaded consecutively. The page load cycle will be terminated and the internal programming
cycle will start if no additional byte is loaded into the page buffer A

to A

specify the page address. All

bytes that are loaded into the page buffer must have the same page address. A

to A

specify the byte

address within the page. The bytes may be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up and power-down.

The W29EE512 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required.

W29EE512

- 4 -

Hardware Data Protection

The integrity of the data stored in the W29EE512 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming and read operation are inhibited when V

less than 2.8V.

(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ

)-Write Status Detection

The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE512 is in the internal programming cycle, any attempt to read DQ

of the last byte loaded during

the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is
completed. DQ

will show the true data.

Toggle Bit (DQ

)-Write Status Detection

In addition to data polling, the W29EE512 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ

will

produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.

5-Volt-only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C8h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing #CE and #OE

low,

#WE high, and raising A9 to 12 volts.

W29EE512

Publication Release Date: February 18, 2002

- 5 - Revision A7

TABLE OF OPERATING MODES

Operating Mode Selection

(Operating Range = 0 to 70

C (Ambient Temperature), V

= 5V

10%, V

= 0V, V

= 12V)

MODE

PINS

#CE

#OE #WE

ADDRESS

DQ.

Read

Dout

Write

Din

Standby

X X

High Z

Write Inhibit

X X

High Z/D

OUT

High Z/D

OUT

Output Disable

X X

High Z

5-Volt Software Chip Erase V

Product ID

= V

; A

= V

;

= V

Manufacturer Code
DA (Hex)

= V

; A

= V

;

= V

Device Code
C8 (Hex)

W29EE512

- 6 -

Command Codes for Software Data Protection

BYTE SEQUENCE

TO ENABLE PROTECTION

TO DISABLE PROTECTION

ADDRESS

DATA

ADDRESS

DATA

0 Write

5555H

AAH

5555H

AAH

1 Write

2AAAH

55H

2AAAH

55H

2 Write

5555H

A0H

5555H

80H

3 Write

5555H

AAH

4 Write

2AAAH

55H

5 Write

5555H

20H

Software Data Protection Acquisition Flow

Software Data Protection
Enable Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data A0

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 20

address 5555

Software Data Protection
Disable Flow

Sequentially load

up to 128 bytes

of page data

Pause 10 mS

Exit

Pause 10 mS

Exit

(Optional page-load

operation)

Notes for software program code:
Data Format: DQ7

DQ0 (Hex)

Address Format: A14

A0 (Hex)

W29EE512

- 8 -

Command Codes for Product Identification

BYTE

SEQUENCE

ALTERNATE SOFTWARE (5)

PRODUCT IDENTIFICATION

ENTRY

SOFTWARE PRODUCT

IDENTIFICATION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION EXIT

ADDRESS

DATA

ADDRESS

DATA

ADDRESS

DATA

0 Write

5555H

AAH

5555H

AAH

5555H

AAH

1 Write

2AAAH

55H

2AAAH

55H

2AAAH

55H

2 Write

5555H

90H

5555H

80H

5555H

F0H

3 Write

5555H

AAH

4 Write

2AAAH

55H

5 Write

5555H

60H

Pause 10

Software Product Identification Acquisition Flow

Product Identification Entry (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 60

address 5555

Product Identification Mode (2,3)

Read address = 0

data = DA

Read address = 1

data = C8

Product Identification Exit (1)

Load data AA

address 5555

Load data 55

address 2AAA

Load data FO

address 5555

Normal Mode

(4)

Pause 10 S

Notes for software product identification:
(1) Data format: DQ7

DQ0 (Hex); address format: A14

A0 (Hex).

(2) A1

A16 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.
(5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code
sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used.

W29EE512

Publication Release Date: February 18, 2002

- 9 - Revision A7

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to V

Potential

-0.5 to +7.0

Operating Temperature

0 to +70

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential except A9

-0.5 to V

+1.0

Transient Voltage (

¡ Õ

20 nS) on Any Pin to Ground Potential

-1.0 to V

+1.0

Voltage on A9 and #OE Pin to Ground Potential

-0.5 to 12.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Operating Characteristics

= 5.0V

, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX.

Power Supply
Current

#CE = #OE = V

, #WE = V

all I/Os open

Address inputs = V

, at f = 5 MHz

Standby Vcc Current
(TTL Input)

#CE = V

, all I/Os open

Other inputs = V

Standby Vcc Current
(CMOS Input)

2 #CE = V

-0.3V, all I/Os open

Other inputs = V

-0.3V/GND

100

Input Leakage
Current

= GND to V

Output Leakage
Current

= GND to V

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

= 2.1 mA

0.45

Output High Voltage V

OH1

= -0.4 mA

2.4

Output High Voltage
CMOS

OH2

= -100

A; V

= 4.5V

4.2

W29EE512

- 10 -

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

.READ

100

Power-up to Write Operation

.WRITE

CAPACITANCE

= 5.0V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

CONDITIONS

MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0V to 3V

Input Rise/Fall Time

5 nS

Input/Output Timing Level

1.5V/1.5V

Output Load

1 TTL Gate and C

= 100 pF/30 pF

AC Test Load and Waveform

+5V

1.8

1.3

100 pF

Input

Test Point

OUT

1.5V

Test Point

Output

Kohm

(For 90 nS/120 nS)

30 pF (For 70 nS)

W29EE512

Publication Release Date: February 18, 2002

- 11 - Revision A7

Read Cycle Timing Parameters

= 5.0V

, V

= 5.0

for 70 nS, V

= 0V, T

= 0 to 70

PARAMETER

SYM. W29EE512-70 W29EE512-90 W29EE512-12 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

120

Chip Enable Access Time

120

Address Access Time

120

Output Enable Access Time

#CE High to High-Z Output

CHZ

#OE High to High-Z Output

OHZ

Output Hold from Address Change T

Byte/Page-write Cycle Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Write Cycle (Erase and Program)

Address Setup Time

Address Hold Time

#WE and #CE Setup Time

#WE and #CE Hold Time

#OE High Setup Time

OES

#OE High Hold Time

OEH

#CE Pulse Width

#WE Pulse Width

#WE High Width

WPH

100

Data Setup Time

Data Hold Time

Byte Load Cycle Time

BLC

200

Notes: All AC timing signals observe the following guidelines for determining setup and hold times:

(1) High level signal's reference level is V

(2) Low level signal's reference level is V

W29EE512

- 12 -

#DATA Polling Characteristics

(1)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Data Hold Time

#OE Hold Time

OEH

#OE to Output Delay

(2)

Write Recovery Time

Notes:

(1) These parameters are characterized and not 100% tested.

(2) See T

spec in A.C. Read Cycle Timing Parameters

Toggle Bit Characteristics

(1)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Data Hold Time

#OE Hold Time

OEH

#OE to Output Delay

(2)

#OE High Pulse

OEHP

150

Write Recovery Time

Notes:

(1) These parameters are characterized and not 100% tested.

(2) See T

spec in A.C. Read Cycle Timing Parameters

W29EE512

- 18 -

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY V

CURRENT MAX.

(

PACKAGE

CYCLE

W29EE512P-70

100

32-pin PLCC

W29EE512P-90

100

32-pin PLCC

W29EE512P-12

120

100

32-pin PLCC

W29EE512T-70

100

Type one TSOP

W29EE512T-90

100

Type one TSOP

W29EE512T-12

120

100

Type one TSOP

W29EE512Q-70

100

Type one VSOP

W29EE512Q-90

100

Type one VSOP

W29EE512P-70B

100

32-pin PLCC

10K

W29EE512P-90B

100

32-pin PLCC

10K

W29EE512P-12B

120

100

32-pin PLCC

10K

W29EE512T-70B

100

Type one TSOP

10K

W29EE512T-90B

100

Type one TSOP

10K

W29EE512T-12B

120

100

Type one TSOP

10K

W29EE512Q-70B

100

Type one VSOP

10K

W29EE512Q-90B

100

Type one VSOP

10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

W29EE512

- 20 -

PACKAGE DIMENSIONS

32-pin PLCC

D H

Seating Plane

Notes:

1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on fina visual
inspection sepc.

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension In Inches

Dimension In mm

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

b
c
D

A
A

12.45

12.95

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.490

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.510

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

32-pin TSOP

0.10(0.004)

Min.

Nom.

Max.

Min.

Nom.

Max.

Symbol

Note:

Controlling dimension: Millimeters

Dimension In Inches

0.047

0.006

0.041

0.039

0.037

0.007

0.008

0.009

0.005

0.006

0.007

0.720

0.724

0.728

0.311

0.315

0.319

0.780

0.787

0.795

0.020

0.016

0.020

0.024

0.031

0.000

0.004

0.002

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.12

18.30

7.90

19.80

0.40

0.00

0.20

0.23

0.15

0.17

18.40

18.50

8.00

8.10

20.00

20.20

0.50

0.60

0.80

0.10

Dimension In mm

W29EE512

- 22 -

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Mar. 1998

Add. pause 10 mS

Add. pause 50 mS

Correct the time from 10 mS to 10

1, 2, 18, 19 Eliminate 600 mil DIP, 450 mil SOP packages

Oct. 1999

1, 2, 18, 20 Add 32-pin VSOP package

3, 11

Change Byte Load Cycle Time from 150

S to 200

Feb. 18, 2002

Modify V

Power Up/Down Detection in Hardware

Data Protection

Add HOW TO READ THE TOP MARKING

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W29EE512PT

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W29EE512PT