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Электронный компонент: W39F010T-70B

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W39F010
128K
8 CMOS FLASH MEMORY
Publication Release Date: June 17, 2002
- 1 - Revision A2
1. GENERAL DESCRIPTION
The
W39F010
is a 1Mbit, 5-volt only CMOS flash memory organized as 128K
8 bits. For flexible erase
capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (
8)
data appears on DQ7
-
DQ0. The device can be programmed and erased in-system with a standard
5V power supply. A 12-volt V
PP
is not required. The unique cell architecture of the W39F010 results in
fast program/erase operations with extremely low current consumption (compared to other comparable
5-volt flash memory products). The device can also be programmed and erased by using standard
EPROM programmers.
2. FEATURES
Single 5-volt operations
-
5-volt Read
-
5-volt Erase
-
5-volt Program
Fast Program operation:
-
Byte-by-Byte programming: 50
S (max.)
Fast Erase operation:
-
Chip Erase cycle time: 100 mS (max.)
-
Page Erase cycle time: 25 mS (max.)
Read access time: 70/90 nS
32 even pages with 4K bytes
Any individual page can be erased
Hardware protection:
-
Optional 16K byte Top/Bottom Boot Block
with lockout protection
Flexible 4K-page size can be used as
Parameter Blocks
Typical program/erase cycles:
-
1K/10K
Twenty-year data retention
Low power consumption
-
Active current: 15 mA (typ.)
-
Standby current: 15
A (typ.)
End of program detection
-
Software method: Toggle bit/Data polling
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP,
32-pin PLCC, 32- pin STSOP (8 x 14 mm) and
32- pin TSOP
W39F010
- 2 -
3. PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
Vss
A7
A6
A5
A4
A3
A2
A1
A0
NC
A16
A15
A12
V
#WE
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
DD
32-pin
DIP
5
6
7
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
D
Q
2
V
S
S
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
A
1
2
A
1
6
N
C
V
D
D
#
W
E
A
1
5
32-pin
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin
TSOP
A15
A12
A7
A6
A5
A4
V
#WE
A14
A13
A8
DD
A11
A9
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
NC
N
C
NC
4. BLOCK DIAGRAM
DQ
0
- DQ
7
A
0
- A
16
Data
latch
Input / output
Buffers
Chip Enable
Output Enable
Logic
Y-MUX / SENSING
ARRAY
Y-Decode
X-decode
A
d
d
r
e
s
s
L
a
t
c
h
State
Control
Command
Register
#CE
#WE
#OE
VDD
Vss
VDD Detect
Timer
Erase Voltage
Generator
Program Voltage
Generator
5. PIN DESCRIPTION
SYMBOL
PIN NAME
A0
-
A16
Address Inputs
DQ0
-
DQ7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
V
DD
Power Supply
V
SS
Ground
NC
No Connections
W39F010
Publication Release Date: June 17, 2002
- 3 - Revision A2
6. FUNCTIONAL DESCRIPTION
Device Bus Operation
Read Mode
The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the
host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for further details.
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device.
The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state, while #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
Standby Mode
There are two ways to implement the standby mode on the W39F010 device, both using the #CE pin.
A CMOS standby mode is achieved with the
#CE
input held at
V
DD
0.5V. Under this condition the current
is typically reduced to less than 50
A. A TTL standby mode is achieved with the #CE pin held at V
IH
.
Under this condition the current is typically reduced to 2 mA.
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
Data Protection
The W39F010
is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V
DD
power-up and power-down transitions or system noise.
W39F010
- 4 -
Boot Block Operation
There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device
can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes
or first 16K bytes of the memory with the address range from 1C000(hex) to 1FFFF(hex) for top
location or 00000(hex) to 03FFF(hex) for bottom location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K-byte block or not, users can
perform software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex)
for first(bottom) location or 1FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data is "1,"
the 16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data
is "0," the lockout feature will be inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Low V
DD
Inhibit
To avoid initiation of a write cycle during V
DD
power-up and power-down, the W39F010 locks out when
V
DD
< 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited
when V
DD
is less than 2.0V typical. The W39F010
ignores all write and read operations until V
DD
>
2,0V. The user must ensure that the control pins are in the correct logic state when V
DD
> 2.0V to
prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of #OE = V
IL
, #CE = V
IH
, or #WE = V
IH
. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write Inhibit
Power-up of the device with #WE = #CE = V
IL
and #OE = V
IH
will not accept commands on the rising
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state
machine is automatically reset to the read mode on power-up.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
W39F010
Publication Release Date: June 17, 2002
- 5 - Revision A2
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system.
The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 =
A1).
To terminate the operation, it is necessary to write the auto-select exit command sequence into the
register.
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later
and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of
#CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm.
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot
be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only
erase operations can convert "0"s to "1"s.
Refer to the Programming Command Flow Chart using typical command strings and bus operations.