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Электронный компонент: W39L040Q-90B

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W39L040
512K
8 CMOS FLASH MEMORY
Publication Release Date: February 10, 2003
- 1 -
Revision A3
1. GENERAL DESCRIPTION
The W39L040 is a 4Mbit, 3.3-volt only CMOS flash memory organized as 512K
8 bits. For flexible
erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The byte-wide (
8) data appears on DQ7 - DQ0.
The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt
V
PP
is not required. The unique cell architecture of the W39L040 results in fast program/erase
operations with extremely low current consumption (compared to other comparable 3.3-volt flash
memory products). The device can also be programmed and erased by using standard EPROM
programmers.
2. FEATURES
Single 3.3-volt operations
- 3.3-volt Read
- 3.3-volt Erase
- 3.3-volt Program
Fast Program operation:
- Byte-by-Byte programming: 50 S (max.)
Fast Erase operation:
- Chip Erase cycle time: 100 mS (max.)
- Sector Erase cycle time: 25 mS (max.)
- Page Erase cycle time: 25 mS (max.)
Read access time: 70/90 nS
8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
Any individual sector or page can be erased
Hardware protection:
- Optional 16K byte or 64K byte Top/Bottom
Boot Block with lockout protection
Flexible 4K-page size can be used as
Parameter Blocks
Typical program/erase cycles: 1K/10K
Twenty-year data retention
Low power consumption
- Active current: 10 mA (typ.)
- Standby current: 2 A (typ.)
End of program detection
- Software method: Toggle bit/Data polling
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32L PLCC, 32L TSOP (8 x
20 mm) and 32L STSOP (8 x 14 mm)
W39L040
- 2 -
3. PIN CONFIGURATIONS
5
6
7
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
D
Q
2
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
A
1
2
A
1
6
V
D
D
#
W
E
A
1
5
A
1
7
32L PLCC
V
S
S
A
1
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
32L TSOP & STSOP
A15
A12
A7
A6
A5
A4
V
#WE
A14
A13
A8
DD
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A17
SS
A18
4. BLOCK DIAGRAM
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
#CE
#OE
#WE
A0
.
.
A18
.
.
DQ0
DQ7
V
DD
V
SS
5. PIN DESCRIPTION
SYMBOL
PIN NAME
A0
- A18
Address Inputs
DQ0
- DQ7
Data Inputs/Outputs
#CE
Chip Enable
#OE Output
Enable
#WE Write
Enable
V
DD
Power
Supply
V
SS
Ground
W39L040
Publication Release Date: February 10, 2003
- 3 -
Revision A3
6. FUNCTIONAL DESCRIPTION
Device Bus Operation
Read Mode
The read operation of the W39L040 is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is
high. Refer to the timing waveforms for further details.
Write Mode
Device erasure and programming are accomplished via the command register. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the function
of the device.
The command register itself does not occupy any addressable memory location. The register is a
latch used to store the commands, along with the address and data information needed to execute the
command. The command register is written by bringing #WE to logic low state, while #CE is at logic
low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.
Standby Mode
There are two ways to implement the standby mode on the W39L040 device, both using the #CE pin.
A CMOS standby mode is achieved with the
#CE
input held at
V
DD
0.3V. Under this condition the current
is typically reduced to less than 15
A (max). A TTL standby mode is achieved with the #CE pin held
at V
IH
.
Under this condition the current is typically reduced to 2 mA(max).
In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the
output pins to be in a high impedance state.
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended for use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5V to 12.5V) on address pin
A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from
V
IL
to V
IH
. All addresses are don
t cares except A0 and A1 (see "Auto-select Codes").
W39L040
- 4 -
The manufacturer and device codes may also be read via the command register, for instance, when
the W39L040
is erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in "Auto-select Codes".
Byte 0 (A0 = V
IL
) represents the manufacturer
s code (Winbond = DAH) and byte 1 (A0 = V
IH
) the
device identifier code (W39L040 = B6hex). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be low state.
Data Protection
The W39L040
is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V
DD
power-up and power-down transitions or system noise.
Boot Block Operation
There are four alternatives to set the boot block. Either 16K-byte or 64K-byte in the top/bottom
location of this device can be locked as boot block, which can be used to store boot codes. It is
located in the last 16K/64K bytes or first 16K/64K bytes of the memory with the address range from
7C000/ 70000(hex) to 7FFFF(hex) for top location or 00000(hex) to 03FFF/0FFFF(hex) for bottom
location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K/64K-bytes block or not,
users can perform software command sequence: enter the product identification mode (see
Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read
from address 0002(hex) for first (bottom) location or 7FFF2(hex) for last (top) location. If the DQ0/DQ1
of output data is "0/1," the 16K-bytes boot block programming lockout feature will be activated; if the
DQ0/DQ1 of output data is "1/1," the 64K-bytes boot block programming lockout feature will be
activated. If the DQ0/DQ1 of output data is "0/0," for both 16K/64K-bytes boot block, the lockout
feature will be inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Low V
DD
Inhibit
To avoid initiation of a write cycle during V
DD
power-up and power-down, the W39L040 locks out
when V
DD
< 2.0V (see DC Characteristics section for voltages). The write and read operations are
inhibited when V
DD
is less than 2.0V typical. The W39L040 ignores all write and read operations until
V
DD
> 2,0V. The user must ensure that the control pins are in the correct logic state when V
DD
> 2.0V
to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
W39L040
Publication Release Date: February 10, 2003
- 5 -
Revision A3
Logical Inhibit
Writing is inhibited by holding any one of #OE = V
IL
, #CE = V
IH
, or #WE = V
IH
. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = V
IL
and #OE = V
IH
will not accept commands on the rising
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state
machine is automatically reset to the read mode on power-up.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto the address lines is not generally a desirable system design
practice.
The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L040 =
B6hex).
To terminate the operation, it is necessary to write the auto-select exit command sequence into the
register.
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens
later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising
edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program