W39V040A

512K

× 8 CMOS FLASH MEMORY

WITH LPC INTERFACE

Publication Release Date: December 19, 2002

- 1 -

Revision A2

1. GENERAL DESCRIPTION

The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K

× 8 bits. For

flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt V

is not required. The unique cell architecture

of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.

2. FEATURES

Single 3.3-volt Operations:

- 3.3-volt Read

- 3.3-volt Erase

- 3.3-volt Program

Fast Program Operation:

- Byte-by-Byte programming: 35 µS (typ.)

Fast Erase Operation:

- Chip erase 100 mS (max.)

- Sector erase 25 mS (max.)

- Page erase 25 mS (max.)

Fast Read access time: Tkq 11 nS

Endurance: 10K cycles (typ.)

Twenty-year data retention

8 Even sectors with 64K bytes each, which is

composed of 16 flexible pages with 4K bytes

Any individual sector or page can be erased

Hardware protection:

- Optional 16K byte or 64K byte Top Boot Block

with lockout protection

- #TBL & #WP support the whole chip hardware

protection

Flexible 4K-page size can be used as Parameter

Blocks

Low power consumption

- Active current: 12.5 mA (typ. for LPC mode)

Automatic program and erase timing with

internal

generation

End of program or erase detection

- Toggle bit

- Data polling

Latched address and data

TTL compatible I/O

Available packages: 32L PLCC, 32L STSOP

W39V040A

- 2 -

3. PIN CONFIGURATIONS

32L PLCC

DQ0(LAD0)

A7(GPI1)

A6(GPI0)

A3(RSV)

A2(RSV)

A1(RSV)

A0(RSV)

MODE

DQ7(RSV)

#WE(#LFRAM)

#OE(#INIT)

Vss

A4(#TBL)

A5(#WP)

1
2
3
4
5

6
7
8
9

10
11
12

14
15

32L STSOP

32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17

A9(GPI3)

#RESET

A8(GPI2)
A7(GPI1)
A6(GPI0)

MODE

A10(GPI4)

R/#C(CLK)

DQ0(LAD0)

A3(RSV)

A2(RSV)

A1(RSV)

A0(RSV)

DQ1(LAD1)

DQ2(LAD2)

DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
DQ3(LAD3)

DQ7(RSV)

#WE(#LFRAM

#OE(#INIT)

A4(#TBL)

A5(#WP)

4. BLOCK DIAGRAM

Program-

mer

Interface

7FFFF

00000

BOOT BLOCK,

16K BYTES

60000

5FFFF

7C000

7BFFF

40000

3FFFF

PARAMETER BLOCK1,

8K BYTES

PARAMETER BLOCK2,

8K BYTES

7A000

79FFF
78000

77FFF

#RESET

LPC

Interface

MODE

CLK

#LFRAM

LAD[3:0]

A[10:0]

DQ[7:0]

#OE

#WE

R/#C

70000

6FFFF

MAIN MEMORY SECTOR3, 64K BYTES

MAIN MEMORY SECTOR2, 64K BYTES

MAIN MEMORY SECTOR1, 64K BYTES

MAIN MEMORY SECTOR0, 64K BYTES

20000

1FFFF

50000

4FFFF

30000

2FFFF

10000

0FFFF

MAIN MEMORY SECTOR4, 64K BYTES

MAIN MEMORY SECTOR5, 64K BYTES

MAIN MEMORY SECTOR6, 64K BYTES

MEMORY BLOCK,

32K BYTES

MAIN MEMORY

SECTOR7,

64K BYTES

#TBL

#WP

5. PIN DESCRIPTION

INTERFACE

SYM.

PGM LPC

PIN NAME

MODE

Interface Mode Selection

#RESET

* *

Reset

#INIT

Initialize

#TBL

Top Boot Block Lock

#WP

Write

Protect

CLK *

CLK

Input

GPI[4:0]

General Purpose Inputs

ID[3:0] *

Identification

Inputs

LAD[3:0] * Address/Data Inputs

#LFRAM

LPC Cycle Initial

Row/Column

Select

A[10:0] * Address

Inputs

DQ[7:0] * Data

Inputs/Outputs

#OE

Output

Enable

#WE

Write

Enable

* *

Power

Supply

* *

Ground

RSV * *

Reserve

Pins

No Connection

W39V040A

Publication Release Date: December 19, 2002

- 3 -

Revision A2

6. FUNCTIONAL DESCRIPTION

Interface Mode Selection And Description

This device can be operated in two interface modes, one is Programmer interface mode, and the other is
LPC interface mode. The MODE pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET

When

MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to
low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash
parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is
mapped to the higher internal address A[18:11]. And the column address is mapped to the lower internal
address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through
the LAD[3:0] and #LFRAM

to communicate with the system chipset .

Read(Write) Mode

In Programmer interface mode, the read(write) operation of the W39V040A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface the "bit 1 of CYCLE TYPE+DIR" determines mode, the read
or write. Refer to the timing waveforms for further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is
in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be
at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read
or standby mode, it depends on the control signals.

Boot Block Operation and Hardware Protection at Initial - #TBL and #WP

There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this
device can be locked as boot block, which can be used to store boot codes. It is located in the last
16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.

Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before power on programmer, tie the #TBL

pin to low state and then the top boot block will not

be programmed/erased. If #WP

pin is tied to low state before power on, the other sectors will not be

programmed/erased.

In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output
data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the
DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be
erased/programmed. But the hardware protection will override the software lock setting, i.e., while the
#TBL

pin is trapped at low state, the top boot block cannot be programmed/erased whether the output

data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL

will lock the whole 64Kbytes top boot

W39V040A

- 4 -

block, it will not partially lock the 16Kbytes boot block. You can check the DQ2/DQ3 at the address
7FFF2 to see whether the #TBL/#WP

is in low or high state. If the DQ2 is "0", it means the #TBL

is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend
on software setting. On the other hand, if the DQ2 is "1", it means the #TBL

pin is tied to low state, then

boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP

state. If the DQ3 is "0", it means the #WP

pin is in high state, then all the sectors except the boot block

can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot
block are programmed/erased inhibited.

To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
within fast 100 mS (max). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the other memory sectors
will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state
before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase
operation if the "boot block programming lockout feature" is not activated. The device will automatically
return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be
used to detect end of erase cycle.

Sector/Page Erase Operation

Sector/page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing
the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command.
The sector/page address (any address location within the desired sector/page) is latched on the rising
edge of R/C, while the command (30H/50H) is latched on the rising edge of #WE in programmer mode.
Sector/page erase does not require the user to program the device prior to erase. When erasing a
sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is
not required to provide any controls or timings during these operations.
The automatic sector/page erase begins after the erase command is completed, right from the rising
edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on
DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be
performed at an address within any of the sectors/pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.

Program Operation

The W39V040A is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50

µS max. -

) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be

used to detect end of program cycle.

W39V040A

Publication Release Date: December 19, 2002

- 5 -

Revision A2

Hardware Data Protection

The integrity of the data stored in the W39V040A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V

Power Up/Down Detection: The programming and read operation is inhibited when V

is less

than 1.5V typical.

(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents

inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the devices will automatically time-out 5

mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W39V040A includes a data polling feature to indicate the end of a program or erase cycle. When
the W39V040A is in the internal program or erase cycle, any attempts to read DQ

of the last byte

loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and become logical

"1" or true data when the erase cycle has been completed.

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W39V040A provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

Multi-Chip Operation

Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to
16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.

Register

There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.

General Purpose Inputs Register
This register reads the states of GPI[4:0] pins on the W39V040A. This is a pass-through register, which
can be read via memory address FFBxE100(hex). The "x" in the addresses represents the ID [3:0] pin
straps. Since it is pass-through register, there is no default value.

W39V040A

- 6 -

GPI Register

BIT FUNCTION

- 5

Reserved

Read GPI4 pin status

Read GPI3 pin status

Read GPI2 pin status

Read GPI1 pin status

Read GPI0 pin status

Product Identification Registers
There is an alternative software method (six commands bytes) to read out the Product Identification in
both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment
can automatically matches the device with its proper erase and programming algorithms.
In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID for programmer interface mode. A read from address 0000(hex) outputs the
manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 3D(hex)." The
product ID operation can be terminated by a three-byte command sequence or an alternate one-byte
command sequence (see Command Definition table for detail).

Identification Input Pins ID[3:0]

These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot
device should be 0000b. And all the subsequent parts should use the up-count strapping. Note that a 1M
byte ROM will occupy two Ids. For example: a 1MByte ROM's ID is 0000b, the next ROM's ID is 0010b.
These pins all are pulled down with internal resistor.

Memory Address Map

There are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M
system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS storage
space, the ID[2:0] pins are inverted in the ROM and are compared to address lines [21:19]. ID[3] can be
used as like active low chip-select pin.

The 32Mbit address space is as below:

BLOCK LOCK

ADDRESS

RANGE

4M Byte BIOS ROM

None

FFFF, FFFFh: FFC0, 0000h

The ROM responds to 640K (top 512K + bottom 128K) byte pages based on the ID pins strapping
according to the following table:

ID[2:0] PINS

ROM BASED ADDRESS RANGE

000

FFFF, FFFFh: FFF8, 0000h & 000F, FFFFh: 000E, 00000h

001

FFF7, FFFFh: FFF0, 0000h

010

FFEF, FFFFh: FFE8, 0000h

011

FFE7, FFFFh: FFE0, 0000h

W39V040A

Publication Release Date: December 19, 2002

- 7 -

Revision A2

Continued

100

FFDF, FFFFh: FFD8, 0000h

101

FFD7, FFFFh: FFD0, 0000h

110

FFCF, FFFFh: FFC8, 0000h

111

FFC7, FFFFh: FFC0, 0000h

Table of Operating Modes

Operating Mode Selection - Programmer Mode

PINS

MODE

#OE #WE #RESET ADDRESS

DQ.

Read

AIN

Dout

Write

AIN

Din

Standby

X X V

High

X V

High

Z/DOUT

Write Inhibit

X V

High

Z/DOUT

Output Disable

X V

High

Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".

Standard LPC Memory Cycle Definition

FIELD

NO. OF

CLOCKS

DESCRIPTION

Start 1

"0000b" appears on LPC bus to indicate the initial

Cycle Type & Dir

"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.

TAR 2

Turned Around Time

Addr. 8

Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)

Sync. N

Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.

Data 2

Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)

W39V040A

- 8 -

Table of Command Definition

COMMAND

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles

Addr. Data

OUT

Chip Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 10

Sector Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

(3)

Page Erase

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

(4)

Byte Program

5555 AA

2AAA 55

5555 A0

Top Boot Block Lockout
64K/16KByte

5555 AA

2AAA 55

5555 80

5555 AA

2AAA 55

5555 40/70

Product ID Entry

5555 AA

2AAA 55

5555 90

Product ID Exit

(1)

5555 AA

2AAA 55

5555 F0

Product ID Exit

(1)

XXXX F0

Notes:

1. The cycle means the write command cycle not the LPC clock cycle.

2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address

A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]

3. Address Format: A14

- A0 (Hex); Data Format: DQ7 - DQ0 (Hex)

4. Either one of the two Product ID Exit commands can be used.

5. SA: Sector Address

SA = 7XXXXh for Unique Sector7 (Boot Sector)

SA = 3XXXXh for Unique Sector3

SA = 6XXXXh for Unique Sector6

SA = 2XXXXh for Unique Sector2

SA = 5XXXXh for Unique Sector5

SA = 1XXXXh for Unique Sector1

SA = 4XXXXh for Unique Sector4

SA = 0XXXXh for Unique Sector0

6. PA: Page Address

PA = 7FXXXh for Page 15 in Sector 7

PA = 7EXXXh for Page 14 in Sector 7

PA = 7DXXXh for Page 13 in Sector 7

PA = 7CXXXh for Page 12 in Sector 7

PA = 7BXXXh for Page 11 in Sector 7

PA = 7AXXXh for Page 10 in Sector 7

PA = 79XXXh for Page 9 in Sector 7

PA = 78XXXh for Page 8 in Sector 7

PA = 77XXXh for Page 7 in Sector 7

PA = 76XXXh for Page 6 in Sector 7

PA = 75XXXh for Page 5 in Sector 7

PA = 74XXXh for Page 4 in Sector 7

PA = 73XXXh for Page 3 in Sector 7

PA = 72XXXh for Page 2 in Sector 7

PA = 71XXXh for Page 1 in Sector 7

PA = 70XXXh for Page 0 in Sector 7

PA =

6FXXXh

60XXXh

for

Page 15

Page 0

Sector 6

(Reference

to the

first

column)

PA =

5FXXXh

50XXXh

for

Page 15

Page 0

Sector 5

(Reference

to the

first

column)

PA =

4FXXXh

40XXXh

for

Page 15

Page 0

Sector 4

(Reference

to the

first

column)

PA =

3FXXXh

30XXXh

for

Page 15

Page 0

Sector 3

(Reference

to the

first

column)

PA =

2FXXXh

20XXXh

for

Page 15

Page 0

Sector 2

(Reference

to the

firs

column)

PA =

1FXXXh

10XXXh

for

Page 15

Page 0

Sector 1

(Reference

to the

first

column)

PA =

0FXXXh

00XXXh

for

Page 15

Page 0

Sector 0

(Reference

to the

first

column)

W39V040A

- 12 -

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Load data 55

address 2AAA

Load data 90

address 5555

Pause 10 S

Product

Identification

and Boot Block

Lockout Detection

Mode (3)

Read address = 00000

data = DA

Read address = 00001

data = 3D

Read address = 00002

DQ0/DQ1 of data outputs

= 1/0

(4)

Product

Identification Exit (6)

Load data 55

address 2AAA

Load data F0

address 5555

Normal Mode

(5)

(2)

Load data AA

address 5555

Load data AA

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7

- DQ0 (Hex); Address Format: A14 - A0 (Hex)

(2) A1

- A18 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in "identification and boot block lockout detection" mode if power down.
(4) The DQ[3:0] to indicate the sectors protect status as below:

DQ0

DQ1

DQ2

DQ3

64Kbytes Boot Block
Unlocked by Software

16Kbytes Boot Block
Unlocked by Software

64Kbytes Boot Block Unlocked
by #TBL hardware trapping

Whole Chip Unlocked by #WP hardware
trapping Except Boot Block

64Kbytes Boot Block
Locked by Software

16Kbytes Boot Block
Locked by Software

64Kbytes Boot Block Locked by
#TBL hardware trapping

Whole Chip Locked by #WP hardware
trapping Except Boot Block

(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the "product identification/boot block lockout

detection."

W39V040A

- 14 -

7. DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING

UNIT

Power Supply Voltage to V

Potential

-0.5 to +4.6

Operating Temperature

0 to +70

°C

Storage Temperature

-65 to +150

°C

D.C. Voltage on Any Pin to Ground Potential

-0.5 to V

+0.5

Transient Voltage (<20 nS) on Any Pin to Ground Potential

-1.0 to V

+0.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Programmer Interface Mode DC Operating Characteristics

= 3.3V

± 0.3V, V

= 0V, T

= 0 to 70

° C)

LIMITS

PARAMETER SYM.

TEST

CONDITIONS

MIN. TYP. MAX.

UNIT

Power Supply
Current

In Read or Write mode, all DQs open
Address inputs = 3.0V/0V, at f = 3 MHz

- 10 20

Input Leakage
Current

= V

to V

µA

Output Leakage
Current

OUT

= V

to V

µA

Input Low Voltage

- -0.3

0.8

Input High Voltage

- 2.0

+0.5

Output Low Voltage

= 2.1 mA

0.45

Output High Voltage V

= -0.1mA

2.4

W39V040A

Publication Release Date: December 19, 2002

- 15 -

Revision A2

LPC Interface Mode DC Operating Characteristics

= 3.3V

± 0.3V, V

= 0V, T

= 0 to 70

° C)

LIMITS

PARAMETER SYM.

TEST

CONDITIONS

MIN. TYP. MAX.

UNIT

Power Supply Current

All I

out

= 0A, CLK = 33 MHz,

in LPC mode operation.

- 12.5 20

CMOS Standby
Current

Isb1

#LFRAM = 0.9 V

, CLK = 33 MHz,

all inputs = 0.9 V

/ 0.1 V

- 5 25

µA

TTL Standby Current

Isb2

#LFRAM = 0.1 V

, CLK = 33 MHz,

all inputs = 0.9 V

/ 0.1 V

- 3 10

Input Low Voltage

- -0.5

0.3

Input Low Voltage of
#INIT Pin

ILI

- -0.5

0.2

Input High Voltage

0.5

Input High Voltage of
#INIT Pin

IHI

- 1.35V

0.5

Output Low Voltage

OL1

= 1.5 mA

0.1

Output High Voltage

OH1

= -0.5 mA

0.9

- V

Power-up Timing

PARAMETER SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

100

µS

Power-up to Write Operation

. WRITE

Capacitance

= 3.3V, T

= 25

° C, f = 1 MHz)

PARAMETER SYMBOL

CONDITIONS MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

W39V040A

Publication Release Date: December 19, 2002

- 17 -

Revision A2

AC Characteristics

Read Cycle Timing Parameters

= 3.3V

±0.3V, V

= 0V, T

= 0 to 70

° C)

W39V040A

PARAMETER

SYMBOL

MIN. MAX.

UNIT

Read Cycle Time

300 - nS

Row/Column Address Set Up Time

50 - nS

Row/Column Address Hold Time

50 - nS

Address Access Time

- 175 nS

Output Enable Access Time

- 75 nS

#OE Low to Act Output

OLZ

0 - nS

#OE High to High-Z Output

OHZ

- 35 nS

Output Hold from Address Change

0 - nS

Write Cycle Timing Parameters

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Reset Time

RST

1 - -

µS

Address Setup Time

50 - - nS

Address Hold Time

50 - - nS

R/#C to Write Enable High Time

CWH

50 - - nS

#WE Pulse Width

100 - - nS

#WE High Width

WPH

100 - - nS

Data Setup Time

50 - - nS

Data Hold Time

50 - - nS

#OE Hold Time

OEH

0 - - nS

Byte Programming Time

- 35 50

µS

Sector/Page Erase Cycle Time

PEC

- 20

Chip Erase Cycle Time

- 75

100

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

Data Polling and Toggle Bit Timing Parameters

W39V040A

PARAMETER

SYMBOL

MIN. MAX.

UNIT

#OE to Data Polling Output Delay

OEP

40 nS

#OE to Toggle Bit Output Delay

OET

- 40 nS

W39V040A

Publication Release Date: December 19, 2002

- 19 -

Revision A2

Timing Waveforms for Programmer Interface Mode, continued

Program Cycle Timing Diagram

A[10:0]

Byte 0

Byte 1

Byte 2

Internal Write Start

DQ[7:0]

Byte Program Cycle

WPH

5555

2AAA

Programmed Address

Data-In

Byte 3

Note: The internal address A[18:0] are converted from external Column/Row address

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

(Internal A[18:0])

#OE

#WE

R/#C

#DATA Polling Timing Diagram

A[10:0]

DQ7

OEP

BP or

(Internal A[18:0])

#OE

#WE

R/#C

W39V040A

- 20 -

Timing Waveforms for Programmer Interface Mode, continued

Toggle Bit Timing Diagram

A[10:0]

DQ6

OET

BP or

#OE

#WE

R/#C

Boot Block Lockout Enable Timing Diagram

SB2

SB1

SB0

DQ[7:0]

#OE

#WE

SB3

SB4

SB5

WPH

40/70

Note: The internal address A[18:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

(Internal A[18:0])

SIX-byte code for Boot Block Lockout command

5555

2AAA

5555

2AAA

5555

A[10:0]

R/#C

When 40(hex) is loaded, the 64KByte are locked; while 70(hex) is loaded, the 16KByte is locked.

W39V040A

Publication Release Date: December 19, 2002

- 21 -

Revision A2

Timing Waveforms for Programmer Interface Mode, continued

Chip Erase Diagram

DQ[7:0]

SB2

SB1

SB0

SB3

SB4

SB5

Internal Erasure Starts

WPH

Note: The internal address A[18:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

(Internal A[18:0])

Six-byte code for 3.3V-only software chip erase

5555

2AAA

5555

2AAA

5555

A[10:0]

#OE

#WE

R/#C

Sector/Page Erase Timing Diagram

SB2

SB1

SB0

A[10:0]

DQ[7:0]

SB3

SB4

SB5

Internal Erase starts

Six-byte code for 3.3V-only

Sector/Page Erase

WPH

5555

2AAA

5555

2AAA

SA/PA

30/50

SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"

Note: The internal address A[18:0] are converted from external Column/Row address.

Column/Row Address are mapped to the Low/High order internal address.

i.e. Column Address A[10:0] are mapped to the internal A[10:0],

Row Address A[7:0] are mapped to the internal A[18:11].

(Internal A[18:0])

#OE

#WE

R/#C

W39V040A

- 22 -

10. LPC INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels

0.6 V

to 0.2 V

Input Rise/Fall Slew Rate

1 V/nS

Input/Output Timing Level

0.4 V

/ 0.4 V

Output Load

1 TTL Gate and C

= 10 pF

Read/Write Cycle Timing Parameters

= 3.3V

±0.3V, V

= 0V, T

= 0 to 70

° C)

W39V040A

PARAMETER

SYMBOL

MIN. MAX.

UNIT

Clock Cycle Time

CYC

30 - nS

Input Set Up Time

7 -

Input Hold Time

0 -

Clock to Data Valid

2 11

Note: Minimum and Maximum time has different loads. Please refer to PCI specification.

Reset Timing Parameters

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Stable to Reset Active

PRST

1 - - mS

Clock Stable to Reset Active

KRST

100 - -

µS

Reset Pulse Width

RSTP

100 - - nS

Reset Active to Output Float

RSTF

- - 50 nS

Reset Inactive to Input Active

RST

1 - -

µS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.

Ref. to the AC testing condition.

W39V040A

Publication Release Date: December 19, 2002

- 23 -

Revision A2

11. TIMING WAVEFORMS FOR LPC INTERFACE MODE

Read Cycle Timing Diagram

CYC

LAD[3:0]

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

A[15:12]

Address

Sync

TAR

1111b

Tri-State 0000b

A[11:8]

A[7:4]

A[3:0]

Data out 2 Clocks

D[7:4]

Data

D[3:0]

0000b

A[19:16]

A[31:28]

A[23:20]

A[27:24]

#LFRAM

#RESET

Write Cycle Timing Diagram

TCYC

LAD[3:0]

Start

Memory

Write

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

011Xb

0000b

A[15:12]

Load Data in 2 Clocks

D[7:4]

Address

Sync

TAR

Data

1111b

Tri-State

0000b

THD

TSU

A[11:8]

A[7:4]

A[3:0]

D[3:0]

0000b

A[19:16]

A[31:28]

A[23:20]

A[27:24]

#LFRAM

#RESET

W39V040A

- 24 -

Timing Waveforms for LPC Interface Mode, continued

Program Cycle Timing Diagram

LAD[3:0]

1st Start

Memory

Write

Cycle

Load Address "5555" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA" in 2 Clocks

1010b

Write the 1st command to the device in LPC mode.

2nd Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 2nd command to the device in LPC mode.

3rd Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "A0"

in 2 Clocks

1010b

0000b

Write the 3rd command to the device in LPC mode.

4th Start

Load Ain in 8 Clocks

CLK

1 Clock

TAR

Sync

Internal

program start

TAR

1 Clock

2 Clocks

011Xb

0000b

A[15:12]

Load Din in 2 Clocks

D[7:4]

Write the 4th command(target location to be programmed) to the device in LPC mode.

A[11:8]

A[7:4]

A[3:0]

D[3:0]

1111b

Tri-State

0000b

Data

Address

Sync

TAR

Data

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Internal

program start

A[19:16]

A[31:28]

A[23:20]

A[27:24]

LAD[3:0]

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

Publication Release Date: December 19, 2002

- 25 -

Revision A2

Timing Waveforms for LPC Interface Mode, continued

#DATA Polling Timing Diagram

Read the DQ7 to see if the internal write complete or not.

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

XXXXb

XXAn[17:16]

An[15:12]

Address

Sync

TAR

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Data out 2 Clocks

Dn7,xxx

Data

XXXXb

0000b

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

Data

0000b

When internal write complete, the DQ7 will equal to Dn7.

Dn7,xxx

XXXXb

An[15:12]

An[11:8]

An[7:4]

An[3:0]

LAD[3:0]

1st Start

Load Address "An" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

An[15:12]

Load Data "Dn"

in 2 Clocks

Dn[7:4]

Write the last command(program or erase) to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Dn[3:0]

Memory

Write

Cycle

0000b

1 Clock

A[19:16]

A[31:28]

A[23:20]

A[27:24]

An[31:28]

An[27:24]

An[23:20]

An[19:16]

LAD[3:0]

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

- 26 -

Timing Waveforms for LPC Interface Mode, continued

Toggle Bit Timing Diagram

Read the DQ6 to see if the internal write complete or not.

LAD[3:0]

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

XXXXb

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

X,D6,XXb

Data

XXXXb

0000b

LAD[3:0]

Start

Memory

Read

Cycle

Load Address in 8 Clocks

CLK

1 Clock

TAR

Next Start

1 Clock

2 Clocks

1 Clock

010Xb

0000b

XXXXb

Address

Sync

TAR

1111b

Tri-State

0000b

Data out 2 Clocks

Data

0000b

When internal write complete, the DQ6 will stop toggle.

X,D6,XXb

XXXXb

LAD[3:0]

1st Start

Load Address "An" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

An[15:12]

Load Data "Dn"

in 2 Clocks

Dn[7:4]

Write the last command(program or erase) to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

An[11:8]

An[7:4]

An[3:0]

Dn[3:0]

XXAn[17:16]

Memory

Write

Cycle

XXXXb

1 Clock

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

Publication Release Date: December 19, 2002

- 27 -

Revision A2

Timing Waveforms for LPC Interface Mode, continued

Boot Block Lockout Enable Timing Diagram

CLK

LAD[3:0

]

1st Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 1st command to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

Memory

Write

Cycle

CLK

2nd Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clocks

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 2nd command to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

Memory

Write

Cycle

LAD[3:0

]

CLK

3rd Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "80"

in 2 Clocks

1000b

0000b

Write the 3rd command to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

Memory

Write

Cycle

LAD[3:0

]

CLK

4th Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 4th command to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

Memory

Write

Cycle

LAD[3:0

]

CLK

5th Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

1 Clock

2 Clocks

Start next

command

1 Clock

011Xb

0000b

XXXXb

XXXX

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 5th command to the device in LPC mode.

Address

Sync

TAR

Data

1111b

Tri-State

0000b

Memory

Write

Cycle

LAD[3:0

]

CLK

6th Start

Load Address "5555" 8 Clocks

1 Clock

TAR

Sync

TAR

1 Clock

2 Clocks

011Xb

0000b

XXXXb

X101b

Load Data "40"

or "70" in 2 Clocks

0100b

Write the 6th command to the device in LPC mode.

0101b

0000b

1111b

Tri-State

0000b

Data

Address

Memory

Write

Cycle

0111b

LAD[3:0

]

Start next

command

1 Clock

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

- 28 -

Timing Waveforms for LPC Interface Mode, continued

Chip Erase Timing Diagram

6th Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Sync

Internal

erase start

TAR

1 Clock

011Xb

0000b

XXXXb

X101b

Load Data "10"

in 2 Clocks

0001b

Write the 6th command to the device in LPC mode.

0101b

0000b

1111b

Tri-State

0000b

Data

Address

LAD[3:0]

1st Start

CLK

TAR

Start next

command

011Xb

0000b

XXXXb

X101b

0101b

1010b

LAD[3:0]

CLK

LAD[3:0]

CLK

LAD[3:0]

CLK

Address

Sync

TAR

Data

Load Address "5555" in 8 Clocks

1 Clock

2 Clocks

1 Clock

Load Data "AA"

in 2 Clocks

Write the 1st command to the device in LPC mode.

2nd Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 2nd command to the device in LPC mode.

3rd Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "80"

in 2 Clocks

1000b

0000b

Write the 3rd command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

4th Start

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 4th command to the device in LPC mode.

5th Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 5th command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

LAD[3:0]

CLK

LAD[3:0]

CLK

2 Clocks

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Internal

erase start

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

Publication Release Date: December 19, 2002

- 29 -

Revision A2

Timing Waveforms for LPC Interface Mode, continued

Sector Erase Timing Diagram

6th Start

Load Sector Address in 8 Clocks

1 Clock

TAR

Sync

Internal

erase start

TAR

1 Clock

2 Clocks

011Xb

0000b

XXXXb

SA[18:16]

Load Data "30"

in 2 Clocks

0011b

Write the 6th command(target sector to be erased) to the device in LPC mode.

0000b

1111b

Tri-State

0000b

Data

Address

1st Start

Load Address "5555" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 1st command to the device in LPC mode.

CLK

Address

Sync

TAR

Data

2nd Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 2nd command to the device in LPC mode.

3rd Start

Load Address "5555" in 8 Clocks

1 Clocks

TAR

Start next

command

1 Clocks

2 Clocks

1 Clocks

011Xb

0000b

XXXXb

X101b

0101b

Load Data "80"

in 2 Clocks

1000b

0000b

Write the 3rd command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

4th Start

Memory

Write

Cycle

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 4th command to the device in LPC mode.

5th Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 5th command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

CLK

XXXXb

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Internal

erase start

LAD[3:0]

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

- 30 -

Timing Waveforms for LPC Interface Mode, continued

Page Erase Timing Diagram

6th Start

Load Page Address in 8 Clocks

1 Clock

TAR

Sync

Internal

erase start

TAR

1 Clock

2 Clocks

011Xb

0000b

XXXXb

PA[15:12]

Load Data "50"

in 2 Clocks

0101b

Write the 6th command(target page to be erased) to the device in LPC mode.

0000b

1111b

Tri-State

0000b

Data

Address

1st Start

Load Address "5555" in 8 Clocks

CLK

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 1st command to the device in LPC mode.

CLK

Address

Sync

TAR

Data

2nd Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 2nd command to the device in LPC mode.

3rd Start

Load Address "5555" in 8 Clocks

1 Clocks

TAR

Start next

command

1 Clocks

2 Clocks

1 Clocks

011Xb

0000b

XXXXb

X101b

0101b

Load Data "80"

in 2 Clocks

1000b

0000b

Write the 3rd command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

1111b

Tri-State

0000b

4th Start

Memory

Write

Cycle

Load Address "5555" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X101b

0101b

Load Data "AA"

in 2 Clocks

1010b

Write the 4th command to the device in LPC mode.

5th Start

Load Address "2AAA" in 8 Clocks

1 Clock

TAR

Start next

command

1 Clock

2 Clocks

1 Clock

011Xb

0000b

XXXXb

X010b

1010b

Load Data "55"

in 2 Clocks

0101b

Write the 5th command to the device in LPC mode.

Address

Sync

TAR

Data

Sync

TAR

Data

1111b

Tri-State

0000b

1111b

Tri-State

0000b

CLK

LAD[3:0]

CLK

XXXXb

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Memory

Write

Cycle

Internal

erase start

PA[18:16]

LAD[3:0]

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

#LFRAM

#RESET

W39V040A

- 32 -

12. ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER SUPPLY

CURRENT MAX.

(mA)

STANDBY V

CURRENT MAX.

(mA)

PACKAGE

W39V040AP 11

20 10

32L

PLCC

W39V040AQ 11

20 10

32L

STSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

13. HOW TO READ THE TOP MARKING

Example: The top marking of 32-pin STSOP W39V040AQ

line: Winbond logo

line: the part number: W39V040AQ

line: the lot number

line: the tracking code: 149 O B SA

149: Packages made in '01, week 49
O: Assembly house ID: A means ASE, O means OSE, ... etc.
B: IC revision; A means version A, B means version B, ... etc.
SA: Process code

W39V040AQ

2138977A-A12

149OBSA

W39V040A

Publication Release Date: December 19, 2002

- 33 -

Revision A2

14. PACKAGE DIMENSIONS

32L PLCC

Notes:

D H

Seating Plane

1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusio
3. Controlling dimension: Inches
4. General appearance spec. should be based on final

visual inspection sepc.

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

b
c
D

A
A

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.95

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.490

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.510

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

32L STSOP

Min.

Dimension in Inches

Nom. Max. Min. Nom. Max.

Symbol

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.10

0.50

0.00

0.22

0.27

-----

0.21

12.40

8.00

14.00

0.50

0.60

0.70

0.80

0.10

0.047

0.006

0.041

0.040

0.035

0.007

0.009

0.010

0.004

-----

0.008

0.488

0.315

0.551

0.020

0.024

0.028

0.031

0.000

0.004

0.002

A
A

b
c

Dimension in mm

A
A

W39V040A

- 34 -

15. VERSION HISTORY

VERSION DATE PAGE

DESCRIPTION

October 8, 2002

Initial Issued

Dec. 19, 2002

Modify PGM mode power supply current (Icc)
parameter from 20 mA (typ.) to 10 mA (typ.)
and 30 mA (max.) to 20 mA (max.)

1, 15, 32

Modify LPC mode power supply current (Icc)
parameter from 40 mA (typ.) to 12.5 mA (typ.)
and 60 mA (max.) to 20 mA (max.)

Modify CMOS standby current (Isb1) parameter
from 20

µA (typ.) to 5 µA (typ.) and 100 µA (max.)

to 25

µA (max.)

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

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