W39V040FB Data Sheet
512K
8 CMOS FLASH MEMORY
WITH FWH INTERFACE
Publication Release Date: April 14, 2005
- 1 -
Revision A3
Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................... 3
2.
FEATURES ................................................................................................................................. 3
3.
PIN CONFIGURATIONS............................................................................................................. 4
4.
BLOCK DIAGRAM ...................................................................................................................... 4
5.
PIN DESCRIPTION..................................................................................................................... 4
6.
FUNCTIONAL DESCRIPTION.................................................................................................... 5
6.1
Interface Mode Selection and Description..................................................................... 5
6.2
Read (Write) Mode ........................................................................................................ 5
6.3
Reset Operation............................................................................................................. 5
6.4
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ....................... 5
6.5
Sector Erase Command ................................................................................................ 6
6.6
Program Operation ........................................................................................................ 6
6.7
Hardware Data Protection ............................................................................................. 6
6.8
WRITE OPERATION STATUS...................................................................................... 6
7.
REGISTER FOR FWH MODE .................................................................................................... 8
7.1
General Purpose Inputs Register for FWH Mode.......................................................... 8
7.2
Product Identification Registers..................................................................................... 8
7.3
Block Locking Registers ................................................................................................ 8
7.4
Register Based Block Locking Value Definitions Table................................................. 9
7.5
Read Lock.................................................................................................................... 10
7.6
Write Lock .................................................................................................................... 10
7.7
Lock Down ................................................................................................................... 10
7.8
Product Identification Registers................................................................................... 10
8.
TABLE OF OPERATING MODES ............................................................................................ 10
8.1
Operating Mode Selection - Programmer Mode.......................................................... 10
8.2
Operating Mode Selection - FWH Mode...................................................................... 11
8.3
FWH Cycle Definition................................................................................................... 11
9.
TABLE OF COMMAND DEFINITION ....................................................................................... 11
9.1
Embedded Programming Algorithm ............................................................................ 12
9.2
Embedded Erase Algorithm......................................................................................... 13
9.3
Embedded #Data Polling Algorithm............................................................................. 14
9.4
Embedded Toggle Bit Algorithm.................................................................................. 15
W39V040FB
- 2 -
9.5
Software Product Identification and Boot Block Lockout Detection Acquisition Flow . 16
10.
ELECTRICAL CHARACTERISTICS ......................................................................................... 17
10.1
Absolute Maximum Ratings ......................................................................................... 17
10.2
Programmer interface Mode DC Operating Characteristics........................................ 17
10.3
FWH Interface Mode DC Operating Characteristics ................................................... 18
10.4
Power-up Timing.......................................................................................................... 18
10.5
Capacitance................................................................................................................. 18
10.6
Programmer Interface Mode AC Characteristics......................................................... 19
10.7
Read Cycle Timing Parameters................................................................................... 20
10.8
Write Cycle Timing Parameters................................................................................... 20
10.9
Data Polling and Toggle Bit Timing Parameters ......................................................... 20
11.
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 21
11.1
Read Cycle Timing Diagram........................................................................................ 21
11.2
Write Cycle Timing Diagram ........................................................................................ 21
11.3
Program Cycle Timing Diagram .................................................................................. 22
11.4
#DATA Polling Timing Diagram................................................................................... 22
11.5
Toggle Bit Timing Diagram .......................................................................................... 23
11.6
Sector Erase Timing Diagram ..................................................................................... 23
12.
FWH INTERFACE MODE AC CHARACTERISTICS................................................................ 24
12.1
AC Test Conditions...................................................................................................... 24
12.2
Read/Write Cycle Timing Parameters ......................................................................... 24
12.3
Reset Timing Parameters ............................................................................................ 24
13.
TIMING WAVEFORMS FOR FWH INTERFACE MODE.......................................................... 25
13.1
Read Cycle Timing Diagram........................................................................................ 25
13.2
Write Cycle Timing Diagram ........................................................................................ 25
13.3
Program Cycle Timing Diagram .................................................................................. 26
13.4
#DATA Polling Timing Diagram................................................................................... 27
13.5
Toggle Bit Timing Diagram .......................................................................................... 28
13.6
FGPI Register/Product ID Readout Timing Diagram................................................... 30
13.7
Reset Timing Diagram ................................................................................................. 30
14.
ORDERING INFORMATION..................................................................................................... 31
15.
HOW TO READ THE TOP MARKING...................................................................................... 31
16.
PACKAGE DIMENSIONS ......................................................................................................... 32
16.1
32L PLCC .................................................................................................................... 32
16.2
32L STSOP.................................................................................................................. 32
17.
VERSION HISTORY ................................................................................................................. 33
W39V040FB
Publication Release Date: April 14, 2005
- 3 -
Revision A3
1. GENERAL DESCRIPTION
The W39V040FB is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K
8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The device
can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
required for accelerated program. The unique cell architecture of the W39V040FB results in fast
program/erase operations with extremely low current consumption. This device can operate at two
modes, Programmer bus interface mode, Firmware Hub (FWH) bus interface mode. As in the
Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But
in the FWH interface mode, this device complies with the Intel FWH specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
Single 3.3-volt operations:
-
3.3-volt Read
-
3.3-volt Erase
-
3.3-volt Program
Fast Program operation:
-
Byte-by-Byte programming: 9
S (typ.)
(V
PP
= 12V)
-
Byte-by-Byte programming: 12
S (typ.)
(V
PP
= Vcc)
Fast
Erase
operation:
-
Sector erase 0.6 Sec. (typ.)
Fast Read access time: Tkq 11 nS
Endurance: 10K cycles (typ.)
Twenty-year data retention
8 Even sectors with 64K bytes
Any individual sector can be erased
Hardware protection:
-
#TBL supports 64-Kbyte Boot Block
hardware protection
-
#WP supports the whole chip except Boot
Block hardware protection
Low power consumption
-
Active current: 15 mA (typ. for FWH read
mode)
Automatic program and erase timing with
internal
V
PP
generation
End of program or erase detection
-
Toggle bit
-
Data polling
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC, 32L STSOP
32L PLCC Lead free, 32L STSOP Lead free
W39V040FB
- 4 -
3. PIN CONFIGURATIONS
Firmware Hub (FWH) Mode
#WE(FWH4)
DQ4(RSV)
DQ3(FWH3)
DQ7(RSV)
DQ6(RSV)
#OE(#INIT)
DQ5(RSV)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
32L STSOP
24
23
22
21
20
19
18
17
A3(ID3)
IC
R/#C(CLK)
NC
V DD
A10(FGPI4)
Vpp
A9(FGPI3)
A8(FGPI2)
#RESET
A7(FGPI1)
A6(FGPI0)
A2(ID2)
A1(ID1)
A0(ID0)
DQ2(FWH2)
DQ1(FWH1)
DQ0(FWH0)
A5(#WP)
A4(#TBL)
VSS
VSS
NC
NC
A
1
0
^
F
G
P
I
4
v
5
6
7
9
10
11
12
13
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
^
F
W
H
1
v
V
S
S
D
Q
6
^
R
S
V
v
#
R
E
S
E
T
V
D
D
R
/
#
C
^
C
L
K
v
A
9
^
F
G
P
I
3
v
32L PLCC
DQ0(FWH0)
A7(FGPI1)
A6(FGPI0)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)
A5(#WP)
IC
DQ7(RSV)
#WE(FWH4)
#OE(#INIT)
NC
A
8
^
F
G
P
I
2
v
D
Q
2
^
F
W
H
2
v
D
Q
3
^
F
W
H
3
v
D
Q
4
^
R
S
V
v
D
Q
5
^
R
S
V
v
V
SS
RY/#BY(RSV)
V
DD
NC
V
P
P
RY/#BY(RSV)
4. BLOCK DIAGRAM
Program-
mer
Interface
6FFFF
00000
20000
1FFFF
10000
0FFFF
#RESET
IC
A[10:0]
DQ[7:0]
#OE
#WE
R/#C
FWH
Interface
CLK
FWH4
FWH[3:0]
60000
5FFFF
64K BYTES BLOCK 0
30000
2FFFF
#INIT
#WP
#TBL
50000
4FFFF
40000
3FFFF
64K BYTES BLOCK 1
64K BYTES BLOCK 2
64K BYTES BLOCK 5
64K BYTES BLOCK 6
64K BYTES BLOCK 7
RY/#BY
64K BYTES BLOCK 3
64K BYTES BLOCK 4
7FFFF
70000
5. PIN DESCRIPTION
INTERFACE
SYM.
PGM
FWH
PIN NAME
IC
*
*
Interface Mode Selection
#RESET * *
Reset
#INIT *
Initialize
#TBL
*
Top Boot Block Lock
#WP
*
Write
Protect
CLK *
CLK
Input
FGPI[4:0] *
General
Purpose
Inputs
ID[3:0] *
Identification Inputs They
Are Internal Pull Down to
Vss
FWH[3:0] *
Address/Data
Inputs
FWH4
*
FWH Cycle Initial
R/#C *
Row/Column
Select
A[10:0] *
Address
Inputs
DQ[7:0] * Data
Inputs/Outputs
#OE *
Output
Enable
#WE *
Write
Enable
RY/#BY
*
Ready/ Busy
V
DD
*
*
Power
Supply
V
SS
*
*
Ground
V
PP
*
*
Accelerate Program
Power Supply
RSV * *
Reserved
Pins
NC
*
*
No Connection
W39V040FB
Publication Release Date: April 14, 2005
- 5 -
Revision A3
6. FUNCTIONAL DESCRIPTION
6.1 Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is
FWH interface mode. The IC (Mode) pin of the device provides the control between these two
interface modes. These interface modes need to be configured before power up or return from
#RESET
.
When IC (Mode) pin is set to V
DD
, the device will be in the Programmer mode; while the IC
(Mode) pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer
mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column
address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11].
And the column address are mapped to the lower internal address A[10:0]. For FWH mode, it
complies with the FWH Interface Specification, through the FWH[3:0] to communicate with the system
chipset .
6.2 Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040FB is controlled by #OE
(#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs).
#OE is the output control and is used to gate data from the output pins. The data bus is in high
impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined
by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for
further details.
6.3 Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the
device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all
outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device
will return to read or standby mode, it depends on the control signals.
6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There is a hardware method to protect the top boot block and other sectors. Before power on
programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased.
If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software
command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address
7FFF2(hex). You can check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin
is
in low or high state. If the DQ2 is "0", it means the #TBL
pin is tied to high state. In such condition,
whether boot block can be programmed/erased or not will depend on software setting. On the other
hand, if the DQ2 is "1", it means the #TBL
pin is tied to low state, then boot block is locked no matter
how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it
means the #WP
pin is in high state, then all the sectors except the boot block can be
programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot block
are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
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