W49F002U

256K

8 CMOS FLASH MEMORY

Publication Release Date: February 21, 2002

- 1 - Revision A6

GENERAL DESCRIPTION

The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K

8 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

not required. The unique cell architecture of the W49F002U results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory products).

The device can also be programmed and erased using standard EPROM programmers.

FEATURES

Single 5-volt operations:

5-volt Read

5-volt Erase

5-volt Program

Fast Program operation:

Byte-by-Byte programming: 35

S (typ.)

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 70/90/120 nS

Endurance: 10K cycles (typ.)

Ten-year data retention

Hardware data protection

One 16K byte Boot Block with Lockout

protection

Two 8K byte Parameter Blocks

Two Main Memory Blocks (96K, 128K) Bytes

Low power consumption

Active current: 25 mA (typ.)

Standby current: 20

A (typ.)

Automatic program and erase timing with

internal V

generation

End of program or erase detection

Toggle bit

Data polling

Latched address and data

TTL compatible I/O

JEDEC standard byte-wide pinouts

Available packages: 32-pin DIP, 32-pin

STSOP (8 mm

14 mm), 32-pin TSOP

(8 mm

20 mm)

and 32-pin-PLCC

W49F002U

- 2 -

PIN CONFIGURATIONS

DQ0

DQ1

DQ2

Vss

A16

A15

A12

#WE

A14

A13

A11

#OE

A10

#CE

DQ7

DQ6

DQ5

DQ4

DQ3

A17

32-pin

DIP

#RESET

DQ0

D
Q

V
s
s

D
Q

A14

A13

A11

#OE

A10

#CE

DQ7

A
1
2

A
1
6

D
D

A
1
5

32-pin
PLCC

A
1
7

E
S
E
T

32-pin
TSOP

A15

A12

A6
A5

#WE

A14

A13

A11

A16

A17

#RESET

DQ0

DQ1

DQ2

Vss

#OE
A10

#CE
DQ7
DQ6

DQ5

DQ4
DQ3

BLOCK DIAGRAM

CONTROL

OUTPUT

BUFFER

DECODER

#CE

#OE

#WE

A17

DQ0

VDD

VSS

DQ7

3FFFF

20000
1FFFF

38000
37FFF

3A000
39FFF

00000

3C000
3BFFF

PARAMETER
BLOCK2
8K BYTES

BOOT BLOCK
16K BYTES

PARAMETER
BLOCK1
8K BYTES

#RESET

MAIN MEMORY

BLOCK2

128K BYTES

MAIN MEMORY

BLOCK1

96K BYTES

PIN DESCRIPTION

SYMBOL

PIN NAME

#RESET

Reset

A17

Address Inputs

DQ0

DQ7

Data Inputs/Outputs

#CE

Chip Enable

#OE

Output Enable

#WE

Write Enable

Power Supply

Ground

W49F002U

Publication Release Date: February 21, 2002

- 3 - Revision A6

FUNCTIONAL DESCRIPTION

Device Operation

Read Mode

The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for details.

Write Mode

Device erase and program are accomplished via the command register. The content of the register
serves as inputs to the internal state machine. The state machine outputs dictate the function of the
device.

The command register itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information needed to execute the
command. The command register is written to bring #WE to logic low state when #CE is at logic low
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens
first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing
parameters.

Standby Mode

There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin.

A CMOS standby mode is achieved with the

#CE

input held at

-0.3V. Under this condition the current

is typically reduced to less than 100

A. A TTL standby mode is achieved with the #CE pin held at V

Under this condition the current is typically reduced to less than 3 mA.

In the standby mode the outputs are in the high impedance state, independent of the #OE input.

Output Disable Mode

With the #OE input at a logic high level (V

), output from the device is disabled. This will cause the

output pins to be in a high impedance state.

Auto-select Mode

The auto-select mode allows the reading of a binary code from the device and will identify its
manufacturer and type. This mode is intended to be used by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V

(11.5V to 12.5V) on address pin A9.

Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from V

to V

. All addresses are don

t cares except A0 and A1 (see "Auto-select Codes"). Note: The

hardware SID read function is not included in all parts; please refer to Ordering Information for
details.

W49F002U

- 4 -

The manufacturer and device codes may also be read via the command register; i.e., the W49F002U

is erased or programmed in a system without access to high voltage on the A9 pin. The command
sequence is illustrated in "Auto-select Codes".

Byte 0 (A0 = V

) represents the manufacturer

s code (Winbond = DAh) and byte 1 (A0 = V

) the

device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the
Auto-select, A1 must be V

Reset Mode: Hardware Reset

The #RESET pin provides a hardware method of resetting the device to reading array data. When the
system drives the #RESET pin low for at least a period of t

, the device immediately terminates any

operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.

Current is reduced for the duration of the #RESET pulse. When #RESET is held at V

, the device

enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode.

The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the
Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

Data Protection

The W49F002U

is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device
automatically resets the internal state machine in the Read mode. Also, with its control register
architecture, alteration of the memory contents only occurs after successful completion of specific
multi-bus cycle command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from V

power-up and power-down transitions or system noise.

Low V

Inhibit

To avoid initiation of a write cycle during V

power-up and power-down, the W49F002U locks out

when V

< 2.5V. The write and read operations are inhibited when V

is less than 2.5V typical. The

W49F002U

ignores all write and read operations until V

> 2.5V. The user must ensure that the

control pins are in the correct logic state when V

> 2.5V to prevent unintentional writes.

Write Pulse "Glitch" Protection

Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of #OE = V

, #CE = V

, or #WE = V

. To initiate a write cycle

#CE and #WE must be a logical zero while #OE is a logical one.

Power-up Write and Read Inhibit

Power-up of the device with #WE = #CE = VIL and #OE = V

will not accept commands on the rising

edge of #WE. The internal state machine is automatically reset to the read mode on power-up.

W49F002U

Publication Release Date: February 21, 2002

- 5 - Revision A6

Command Definitions

Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read
mode.

Read Command

The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.

The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.

Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

Auto-select Command

Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto the address lines is not generally a desirable system design
practice.

The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAh. A read cycle from address XX01H returns the device code (W49F002U =
0Bh).

Byte Program Command

The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later
and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of
#CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm.
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.

The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.

W49F002U

- 6 -

Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.

Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot
be programmed back to a "1". Only erase operations can convert "0"s to "1"s.

Refer to the Embedded Programming Algorithm using typical command strings and bus operations.

Chip Erase Command

Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase
command.

Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each sector at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.

The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.

Refer to the Embedded Erase Algorithm using typical command strings and bus operations.

Sector Erase Command

Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase
command. The sector address (any address location within the desired sector) is latched on the falling
edge of #WE, while the command (30H) is latched on the rising edge of #WE.

Sector erase does not require the user to program the device prior to erase. When erasing a sector
or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.

The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase
command pulse and terminates when the data on DQ7, Data Polling, is "1."

Refer to the Embedded Erase Algorithm using typical command strings and bus operations.

Write Operation Status

DQ7: Data Polling

The W49F002U device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.

During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.

During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.

The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm".

W49F002U

Publication Release Date: February 21, 2002

- 7 - Revision A6

For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
#WE pulse.

Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while
the output enable (#OE) is asserted low. This means that the device is driving status information on
DQ7 at one instant of time and then that byte

s valid data at the next instant of time. Depending on

when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0
DQ6 may be still invalid. The valid data on DQ0

DQ7 will be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, or sector erase time-out (see "Command Definitions").

See " #DATA Polling During Embedded Algorithm Timing Diagrams".

DQ6: Toggle Bit

The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the
Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active
during the sector erase time-out.

TABLE OF OPERATING MODES

Device Bus Operations

MODE

PIN

#CE #OE

#WE #RESET A0

A17

DQ0

DQ7

Read

Ain

Dout

Write

Ain

Din

Write Inhibit

High Z/DOUT

Standby

High Z

Output Disable

High Z

Reset

High Z

W49F002U

- 8 -

Auto-select Codes (High Voltage Method)

DESCRIPTION

#CE

#OE

#WE

OTHER

ADD

DQ7

TO DQ0

Manufacturer ID: Winbond

DAh

Device ID: W49F002U
(Top Boot Block)

0Bh

Notes:

1. SA = Sector Address, X = Don

t Care. Sector Protection Verification: 01h (protected); 00h (unprotected).

2. The hardware SID read function is not included in all parts; please refer to Ordering Information for details.

Hardware Sequence Flags

OPERATION

DQ7

DQ6

(Note)

Embedded Program Algorithm

#DQ7

Toggle

Standard Mode

Embedded Erase Algorithm

Toggle

Note: DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Command Definition

(1)

COMMAND

No. of

1th Cycle

2nd Cycle

3rd Cycle

4th Cycle

5th Cycle

6th Cycle

DESCRIPTION

Cycles

Addr. Data

Addr. Data Addr. Data Addr. Data

Addr. Data Addr. Data

Read

AIN DOUT

Chip Erase

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)

Byte Program

5555 AA 2AAA 55 5555 A0 AIN DIN

Boot Block Lockout

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID Entry

5555 AA 2AAA 55 5555 90

Product ID Exit

(2)

5555 AA 2AAA 55 5555 F0

Product ID Exit

(2)

XXXX F0

Notes:

1. Address Format: A14

A0 (Hex); Data Format: DQ7

DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA means: Sector Address

If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated,
nothing will happen and the device will go back to read mode after 100nS.

If the Boot Block programming lockout feature is not activated, this command will erase Boot Block.

If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1.

If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2.

If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1.

If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2.

W49F002U

- 12 -

Software Product Identification and Boot Block Lockout Detection Acquisition
Flow

Product

Identification

Entry (1)

Load data 55

address 2AAA

Load data 90

address 5555

Pause 10 S

Product

Identification

and Boot Block
Lockout Detection

Mode (3)

Read address = 0000

data = 00DA

Read address = 0001

data = 00AE

Read address = 0002

data in DQ0 =1/0

(4)

Product

Identification Exit(6)

Load data 55

address 2AAA

Load data F0

address 5555

Normal Mode

(5)

(2)

Load data AA

address 5555

Load data AA

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ15

DQ8 (Don't Care), DQ7

DQ0 (Hex); Address Format: A14

A0 (Hex)

(2) A1

A16 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification and boot block lockout detection mode if power down.

(4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is
inactivated and the block can be programmed.

(5) The device returns to standard operation mode.

(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.

W49F002U

- 14 -

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to Vss

Potential

-0.5 to +7.0

Operating Temperature

0 to +70

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential Except A9

-0.5 to V

+1.0

Transient Voltage (<20 nS) on Any Pin to Ground Potential

-1.0 to V

+1.0

Voltage on A9 Pin to Ground Potential

-0.5 to 12.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

DC Operating Characteristics

= 5.0V

, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP. MAX.

Power Supply
Current

#CE = #OE = V

, #WE = V

all DQs open

Address inputs = V

, at f = 5 MHz

Standby V

Current

(TTL input)

#CE = V

, all DQs open

Other inputs = V

Standby V

Current

(CMOS input)

2 #CE = V

-0.3V, all DQs open

Other inputs = V

-0.3V/ Vss

100

Input Leakage
Current

= Vss to V

Output Leakage
Current

OUT

= Vss to V

Input Low Voltage

-0.3

0.8

Input High Voltage

2.0

- V

+0.5 V

Output Low Voltage

= 2.1 mA

0.45

Output High Voltage V

= -0.4 mA

2.4

W49F002U

Publication Release Date: February 21, 2002

- 15 - Revision A6

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

100

Power-up to Write Operation

. WRITE

CAPACITANCE

= 5.0V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

CONDITIONS

MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0V to 3V

Input Rise/Fall Time

<5 nS

Input/Output Timing Level

1.5V / 1.5V

Output Load

1 TTL Gate and C

= 30pF (for 70 nS/ 90 nS), 100 pF (for 120 nS)

AC Test Load and Waveform

+5V

1.8K

1.3K

OUT

30 pF for 70nS / 90nS

(Including Jig and Scope)

Input

Test Point

1.5V

Output

100 pF for 120nS

W49F002U

- 16 -

AC Characteristics, continued

Read Cycle Timing Parameters

= 5.0V

10%, V

= 0V, T

= 0 to 70

PARAMETER

SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

120

Chip Enable Access Time

120

Address Access Time

120

Output Enable Access Time

#CE Low to Active Output

CLZ

#OE Low to Active Output

OLZ

#CE High to High-Z Output

CHZ

#OE High to High-Z Output

OHZ

Output Hold from Address Change

Write Cycle Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Address Setup Time

Address Hold Time

#WE and #CE Setup Time

#WE and #CE Hold Time

#OE High Setup Time

OES

#OE High Hold Time

OEH

#CE Pulse Width

100

#WE Pulse Width

100

#WE High Width

WPH

100

Data Setup Time

Data Hold Time

Byte Programming Time

Erase Cycle Time

0.1

0.2

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is V

and (b) low level signal's reference level is V

W49F002U

Publication Release Date: February 21, 2002

- 17 - Revision A6

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYM. W49F002U-70 W49F002U-90 W49F002U-120 UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

#OE to Data Polling Output Delay T

OEP

#CE to Data Polling Output Delay

CEP

120

#OE to Toggle Bit Output Delay

OET

#CE to Toggle Bit Output Delay

CET

120

Reset Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

stable to Reset Active

PRST

Reset Pulse Width

RSTP

500

Reset Active to Output Float

RSTF

Reset Inactive to Input Active

RST

W49F002U

Publication Release Date: February 21, 2002

- 23 - Revision A6

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER

SUPPLY

CURRENT

MAX. (mA)

STANDBY

CURRENT

MAX. (

PACKAGE

CYCLE

HARDWARE

SID READ

FUNCTION

W49F002U-70B

100 (CMOS) 32-pin DIP

10K

W49F002U-90B

100 (CMOS) 32-pin DIP

10K

W49F002U-12B

120

100 (CMOS) 32-pin DIP

10K

W49F002UT70B

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UT90B

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UT12B

120

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UP70B

100 (CMOS) 32-pin PLCC

10K

W49F002UP90B

100 (CMOS) 32-pin PLCC

10K

W49F002UP12B

120

100 (CMOS) 32-pin PLCC

10K

W49F002UQ70B

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

W49F002UQ90B

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

W49F002UQ12B

120

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

W49F002U70BN

100 (CMOS) 32-pin DIP

10K

W49F002U90BN

100 (CMOS) 32-pin DIP

10K

W49F002U12BN

120

100 (CMOS) 32-pin DIP

10K

W49F002UT70N

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UT90N

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UT12N

120

100 (CMOS) 32-pin TSOP (8 mm

20 mm)

10K

W49F002UP70N

100 (CMOS) 32-pin PLCC

10K

W49F002UP90N

100 (CMOS) 32-pin PLCC

10K

W49F002UP12N

120

100 (CMOS) 32-pin PLCC

10K

W49F002UQ70N

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

W49F002UQ90N

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

W49F002UQ12N

120

100 (CMOS) 32-pin STSOP (8 mm

14 mm) 10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

3. Winbond offers Top Boot Block device, if any of Bottom Boot Block devices is required, please contact Winbond FAEs.

4. In Hardware SID read function column: Y = with SID read function; N = without SID read function.

W49F002U

Publication Release Date: February 21, 2002

- 25 - Revision A6

PACKAGE DIMENSIONS

32-pin P-DIP

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

6.General appearance spec. should be based on

final visual inspection spec.

1.37

1.22

0.054

0.048

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

c
D

A
A

0.050

1.27

0.210

5.33

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.41

0.25

3.94

0.46

4.06

0.56

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.20

3.05

0.25

3.30

0.36

3.56

0.555

0.550

0.545

14.10

13.97

13.84

17.02

15.24

14.99

15.49

0.600

0.590

0.610

2.29

2.54

2.79

0.090

0.100

0.110

1.650

1.660

41.91

42.16

0.085

2.16

0.650

0.630

16.00

16.51

protrusion/intrusion.

4.Dimension B1 does not include dambar

5.Controlling dimension: Inches

Seating Plane

Base Plane

32-pin PLCC

Notes:

D H

Seating Plane

1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches

4. General appearance spec. should be based on final
visual inspection sepc.

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in Inches

Dimension in mm

b
c
D

A
A

3.56

0.50

2.80

2.67

2.93

0.71

0.66

0.81

0.41

0.46

0.56

0.20

0.25

0.35

13.89

13.97

14.05

11.35

11.43

11.51

1.27

12.45

12.9
5

13.46

9.91

10.41

10.92

14.86

14.99

15.11

12.32

12.45

12.57

1.91

2.29

0.004

0.095

0.090

0.075

0.495

0.49
0

0.485

0.595

0.590

0.585

0.430

0.410

0.390

0.530

0.51
0

0.490

0.050

0.453

0.450

0.447

0.553

0.550

0.547

0.014

0.010

0.008

0.022

0.018

0.016

0.032

0.026

0.028

0.115

0.105

0.110

0.020

0.140

1.12

1.42

0.044

0.056

0.10

2.41

W49F002U

- 26 -

Package Dimensions, continued

32-pin STSOP (8 x 14 mm)

Min.

Dimension in Inches

Nom. Max.

Min.

Nom. Max.

Symbol

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.10

0.50

0.00

0.22

0.27

-----

0.21

12.40

8.00

14.00

0.50

0.60

0.70

0.80

0.10

0.047

0.006

0.041

0.040

0.035

0.007

0.009

0.010

0.004

-----

0.008

0.488

0.315

0.551

0.020

0.024

0.028

0.031

0.000

0.004

0.002

A
A

b
c

D
E

Dimension in mm

A
A

£c

32-pin TSOP (8 x 20 mm)

0.10(0.004)

Min.

Nom.

Max.

Min.

Nom.

Max.

Symbol

Note:

Controlling dimension: Millimeters

Dimension in Inches

0.047

0.006

0.041

0.039

0.037

0.007

0.008

0.009

0.005

0.006

0.007

0.720

0.724

0.728

0.311

0.315

0.319

0.780

0.787

0.795

0.020

0.016

0.020

0.024

0.031

0.000

0.004

0.002

1.20

0.05

0.15

1.05

1.00

0.95

0.17

0.12

18.30

7.90

19.80

0.40

0.00

0.20

0.23

0.15

0.17

18.40

18.50

8.00

8.10

20.00

20.20

0.50

0.60

0.80

0.10

Dimension in mm

W49F002U

Publication Release Date: February 21, 2002

- 27 - Revision A6

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

Nov. 1999

Renamed from W49F002/B/U/N

Apr. 2000

1, 13

15, 20 Add the 120 nS bin

Change Tbp(typ.) from 10

S to 35

Change Tec (max.) from 1 Sec to 0.2 Sec

Dec. 2000

All

Modify some function description

3, 9, 25

Add in Hardware SID read note

1, 25, 27

Add in 32-pin TSOP (8 mm x 14 mm) package

Jan. 2001

All

Typo correction

Aug. 13, 2001

16,22

Add Reset Timing Parameters and Diagram

Feb. 21, 2002

1, 25, 28

Rename STOP (8 x 14 mm) as STSOP (8 x 14 mm)

Modify Low V

Write Inhibit description

Add in Software Product Identification and Boot
Block Lockout Detection Acquisition Flow

Add in Boot Block Lockout Enable Acquisition Flow

Add HOW TO READ THE TOP MARKING

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

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