Preliminary W49F020

256K

8 CMOS FLASH MEMORY

Publication Release Date: October 1999

- 1 - Revision A1

GENERAL DESCRIPTION

The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K

8 bits. The device

can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

is not

required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The

device can also be programmed and erased using standard EPROM programmers.

FEATURES

Single 5-volt operations:

5-volt Read

5-volt Erase

5-volt Program

Fast Program operation:

Byte-by-Byte programming: 50

S (max.)

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 70/90 nS

Endurance: 1K/10K cycles (typ.)

Twenty-year data retention

Hardware data protection

One 8K byte Boot Block with Lockout

protection

Low power consumption

Active current: 25 mA (typ.)

Standby current: 20

A (typ.)

Automatic program and erase timing with

internal V

generation

End of program or erase detection

Toggle bit

Data polling

Latched address and data

TTL compatible I/O

JEDEC standard byte-wide pinouts

Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

Preliminary W49F020

- 2 -

PIN CONFIGURATIONS

DQ0

DQ1

DQ2

GND

A16

A15

A12

A14

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A17

32-pin

DIP

DQ0

D
Q
1

D
Q
2

G
N
D

D
Q

D
Q
4

D
Q
5

D
Q

A14

A13

A11

OE
A10

DQ7

1
2

A
1
6

V
D
D

1
5

32-pin
PLCC

1
7

N
C

DQ0

DQ1

DQ2

GND

A10

CE
DQ7
DQ6

DQ5
DQ4
DQ3

32-pin
TSOP

A15

A12

A7
A6
A5

A14

A13

A11

A16

A17

BLOCK DIAGRAM

CONTROL

OUTPUT

BUFFER

DECODER

A17

DQ0

VDD

VSS

DQ7

02000
01FFF

00000

MAIM MEMORY

248K BYTES

BOOT BLOCK

8K BYTES

3FFFF

W49F020

PIN DESCRIPTION

SYMBOL

PIN NAME

A17

Address Inputs

DQ0

DQ7

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Power Supply

GND

Ground

No Connection

Preliminary W49F020

Publication Release Date: October 1999

- 3 - Revision A1

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F020 is controlled by CE and OE , both of which have to be low for the

host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is

de-selected and only standby power will be consumed. OE is the output control and is used to gate data

from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the
timing waveforms for further details.

Boot Block Operation

There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block
locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the
specific code, please see Command Codes for Boot Block Lockout Enable.

When the boot block is enabled, data for the designated block cannot be erased or programmed
(programming lockout); other memory locations can be changed by the regular programming method.
When the boot block programming lockout feature is activated, the chip erase function cannot erase the
boot block any longer.

In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform
software command sequence to check it. First, enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the
output data is "0," the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
in a fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the main memory blocks
will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the
chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function erase the main memory block but not the boot block. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.

Program Operation

The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data
"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot
block from "0" to "1") is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50

S max. -

Preliminary W49F020

- 4 -

) when completing programming and return to normal read mode. Data polling and/or Toggle Bits

can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F020 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation is inhibited when V

is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ

of the

last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and

become logical "1" or true data when the erase cycle has been completed.

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will produce

alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).

In the hardware access mode, access to the product ID will be activated by forcing CE and OE low,

high, and raising A9 to 12 volts.

Preliminary W49F020

Publication Release Date: October 1999

- 5 - Revision A1

TABLE OF OPERATING MODES

Operating Mode Selection

= 12V

)

MODE

PINS

ADDRESS

DQ.

Read

Dout

Write

Din

Standby

High Z

Write Inhibit

High Z/D

OUT

High Z/D

OUT

Output Disable

High Z

Product ID

A0 = V

; A1

A17 = V

;

A9 = V

Manufacturer Code DA (Hex)

A0 = V

; A1

A17 = V

;

A9 = V

Device Code 8C (Hex)

TABLE OF COMMAND DEFINITION

COMMAND

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles Addr. Data Addr. Data Addr. Data

Addr. Data

Read

OUT

Chip Erase

5555 AA 2AAA 55 5555 80

5555 AA 2AAA 55 5555 10

Byte Program

5555 AA 2AAA 55 5555 A0

Boot Block Lockout

5555 AA 2AAA 55 5555 80

5555 AA 2AAA 55 5555 40

Product ID Entry

5555 AA 2AAA 55 5555 90

Product ID Exit

(1)

5555 AA 2AAA 55 5555 F0

Product ID Exit

(1)

XXXX F0

Notes:

1. Address Format: A14

A0 (Hex); Data Format: DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

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