Preliminary W49L201

128K

16 CMOS FLASH MEMORY

Publication Release Date: May 2000

- 1 - Revision A1

GENERAL DESCRIPTION

The W49L201 is a 2-megabit, 3.3-volt only CMOS flash memory organized as 128K

16 bits. The

device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V

not required. The unique cell architecture of the W49L201 results in fast program/erase operations

with extremely low current consumption (compared to other comparable 3.3-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

Single 3.3-volt operations:

3.3-volt Read/Erase/Program

Fast Program operation:

Word-by-Word programming: 50

S (max.)

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 70/90 nS

Endurance: 10K cycles (typ.)

Ten-year data retention

Hardware data protection

Sector configuration

One 8K words Boot Block with lockout

protection

Two 8K words Parameter Blocks

One 104K words (208K bytes) Main Memory

Array Blocks

Low power consumption

Active current: 15 mA (typ.)

Standby current: 10

A (typ.)

Automatic program and erase timing with

internal V

generation

End of program or erase detection

Toggle bit

Data polling

Latched address and data

TTL compatible I/O

JEDEC standard word-wide pinouts

Available packages: 44-pin SOP, 48-pin TSOP

Preliminary W49L201

- 2 -

PIN CONFIGURATIONS

DQ15

A10

A11

A12

A13

A14

A15

GND

48-pin

TSOP

A16

A7
A6
A5
A4
A3
A2
A1

47
7

RESET

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

GND

DQ15

GND

44-pin

SOP

24
23

A16

A7
A6
A5
A4
A3
A2
A1

A10
A11
A12

A13
A14
A15

RESET

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

DQ7
DQ14
DQ6

DQ13
DQ5

DQ12

DQ4

GND

BLOCK DIAGRAM

CONTROL

OUTPUT

BUFFER

DECODER

MAIN MEMORY

104K WORDS

A16

DQ0

DQ15

BOOT BLOCK

8K WORDS

PARAMETER

BLOCK2

8K WORDS
PARAMETER

BLOCK1

8K WORDS

1FFFF

06000
05FFF

04000
03FFF

02000
01FFF

00000

RESET

PIN DESCRIPTION

SYMBOL

PIN NAME

RESET

Reset

A16

Address Inputs

DQ0

DQ15

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

Power Supply

GND

Ground

No Connection

Preliminary W49L201

Publication Release Date: May 2000

- 3 - Revision A1

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49L201 is controlled by CE and OE, both of which have to be low for the

host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is

de-selected and only standby power will be consumed. OE is the output control and is used to gate

data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer
to the timing waveforms for further details.

Reset Operation

The RESET

input pin can be used in some application. When RESET pin is at high state, the device

is in normal operation mode. When RESET pin is driven low for at least a period of T

, it will halts

the device and all outputs are at high impedance state. The device also resets the internal state
machine to read array data. The operation that was interrupted should be reinitiated once the device
is ready to accept another command sequence to assure data integrity. As the high state re-asserted

to the RESET pin, the device will return to read or standby mode, it depends on the control signals.

The system can read data T

after the RESET

pin returns to V

. The other function for RESET pin

is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be
reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method.

There is one condition that the lockout feature can be overrides. Just apply 12V to RESET

pin, the

lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once

the RESET pin returns to TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002
hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the
output data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing

Preliminary W49L201

- 4 -

during this operation. The entire memory array will be erased to FF(hex) by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will erase all the sectors except the boot mode.

Sector Erase Operation

The three sectors, main memory and two parameters blocks, can be erased individually by initiating a
six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle
while the 30(hex) data input command is latched at the rising edge of WE. After the command
loading cycle, the device enters the internal sector erase mode, which is automatically timed and will
be completed in a fast 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

When the boot block lockout feature is inactivated, the boot block and the main memory block will be
erased together. Once the boot block is locked, only the main memory block will be erased by the
execution of sector erase operation.

Program Operation

The W49L201 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50

S max. -

) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to

detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49L201 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation is inhibited when V

is less than

1.8V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49L201 includes a data polling feature to indicate the end of a program or erase cycle. When
the W49L201 is in the internal program or erase cycle, any attempt to read DQ

of the last word

loaded will receive the complement of the true data. Once the program or erase cycle is completed,
DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and become

logical "1" or true data when the erase cycle has been completed.

Preliminary W49L201

Publication Release Date: May 2000

- 5 - Revision A1

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W49L201 provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from
address 0001(hex) outputs the device code, 003E(hex). The product ID operation can be terminated
by a three-word command sequence or an alternative one-word command sequence (see Command
Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE
high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

= 12V

0.5V)

MODE

PINS

RESET

ADDRESS

DQ.

Read

Dout

Erase/Program

Din

Standby

High Z

Erase/Program

High Z/D

OUT

Inhibit

High Z/D

OUT

Output Disable

High Z

Product ID

A0 = V

;

A9 = V

;

Other Add = V

Manufacturer Code
00DA (Hex)

A0 = V

;

A9 = V

HH;

Other Add = V

;

Device Code
003E (Hex)

Reset

High Z

Preliminary W49L201

- 6 -

TABLE OF COMMAND DEFINITION

COMMAND

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

DESCRIPTION

Cycles Addr. Data Addr. Data

Addr. Data

Read

OUT

Chip Erase

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

Sector Erase

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA

(3)

Word Program

5555 AA 2AAA 55 5555 A0 A

Boot Block Lockout

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

Product ID Entry

5555 AA 2AAA 55 5555 90

Product ID Exit

(1)

5555 AA 2AAA 55 5555 F0

Product ID Exit

(1)

XXXX F0

Notes:

1. Address Format: A14

A0 (Hex); Data Format: DQ15

DQ8 (Don't Care); DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA: Sector Address, A16 - A12 address bits will select available sectors.

A16 - A12 = 00011, for 8Kword Parameter Block1

A16 - A12 = 00101, for 8Kword Parameter Block2

A16 - A12 = 11111,

- for 104Kword Main Memory Block when Boot Block lockout feature is activated.

- for 104Kword Main Memory Block and 8Kword Boot Block when Boot Block lockout feature is inactivated.

Preliminary W49L201

Publication Release Date: May 2000

- 7 - Revision A1

Command Codes for Word Program

WORD SEQUENCE

ADDRESS

DATA

0 Write

5555H

AAH

1 Write

2AAAH

55H

2 Write

5555H

A0H

3 Write

Programmed-address

Programmed-data

Pause T

Word Program Flow Chart

Word Program
Command Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data A0

address 5555

Load data Din

programmed-

address

Exit

Pause T

Notes for software program code:

Data Format: DQ15

DQ8: Don't Care; DQ7-DQ0 (Hex)

Address Format: A14

A0 (Hex)

*It is not allowed to assert read command during the 4-word command sequence (program).

To assert the read command during the 4-word command sequence will abort programming procedure.

Preliminary W49L201

Publication Release Date: May 2000

- 9 - Revision A1

Command Codes for Sector Erase

BYTE SEQUENCE

ADDRESS

DATA

1 Write

5555H

AAH

2 Write

2AAAH

55H

3 Write

5555H

80H

4 Write

5555H

AAH

5 Write

2AAAH

55H

6 Write

SA*

30H

Pause T

Sector Erase Acquisition Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 30

address SA*

Exit

Pause T

Notes for chip erase:

Data Format: DQ15-DQ8: Don't Care; DQ7

DQ0 (Hex)

Address Format: A14

A0 (Hex)

A16 - A12 = 00011, for 8Kword Parameter Block1 (Sector-1)
A16 - A12 = 00101, for 8Kword Parameter Block2 (Sector-2)
A16 - A12 = 11111,

- for 104Kword Main Memory Block when Boot Block lockout feature is activated.
- for 104Kword Main Memory Block and 8Kword Boot Block when Boot Block lockout feature is inactivated.

Preliminary W49L201

- 10 -

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (6)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK LOCKOUT

DETECTION EXIT

ADDRESS

DATA

ADDRESS

DATA

1 Write

5555

5555H

AAH

2 Write

2AAA

2AAAH

55H

3 Write

5555

5555H

F0H

Pause 10

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Load data 55

address 2AAA

Load data 90

address 5555

Pause 10 S

Product

Identification
and Boot Block
Lockout Detection
Mode (3)

Read address = 0000

data = 00DA

Read address = 0001

data = 003E

Read address = 0002

data in DQ0 =1/0

(4)

Product

Identification Exit(6)

Load data 55

address 2AAA

Load data F0

address 5555

Normal Mode

(5)

(2)

Load data AA

address 5555

Load data AA

address 5555

Pause 10 S

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ15-DQ8 (Don't Care), DQ7

DQ0 (Hex); Address Format: A14

A0 (Hex)

(2) A1

A16 = V

; manufacture code is read for A0 = V

; device code is read for A0 = V

(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is
inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.

Preliminary W49L201

Publication Release Date: May 2000

- 11 - Revision A1

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

BOOT BLOCK LOCKOUT FEATURE SET

ADDRESS

DATA

1 Write

5555H

AAH

2 Write

2AAAH

55H

3 Write

5555H

80H

4 Write

5555H

AAH

5 Write

2AAAH

55H

6 Write

5555H

40H

Pause T

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA

address 5555

Load data 55

address 2AAA

Load data 80

address 5555

Load data AA

address 5555

Load data 55

address 2AAA

Load data 40

address 5555

Exit

Pause T

Notes for boot block lockout enable:
Data Format: DQ15-DQ8 Don't Care), DQ7

DQ0 (Hex)

Address Format: A14

A0 (Hex)

Preliminary W49L201

Publication Release Date: April 2000

- 12 - Revision A1

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

Power Supply Voltage to V

Potential

-0.5 to +4.6

Operating Temperature

0 to +70

Storage Temperature

-65 to +150

D.C. Voltage on Any Pin to Ground Potential except A9

-0.5 to V

+1.0

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

-1.0 to V

+1.0

Voltage on A9 Pin to Ground Potential

-0.5 to 12.5

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Operating Characteristics

= 3.3V

, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN. TYP.

MAX.

Power Supply
Current

CE=OE= V

, WE= V

, all DQs open

Address inputs = V

, at f = 5 MHz

Standby V

Current (TTL input)

CE = V

, all DQs open

Other inputs = V

Standby V

Current

(CMOS input)

2 CE = V

-0.3V, all DQs open

Other inputs = V

-0.3V/GND

Input Leakage
Current

= GND to V

Output Leakage
Current

OUT

= GND to V

Input Low Voltage

-0.3

0.6

Input High Voltage

2.0

+0.5

Output Low Voltage

= 2.1 mA

0.45

Output High Voltage V

= -0.4 mA

2.4

W49L201

Publication Release Date: May 2000

- 13 - Revision A1

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

Power-up to Read Operation

. READ

200

Power-up to Write Operation

. WRITE

CAPACITANCE

= 3.3V, T

= 25

C, f = 1 MHz)

PARAMETER

SYMBOL

CONDITIONS

MAX.

UNIT

I/O Pin Capacitance

I/O

= 0V

Input Capacitance

= 0V

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0.4V to 2.4V

Input Rise/Fall Time

< 5 nS

Input/Output Timing Level

1.5V/1.5V

Output Load

1 TTL Gate and C

= 30 pF for 70 nS

= 100 pF for 90 nS

AC Test Load and Waveform

+3.3V

1.8K

1.3K

OUT

30 pF for 70 nS

(Including Jig and Scope)

Input

2.4V

0.4V

Test Point

1.5V

Output

100 pF for 90 nS

Preliminary W49L201

- 14 -

AC Characteristics, continued

Read Cycle Timing Parameters

= 3.3V

, V

= 0V, T

= 0 to 70

PARAMETER

SYM.

W49L201-70

W49L201-90

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

Chip Enable Access Time

Address Access Time

Output Enable Access Time

Low to Active Output

CLZ

Low to Active Output

OLZ

High to High-Z Output

CHZ

High to High-Z Output

OHZ

Output Hold from Address Change

Note: The parameter of T

CLZ

, T

OLZ

, T

CHZ

, T

OHZ

are characterized only and is not 100% tested.

Write Cycle Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Address Setup Time

Address Hold Time

and

Setup Time

and

Hold Time

High Setup Time

OES

High Hold Time

OEH

Pulse Width

High Width

WPH

100

Data Setup Time

Data Hold Time

Word programming Time

Erase Cycle Time

100

200

Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is V

and (b) low level signal's reference level is V

W49L201

Publication Release Date: May 2000

- 15 - Revision A1

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYM.

W49L201-70

W49L201-90

UNIT

MIN.

MAX.

MIN.

MAX.

OE to Data Polling Output Delay

OEP

CE to Data Polling Output Delay

CEP

WE High to OE Low for Data Polling

OEHP

100

OE to Toggle Bit Output Delay

OET

CE to Toggle Bit Output Delay

CET

WE High to OE Low for Toggle Bit

OEHT

100

Hardware Reset Timing Parameters

PARAMETER

SYM.

MIN.

MAX.

UNIT

RESET Pulse Width

500

RESET High Time Before Read(1)

Note: 1. The parameters are characterized only and is not 100% tested.

W49L201

Publication Release Date: May 2000

- 17 - Revision A1

Timing Waveforms, continued

Controlled Command Write Cycle Timing Diagram

High Z

Data Valid

DQ15-0

CPH

OEH

OES

Address A16-0

Program Cycle Timing Diagram

Address A16-0

Word 0

Word 1

Word 2

Internal Write Start

DQ15-0

Word Program Cycle

WPH

5555

2AAA

Address

Data-In

Word 3

*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the
command sequence. If read command is asserted during the command
sequence, then the device will return to read mode(abort write).

W49L201

Publication Release Date: May 2000

- 19 - Revision A1

Timing Waveforms, continued

Boot Block Lockout Enable Timing Diagram

SW23

SW1

SW0

Address A16-0

DQ15-0

SW3

SW4

SW5

Six-word code for Boot Block
Lockout Feature Enable

WPH

5555

2AAA

5555

2AAA

5555

XXAA

XX55

XX80

XXAA

XX55

XX40

Chip Erase Timing Diagram

SW2

SW1

SW0

Address A16-0

DQ15-0

SW3

SW4

SW5

Internal Erase starts

Six-word code for 3.3V-only software
chip erase

WPH

5555

2AAA

5555

2AAA

5555

XXAA

XX55

XX80

XXAA

XX55

XX10

W49L201

Publication Release Date: May 2000

- 21 - Revision A1

ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

POWER

SUPPLY

CURRENT

MAX. (mA)

STANDBY

CURRENT
MAX. (

PACKAGE

CYCLE

W49L201S-70

50 (CMOS) 44-pin SOP

10K

W49L201S-90

50 (CMOS) 44-pin SOP

10K

W49L201T-70

50 (CMOS) 48-pin TSOP (12 mm

20 mm)

10K

W49L201T-90

50 (CMOS) 48-pin TSOP (12 mm

20 mm)

10K

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

Preliminary W49L201

- 22 -

PACKAGE DIMENSIONS
48-pin TSOP (12 mm

20 mm)

0.020

0.004

0.007

0.037

0.002

MIN.

0.60

0.50

0.10

0.70

0.21

Dimension in mm

0.95

0.17

0.05

Symbol

MIN.

1.20

0.27

1.05

1.00

0.22

MAX.

NOM.

0.028

0.008

0.024

0.011

0.041

0.047

0.009

0.039

NOM.

Dimension in Inches

MAX.

18.3

18.4

18.5

19.8

20.0

20.2

11.9

12.0

12.1

0.720 0.724

0.728

0.780 0.787

0.795

0.468 0.472

0.476

0.10

0.80

0.031

0.004

0.020

0.50

44-pin SOP

SEATING PLANE

0.089

0.004

0.516

0.622

16.00

15.80

16.20

13.30

28.07

13.10

2.26

13.50

28.32

28.19

3.00

2.82

0.638

0.630

0.111

0.118

0.531

1.105

1.115

1.110

0.524

MIN.

Dimension in Inches

Symbol

Dimension in mm

MIN.

NOM.

MAX.

NOM.

0.10

0.014

0.020

0.016

0.004

0.008

0.006

0.024

0.040

0.032

0.053

0.004

0.36

0.50

0.41

0.10

0.21

0.15

1.12

1.42

1.27

0.044

0.056

0.050

0.60

1.00

0.80

1.35

0.10

W49L201

Publication Release Date: May 2000

- 23 - Revision A1

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

May 2000

Initial Issued

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change withou t notice.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change withou t notice.

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