W49L401(T)

256K

16 CMOS FLASH MEMORY

Publication Release Date: August 16, 2002

- 1 - Revision A4

1. GENERAL DESCRIPTION

The W49L401(T) is a 4-megabit, 3.3-volt only CMOS flash memory organized as 256K

16 bits. The

device can be programmed and erased in-system with a standard 3.3-volt power supply. A 12-volt V

is not required. The unique cell architecture of the W49L401(T) results in fast program/erase

operations with extremely low current consumption (compared to other comparable 3.3-volt flash

memory products). The device can also be programmed and erased using standard EPROM

programmers.

2. FEATURES

Single Voltage operations:

3.0

3.6V Read/Erase/Program

Fast Program operation:

Word-by-Word programming: 30

S (typ.)

Fast Erase operation:

Page/Block Erase time: 50 mS (typ.)

Chip Erase time: 200 mS (typ.)

Fast Read access time: 70 nS

Endurance: 10K cycles (typ.)

Twenty-year data retention

Hardware data protection

Block configuration

One 8K-word boot block with lockout

protection

Two 4K-word parameter blocks

One 16K-word main memory array block

Seven 32K-word main memory array blocks

128 uniform 2K-word pages

Optional Uniform Page configuration

Low power consumption

Active current: 10 mA (typ.)

Standby current: 5

A (typ.)

Automatic program and erase timing with

internal V

generation

End of program or erase detection

Toggle bit

Data polling

RY/#BY open-drain output provides hardware

end-of-write detection

Hardware #RESET pin

Latched address and data

TTL compatible I/O

JEDEC standard word-wide pinouts

Available packages: 44-pin SOP, 48-pin TSOP

W49L401(T)

- 2 -

3. PIN CONFIGURATIONS

DQ15

A10

A11

A12

A13

A14

A15

#OE

48-pin

TSOP

A16

#WE

#CE

A7
A6
A5
A4
A3
A2
A1

#RESET

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

DQ7
DQ14
DQ6

DQ13
DQ5
DQ12
DQ4

DQ15

#OE

44-pin

SOP

24
23

A16

#CE

A6
A5
A4
A3
A2
A1

A10
A11
A12

A13
A14

A15

#WE

#RESET

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

DQ7
DQ14
DQ6

DQ13
DQ5
DQ12

DQ4

A17

RY/#BY

4. BLOCK DIAGRAM

CONTROL

OUTPUT
BUFFER

D
E
C
O
D
E
R

#CE

#OE

#WE

A17

DQ0

DQ15

#RESET

BOOT BLOCK
8K WORDS

PARAMETER
BLOCK2
4K WORDS

PARAMETER
BLOCK1
4K WORDS

3FFFF

04000
03FFF

03000
02FFF

02000
01FFF

00000

W49L401

MAIN MEMORY
240K WORDS

BOOT BLOCK
8K WORDS

PARAMETER
BLOCK2
4K WORDS

PARAMETER
BLOCK1
4K WORDS

3FFFF

3E000
3DFFF

3D000
3CFFF

3C000
3BFFF

00000

W49L401T

RY/#BY

(1x16K WORDS

7x32K WORDS)

MAIN MEMORY
240K WORDS

(1x16K WORDS

7x32K WORDS)

5. PIN DESCRIPTION

SYMBOL

PIN NAME

#RESET

Reset

RY/#BY

Ready/#Busy Output

A17

Address Inputs

DQ0

DQ15 Data Inputs/Outputs

#CE

Chip Enable

#OE

Output Enable

#WE

Write Enable

Power Supply

Ground

No Connection

W49L401(T)

Publication Release Date: August 16, 2002

- 3 - Revision A4

6. FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49L401(T) is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data to the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer
to the timing waveforms for further details.

Reset Operation

The #RESET

input pin can be used in some application. When #RESET pin is at high state, the device

is in normal operation mode. When #RESET pin is driven low for at least a period of T

, it will halt the

device and all outputs are at high impedance state. The device also resets the internal state machine
to read array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence to assure data integrity. As the high state re-asserted to the
#RESET pin, the device will return to read or standby mode, it depends on the control signals. The
system can read data T

after the #RESET

pin returns to V

. The other function for #RESET pin is

temporary reset the boot block. By applying the 12V to #RESET

pin, the boot block can be

reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words (for W49L401T, located in the last 8K words) of the memory with the address range
from 0000(hex) to 1FFF(hex). (for W49L401T, address range from 3E000h to 3FFFFh)

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the
data for the designated block cannot be erased or programmed (programming lockout); the regular
programming method can change the data in other memory locations.

There is one condition that the lockout feature can be over-ridden. Just apply 12V to #RESET

pin, the

lockout feature will temporarily be inactivated and the boot block can be erased/programmed. Once the
#RESET

pin returns to CMOS/TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex".
If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output
data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 200 mS (typical). The host system is not required to provide any control or timing
during this operation. The entire memory array will be erased to FFFF(hex) by the chip erase operation
if the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will erase all the blocks/pages except the boot block.

W49L401(T)

- 4 -

Block/Page Erase Operation

The W49L401(T) provides both uniform small page (2K-word) and non-symmetrical block
(4K/8K/16K/32K-word) erase capabilities for versatile Flash applications.

Each block or page can be erased individually by initiating a six-word command sequence. The block
address (BA) or page address (PA) is latched on the falling #WE edge of the sixth cycle while the
XX30/XX50(hex) data input command is latched at the rising edge of #WE. After the command loading
cycle, the device enters the internal block/page erase mode, which is automatically timed and will be
completed in a fast 50 mS (typical). The host system is not required to provide any control or timing
during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data-polling, Toggle-Bit and/or RY/#BY pin can be used to detect end of erase
cycle.

The bootblock (8K-words) consists of 4 corresponding uniform pages of 2K-words each. When the
boot block lockout feature is activated, any page/block erase command with the associated PA/BA
within the bootblock address range (0000-01FFF for W49L401, and 3E000-3FFFF for W49L401T) will
be ignored and the device will return to read mode without any data changes.

Program Operation

The W49L401(T) is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in individual page/block or whole
chip from "0" to "1") is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50

S max. -

) once completed and return to normal read mode. Data_polling, Toggle_Bit and/or RY/#BY pin

can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49L401(T) is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A #WE pulse of less than 10 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation and read are inhibited when V

less than 1.8V typical.

(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

10 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49L401(T) includes a data polling feature to indicate the end of a program or erase cycle.
When the W49L401(T) is in the internal program or erase cycle, any attempt to read DQ

of the last

word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ

will show the true data. Note that, DQ

will show logical "0" during the erase cycle.

And it will become logical "1" or true data when the erase cycle is completed.

Toggle Bit (DQ

)- Write Status Detection

In addition to data polling, the W49L401(T) provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ

will

W49L401(T)

Publication Release Date: August 16, 2002

- 5 - Revision A4

produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

Ready/#Busy

The W49L401(T) also provides the hardware method to detect the completion of program/erase cycle .
The RY/#BY

output pin will be asserted low (busy) during programming/erasing operations, and will be

released to high state by an external pull-up (ready) when internal program/erase cycle is completed.
This is an open-drain output pin for easy external connection.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from
address 0001(hex) outputs the device code, 003D(hex) for bottom boot (and TBD for top boot). The
product ID operation can be terminated by a three-word command sequence or an alternative one-
word command sequence (see Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to V

(12V

0.5V).

Table of Operating Modes

Operating Mode Selection

= 12V

0.5V)

PINS

MODE

#CE #OE #WE #RESET

ADDRESS

DQ.

Read

Dout

Erase/Program

Din

Standby

High Z

High Z/D

OUT

Erase/Program

Inhibit

High Z/D

OUT

Output Disable

High Z

A0 = V

;

A15 = V

;

A9 = V

Manufacturer Code

00DA (Hex)

Product ID

A0 = V

;

A15 = V

;

A9 = V

Device Code
003D (Hex) for bottom

TBD for Top

Reset

High Z

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