Preliminary W49V002A
256K x 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
Publication Release Date: April 2001
- 1 -
Revision A1
GENERAL DESCRIPTION
The W49V002A is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K
8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V
PP
is
not required. The unique cell architecture of the W49V002A results in fast program/erase operations with
extremely low current consumption. This device can operate at two modes, Programmer bus interface
mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional
flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the
Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM
programmers.
FEATURES
Single 3.3-volt operations:
-
3.3-volt Read
-
3.3-volt Erase
-
3.3-volt Program
Fast Program operation:
-
Byte-by-Byte programming: 50
S (typ.)
Fast Erase operation: 150 mS (typ.)
Endurance: 10K cycles (typ.)
Twenty-year data retention
Hardware data protection
-
#TBL & #WP serve as hardware protection
One 16K bytes Boot Block with lockout
protection
Two 8K bytes Parameter Blocks
Four Main Memory Blocks (with 32K bytes, 64K
bytes, 64K bytes, 64K bytes each)
Low power consumption
-
Active current: 25 mA (typ.)
-
Standby current: 20
A (typ.)
Automatic program and erase timing with
internal V
PP
generation
End of program or erase detection
-
Toggle bit
-
Data polling
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC and 32L
STSOP
Preliminary W49V002A
- 2 -
PIN CONFIGURATIONS
5
6
7
9
10
11
12
13
29
28
27
26
25
24
23
22
21
30
31
32
1
2
3
4
8
20
19
18
17
16
15
14
D
Q
1
^
L
A
D
1
v
G
N
D
D
Q
6
^
R
S
V
v
#
R
E
S
E
T
V
D
D
R
#
C
^
C
L
K
v
A
9
^
G
P
I
3
v
32-pin
PLCC
A
1
0
^
G
P
I
4
v
N
C
DQ0(LAD0)
A7(GPI1)
A6(GPI0)
A4(#TBL)
A3(RSV)
A2(RSV)
A1(RSV)
A0(RSV)
A5(#WP)
MODE
VDD
DQ7(RSV)
#WE(#LFRAM)
#OE(#INIT)
GND
NC
NC
A
8
^
G
P
I
2
v
D
Q
2
^
L
A
D
2
v
D
Q
3
^
L
A
D
3
v
D
Q
4
^
R
S
V
v
D
Q
5
^
R
S
V
v
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A9(GPI3)
#RESET
NC
A8(GPI2)
A7(GPI1)
A6(GPI0)
A4(#TBL)
A5(#WP)
V
DD
MODE
GND
NC
NC
A10(GPI4)
R/#C(CLK)
DQ0(LAD0)
A3(RSV)
A2(RSV)
A1(RSV)
A0(RSV)
DQ1(LAD1)
DQ2(LAD2)
GND
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
DQ3(LAD3)
DQ7(RSV)
#WE(#LFRAM)
#OE(#INIT)
NC
NC
BLOCK DIAGRAM
Program-
mer
Interface
3FFFF
00000
BOOT BLOCK
16K BYTES
MAIN MEMORY
BLOCK1
32K BYTES
20000
1FFFF
3C000
3BFFF
10000
0FFFF
PARAMETER
BLOCK1
8K BYTES
PARAMETER
BLOCK2
8K BYTES
3A000
39FFF
38000
37FFF
LPC
Interface
CLK
#LFRAM
MODE
#RESET
LAD[3:0]
A[10:0]
DQ[7:0]
#OE
#WE
R/#C
MAIN MEMORY
BLOCK2
64K BYTES
MAIN MEMORY
BLOCK3
64K BYTES
30000
2FFFF
MAIN MEMORY
BLOCK4
64K BYTES
#INIT
#TBL
#WP
PIN DESCRIPTION
SYMB
INTERFACE
PIN NAME
PGM
LPC
MODE
*
*
Interface Mode Selection
#RESET
*
*
Reset
#INIT
*
Initialize
#TBL
*
Top Boot Block Lock
#WP
*
Write Protect
CLK
*
CLK Input
GPI[4:0]
*
General Purpose
Inputs
LAD[3:0]
*
Address/Data Inputs
#LFRAM
*
LPC Cycle Initial
R/#C
*
Row/Column Select
A[10:0]
*
Address Inputs
DQ[7:0]
*
Data Inputs/Outputs
#OE
*
Output Enable
#WE
*
Write Enable
V
DD
*
*
Power Supply
GND
*
*
Ground
RSV
*
*
Reserve Pins
NC
*
*
No Connection
Preliminary W49V002A
Publication Release Date: April 2001
- 3 -
Revision A1
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC
interface mode. The MODE pin of the device provides the control between these two interface modes.
These interface modes need to be configured before power up or return from #RESET
.
When MODE pin
is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or
leaved no connection), it is in the LPC mode. In Programmer mode, this device just behaves like
traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go
through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification
Revision 1.0. Through LAD[3:0] to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE
TYPER+DIR".
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as
the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by
the chip erase operation if the boot block programming lockout feature is not activated. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle
Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal read
mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of
erase cycle.
Program Operation
The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data
Preliminary W49V002A
- 4 -
"1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-program
command is entered. The internal program timer will automatically time-out (100
S max. - T
BP
) once it
is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect
end of program cycle.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the other
is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can
be used to store boot codes. It is located in the last 16K bytes of the memory with the address range
from 3C000(hex) to 3FFFF(hex).
Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.
Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.
Hardware Data Protection
The integrity of the data stored in the W49V002A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming operation is inhibited when V
DD
is less than 1.5V
typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ
7
)- Write Status Detection
The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When
the W49V002A is in the internal program or erase cycle, any attempts to read DQ
7
of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ
7
will show the true data. Note that DQ
7
will show logical "0" during the erase cycle, and when erase cycle
has been completed it becomes logical "1" or true data.
Toggle Bit (DQ
6
)- Write Status Detection
In addition to data polling, the W49V002A provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will produce
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
Preliminary W49V002A
Publication Release Date: April 2001
- 5 -
Revision A1
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The ROM will respond to 256K byte pages
whenever the memory address rang is within the top 4M bytes and bottom 128K bytes.
The 32bit address space is as below:
Block
Address Range
4M Byte BIOS ROM
FFFF,FFFFh:FFC0,0000h
128K Byte BIOS ROM
000F,FFFFh:000E,0000h
Registers
FFBC,0100h
General Purpose Inputs Register
This register reads the GPI[4:0] pins on the W49V002A.This is a pass-through register which can read
via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
Bit
Function
7-5
Reserved
4
Read GPI4 pin status
3
Read GPI3 pin status
2
Read GPI2 pin status
1
Read GPI1 pin status
0
Read GPI0 pin status
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read
from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs
the device code, B0(hex)." The product ID operation can be terminated by a three-byte command
sequence or an alternate one-byte command sequence (see Command Definition table).
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