W536030P/060P/090P/120P
VOICE & MELODY CONTROLLER
(ViewTalk
TM
Series)
Publication Release Date: May 21, 2003
- 1 -
Revision A4
Table of Contents-
1.
GENERAL DESCRIPTION ......................................................................................................... 2
2.
FEATURES ................................................................................................................................. 3
3.
BLOCK DIAGRAM ...................................................................................................................... 5
4.
PAD DESCRIPTION ................................................................................................................... 6
5.
ELECTRICAL CHARACTERISTICS........................................................................................... 7
5.1
Absolute Maximum Ratings............................................................................................... 7
5.2
DC Characteristics............................................................................................................. 8
5.3
AC Characteristics............................................................................................................. 9
6.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 12
6.1
Sub Clock with RC Mode................................................................................................. 12
6.2
Sub Clock with Xtal Mode................................................................................................ 13
7.
REVISION HISTORY ................................................................................................................ 14
W536030P/060P/090P/120P
- 2 -
1. GENERAL DESCRIPTION
The W536XXXP, a member of ViewTalk
TM
family, is a high-performance 4-bit micro-controller (uC)
with built-in 8KW uC program. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit
timers, one 14 bits divider, maximum 32 pads for input or output, 8 interrupt sources and 8-level
nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum
128 seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable of expanding to 512
seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power
dissipation. It is ideal for educational toys, remote controllers and other application products which
incorporate both melody and speech.
BODY W536030P
W536060P
W536090P
W536120P
Voice
30 sec
60 sec
90 sec
120 sec
I/O pad
8I/O, 8I
(RA/RB/RC/RD)
8I/O, 8I
(RA/RB/RC/RD)
8I/O, 12I, 12O
(RA/RB/RC/RD/RE
/RF/RG/RH)
8I/O, 12I, 12O
(RA/RB/RC/RD/RE/
RF/RG/RH)
WDT disable/Enable
(Mask Option)
Y Y Y Y
Sub-clock
RC/XTAL mode
(Mask Option)
Y Y Y Y
Tri-state serial bus
(Mask Option)( 1)
Y Y Y Y
Cascaded Voice through
serial bus (2)
Y Y N Y
Notes:
1. Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get
minimum power consumption in general.
2. Cascaded Voice ROM user option help to expand voice up to 512 sec through serial bus by W55XXX chip.
W536030P/060P/090P/120P
Publication Release Date: May 21, 2003
- 3 -
Revision A4
2. FEATURES
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
- Main clock with Ring/Crystal (400 KHz to 4 MHz)
- Sub-clock with 32.768 KHz RC/Crystal by mask option
Memory
- Program ROM (P-ROM): 8 K 20 (ROM Bank0)
- Data RAM (W-RAM): 1K 4 bit
(RAM Bank 0 is 512 nibbles from 0: 000~0: 1FF and 0:380~0:3FF are mapped to special
register.
RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script
kernel)
Maximum 32 input/output pads
- Ports for input only: 12 pads (RC, RD and RG port; RG for W536090P/120P only)
- Ports for output only: 12 pads (RE, RF and RH port; RH for W536090P/120P only)
- Ports for Input/output: 8 pads
Power-down mode
- Hold mode (except for 32KHz oscillator)
- Stop mode (including 32KHz oscillator and release by RD or RC port)
Eight types of interrupts
- Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
- Three external interrupts (Port RC, RD, RA)
One built-in 14-bit clock frequency divider circuit
Two built-in 8-bit programmable countdown timers
- Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
- Timer 1: built-in auto-reload function includes internal timer, external event counter from
RC.0
Built-in 18/14-bit watchdog timer for system reset.
Powerful instruction sets.
8-level subroutine (including interrupt) nesting
W536030P/060P/090P/120P
- 4 -
Speech function
- Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030P/060P/090P/120P based on 5
bits MDPCM algorithm
- Voice ROM (V-ROM) available for uC data.
- Maximum 8*256 Label/Interrupt vector (voice section number) available
- Provide two types of speech busy flag to either each GO or each trigger
- Maximum up to 16M bits speech address capability interface with external memory
W55XXX through serial bus.
Melody function
- Provide 1K notes (22bits/note) dedicated melody ROM
- Provide two types of melody busy flag to uC either each note or each song
- Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
- Tremolo, triple frequency and 3 kinds of percussion available
- Maximum 31 songs available
Can mix speech with melody
Multi-engine controller
Direct driving speaker/buzzer or DAC output
Chip On Board available
W536030P/060P/090P/120P
Publication Release Date: May 21, 2003
- 5 -
Revision A4
3. BLOCK DIAGRAM
PC
STACK
(8
Levels)
Tim er 0
(8 Bit)
Tim ing G enerator
XIN
XO UT
Tim er 1
(8 Bit)
W atch Dog Tim er
(18/14 Bit)
ALU
ACC
Divide
r
(14/10 Bit)
X32I X32O
RO M
8K*20Bit
Data RAM
1K* 4Bit
Interrupt ,Hold
& Stop Control
Special Register
HCF
HEF
IEF
EVF
FLAG 1
PSR0
M R
0
PEF
FLAG 0
LPX3
PM
0
LPX2
LPX0
LPX1
LPX4
LPX5 LPY0
LPY1
SPC
M LD
PO RT RE
PO RT RA
TO NE
RA0~3
RE0~3
PO RT RB
PO RT RD
PO RT RE
RB0~3
RD0~3
PO RT RC
RC0~3
PO RT RG
RG 0~3
PO RT RF
RF0~3
PO RT RH
RH0~3
ADDR
M LD_play
M LD_busy
Speech
M DPCM
core
SPC_play
SPC_busy
PW M 1/DAC
RO SC
Parallel
to
Serial
CLK
DATA
VSSP
TEST
Voice ROM
(1M /2M /3M /4M
bits)
PW M /DAC
M ix
Block
PW M 2
VDDP
LPXY
Shared_RO M Data
RES
VDDA
VSSA
VDD
VSS
Dual Tone
M elody
(1K notes)
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