Publication Release Date: April 2000

- 1 - Revision A6

GENERAL DESCRIPTION

The W536XXXA, a member of ViewTalk

family, is a high-performance 4-bit micro-controller (uC) with

built-in speech unit, melody unit and 64seg * 16 com LCD driver unit which includes internal regulator
,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.

Body W536030A

W536060A

W536090A

W536120A

Voice

30 sec

60 sec

90 sec

120 sec

I/O pad

4I/O,8I
(RA/RC/RD)

8I/O, 8I
(RA/RB/RC/RD)

8I/O, 8I , 8O
(RA/RB/RC/RD/RE/RF)

8I/O, 8I, 8O
(RA/RB/RC/RD/RE/RF
)

WDT
disable/Enable
(Mask Option)

Y Y

Sub-clock
RC/XTAL mode
(Mask Option)

Y Y

RD port shared as
serial bus
(Mask Option)

Y(1) Y(1)

(2)

Tri-state serial bus
(Mask Option) ( 3)

Y Y

Cascaded Voice

ROM through
serial bus (2)

Y(1) Y(1)

(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded

Voice ROM can help to expand voice up to 512 sec by W55XXX chip.

(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this

mask option is disabled to get minimum power consumption in general.

FEATURES

Operating voltage: 2.4 volt ~ 5.5 volt

Watch dog disabled/enabled by mask option

Dual clock operating system

Main clock with RC/Crystal (400 KHz to 4 MHz)

Sub-clock with 32.768 KHz RC/Crystal by mask option

Publication Release Date:April 2000

- 2 - Revision A6

Memory

Program ROM (P-ROM): 32K

20 (ROM Bank0, 1, 2)

Data RAM (W-RAM): 1.4K

4 bit

(RAM Bank 0 is 896 nibbles from 0:000 ~0:37F and 0:380~0:3FF are mapped to special register.

RAM Bank F is 512 nibbles from F:200 ~F:3FF either data RAM or dedicated to script kernel )

LCD RAM (L-RAM): 256

4 bit

2 pages (RAM Bank1, 2 from 200~2FF)

Maximum 24 input/output pads

Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536030A/060A)

Ports for output only: 8 pads (RE & RF port; W536090A/120A available only)

Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536060A/090A/120A
only)

Power-down mode

Hold mode (except for 32kHz oscillator)

Stop mode (including 32kHz oscillator and release by RD or RC port)

Eight types of interrupts

Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)

Three external interrupts (Port RC, RD, RA)

One built-in 14-bit clock frequency divider circuit

Two built-in 8-bit programmable countdown timers

Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected

Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0

Built-in 18/14-bit watchdog timer for system reset.

Powerful instruction sets

8-level subroutine (including interrupt) nesting

LCD driver unit capability

VLCD higher than (VDD-0.5V)

Built-in voltage regulator to V2 pad

64 seg

16 com

1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register

COM 8~ 15 and SEG40~63 can be shared as general input/output by special register

Either uC ROM or voice ROM used as LCD picture

Speech function

Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030A/060A/090A/120A based on 5 bits
MDPCM algorithm

Voice ROM (V-ROM) available for uC data or LCD picture data.

Maximum 8*256 Label/Interrupt vector (voice section number) available

Provide two types of speech busy flag to either each GO or each trigger

Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.

Melody function

Provide 1K notes (22bits/note) dedicated melody ROM

Provide two types of melody busy flag to uC either each note or each song

Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7

Tremolo, triple frequency and 3 kinds of percussion available

Maximum 31 songs available

Can mix speech with melody

Multi-engine controller

Direct driving speaker/buzzer or DAC output

Chip On Board available

Publication Release Date:April 2000

- 3 - Revision A6

BLOCK DIAGRAM

XIN XOUT X32I X32O

LCD DRIVER

STACK

(8 Levels)

Timer 0

Timing

Generator

SEG0~63

V3,V4,V5,V6

Timer 1

Watch Dog

ALU

ACC

Divide

ROM

32K*20Bit

DH1,DH2

COM0~15

RAM

1.4*4Bit

Special Register

HCF

HEF

IEF

EVF

FLAG1

PSR0

MR0

PEF

FLAG0

LPX3

PM0

LPX2

LPX0

LPX1

PORT RA

VLCD PUMP &

REGULATOR

TONE

RA0~3

RES

LPX4

PORT RC

PORT RD

RC0~3

RD0~3

LPX5 LPY0

LPY1

SPC

MLD

Dual

Tone

melody

(1K notes)

MLD_play

MLD_busy

Speech

MDPCM

core

SPC_play

SPC_busy

PWM1/DAC

ROSC

Parallel

to Serial

Interrupt ,Hold & Stop

Control

RE0~3

RF0~3

PORT RB

RB0~3

PORT RE

PORT RF

WRP

RDP

SPDATA

VDD

VSS

VSSP

TEST

Voice ROM

(1M /2M/3M/4M bits)

PWM/DAC

Mix

Block

PWM2

VDDP

LPXY

Shared_ROM Data

Publication Release Date:April 2000

- 4 - Revision A6

PAD DESCRIPTION

SYMBOL I/O

FUNCTION

XIN/RXIN

Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode

XOUT

Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.

X32I/RSUB1 I 32.768 KHz crystal input pad or external resistor node 1 by mask option.

External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.

X32O/RSUB2 O 32.768 KHz crystal output pad or external resistor node 2 by mask option.

External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.

RA0 ~ RA3/TONE I/O

General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.

RB0 ~ RB3

I/O

General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode (W536060A/090A/120A only.)

RC0 ~ RC3

I 4-bit

sch

mitter input with internal pull high option specified by PM3 register bit 2. Each pad
has an independent interrupt capability specified by PEFL special register.
Interrupt and STOP mode wake up source. RC0 is also the external event
counter source of Timer1.

RD0
RD1/RDP
RD2/SPDATA
RD3/WRP
(4)

4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source. RD1~3 will be
shared as the external memory W55XXX interface pads while RD port shared as
serial bus mask option is enabled @W536030A/060A.

For W536030A/060A only, "Tri-state serial bus" mask option can use to float
WRP/RDP/SPDATD while "RD port shared as serial bus" mask option is
enabled.

RE0~RE3

O Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving

capability option. (W536090A/120A only)

RF0~RF3

Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)

RES

System reset pad, active low with internal pull-high resistor.

Publication Release Date:April 2000

- 5 - Revision A6

TEST

Test pad. Active high with internal pull low resistor.

ROSC

Connect resistor to VDD pad to generate speech or melody playing clock source.

PWM1/DAC

While speech or melody is active , PWM1/DAC is speaker direct driving output
or DAC output controlled by voice output file.

PWM2

While speech or melody is active, PWM2 is another speaker direct driving output.

WRP (5)

External serial memory address write clock for voice extension (W536120A only).

RDP (5)

External serial memory address read clock for voice extension. (W536120A only).

SPDATA (5)

I/O

External serial memory data in/out for voice extension (W536120A only).

SEG0

SEG39

Dedicated LCD segment output pads.

SEG40/PORTN.0

SEG43/PORTN.3

O/O

LCD segment output pads, and can be shared as general output by register
LCDM3 bit 1. Default function is segment pad.

SEG44/PORTM.0

SEG47/PORTM.3

O/I

LCD segment output pads, and can be shared as general input by register
LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD
waveform abnormal.

SEG48/PORTL.0

SEG51/PORTL.3

O/O

LCD segment output pads, and can be shared as general output by register
LCDM2 bit 0. Default function is segment pad.

SEG52/PORTK.0

SEG55/PORTK.3

O/I

LCD segment output pads, and can be shared as general input by register
LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD
waveform abnormal.

SEG56/PORTJ.0

SEG59/PORTJ.3

O/IO LCD segment output pads, and can be shared as general input/output by register

LCDM2 bit 2. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.3=0 to inhibit LCD
waveform abnormal.

SEG60/PORTI.0

SEG63/PORTI.3

O/IO LCD segment output pads, and can be shared as general input/output by register

LCDM2 bit 3. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.2=0 to inhibit LCD
waveform abnormal.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W536120A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W536120A