Data Sheet

W66910 PCI ISDN S/T-Controller

Publication Release Date: Feb,2001

Revision 1.0

-3 -

TABLE OF CONTENTS

1. GENERAL DESCRIPTION................................................................................................................................................. 8

2. FEATURES............................................................................................................................................................................ 8

3. PIN CONFIGURATION ..................................................................................................................................................... 9

4. PIN DESCRIPTION........................................................................................................................................................... 11

. SYSTEM DIAGRAM AND APPLICATIONS................................................................................................................ 13

6. BLOCK DIAGRAM ........................................................................................................................................................... 14

7. FUNCTIONAL DESCRIPTIONS..................................................................................................................................... 15

7.1 M

AIN

LOCK

UNCTIONS

................................................................................................................................................... 15

7.2 L

AYER

1 F

UNCTIONS

ESCRIPTIONS

................................................................................................................................... 16

7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 16

7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 20

7.2.3 Layer 1 Activation/Deactivation ................................................................................................................................ 20

7.2.3.1 States Descriptions And Command/Indication Codes .......................................................................................... 20

7.2.3.2 State Transition Diagrams................................................................................................................................... 22

7.2.4 D Channel Access Control ......................................................................................................................................... 26

7.2.5 Frame Alignment ....................................................................................................................................................... 26

7.2.5.1 FAinfA_1fr ......................................................................................................................................................... 27

7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 27

7.2.5.3 FAinfD_1fr ......................................................................................................................................................... 27

7.2.5.4 FAinfA_kfr ......................................................................................................................................................... 27

7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 27

7.2.5.6 FAinfD_kfr ......................................................................................................................................................... 28

7.2.5.7 Faregain.............................................................................................................................................................. 28

7.2.6 Multiframe Synchronization....................................................................................................................................... 28

7.2.7 Test Functions ........................................................................................................................................................... 29

7.3 S

ERIAL

NTERFACE

..................................................................................................................................................... 31

7.4 B C

HANNEL

WITCHING

.................................................................................................................................................... 31

7.5 PCM P

ORT

....................................................................................................................................................................... 33

7.6 D C

HANNEL

HDLC C

ONTROLLER

...................................................................................................................................... 33

7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 34

7.6.2 Reception of Frames in D Channel ............................................................................................................................ 34

7.6.3 Transmission of Frames in D Channel ....................................................................................................................... 35

7.7 B C

HANNEL

HDLC C

ONTROLLER

...................................................................................................................................... 36

7.7.1 Reception of Frames in B Channel

....................................................................................................................... 36

7.7.2 Transmission of Frames in B Channel........................................................................................................................ 37

7.8 GCI M

ODE

ERIAL

NTERFACE

.................................................................................................................................... 38

7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 39

7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 39

7.9 8-

BIT

ICROPROSESSOR

NTERFACE

IRCUIT

...................................................................................................................... 40

7.10 P

ERIPHERAL

ONTROL

..................................................................................................................................................... 40

8. REGISTER DESCRIPTIONS ............................................................................................................................................. 42

Data Sheet

W66910 PCI ISDN S/T-Controller

Publication Release Date: Feb,2001

Revision 1.0

-4 -

8.1 C

HIP

ONTROL AND

HDLC

CONTROLLER

................................................................................................................. 42

8.1.1 D_ch receive FIFO

D_RFIFO Read Address 00H................................................................................................... 44

8.1.2 D_ch transmit FIFO

D_XFIFO Write Address 01H ................................................................................................ 44

8.1.3 D_ch command register

D_CMDR Write Address 02H ............................................................................................ 45

8.1.4 D_ch Mode Register

D_MODE Read/Write Address 03H ....................................................................................... 45

8.1.5 Timer 1 Register

TIMR1 Read/Write Address 04H ................................................................................................... 46

8.1.6 Interrupt Status Register

ISTA Read_clear Address 05H ........................................................................................... 47

8.1.7 Interrupt Mask Register

IMASK Read/Write Address 06H....................................................................................... 48

8.1.8 D_ch Extended Interrupt Register

D_EXIR Read_clear Address 07H ..................................................................... 48

8.1.9 D_ch Extended Interrupt Mask Register

D_EXIM Read/Write Address 08H............................................................ 49

8.1.10 D_ch Transmit Status Register

D_XSTA Read Address 09H ................................................................................... 49

8.1.11 D_ch Receive Status Register

D_RSTA Read Address 0AH .................................................................................... 50

8.1.12 D_ch SAPI Address Mask

D_SAM Read/Write Address 0BH............................................................................. 50

8.1.13 D_ch SAPI1 Register

D_SAP1 Read/Write Address 0CH ...................................................................................... 50

8.1.14 D_ch SAPI2 Register

D_SAP2 Read/Write Address 0DH ...................................................................................... 51

8.1.15 D_ch TEI Address Mask

D_TAM Read/Write Address 0EH.................................................................................. 51

8.1.16 D_ch TEI1 Register

D_TEI1 Read/Write Address 0FH .......................................................................................... 51

8.1.17 D_ch TEI2 Register

D_TEI2 Read/Write Address 10H........................................................................................... 51

8.1.18 D_ch Receive Frame Byte Count High

D_RBCH Read Address 11H...................................................................... 52

8.1.19 D_ch Receive Frame Byte Count Low

D_RBCL Read Address 12H........................................................................ 52

8.1.20 Timer 2

TIMR2 Write Address 13H....................................................................................................................... 52

8.1.21 Layer 1_Ready Code

L1_RC Read/Write Address 14H........................................................................................... 53

8.1.22 Control Register

CTL Read/Write Address 15H .................................................................................................... 53

8.1.23 Command/Indication Receive Register

CIR Read Address 58H/16H....................................................................... 54

8.1.24 Command/Indication Transmit Register

CIX Read/Write Address 17H................................................................... 54

8.1.25 S/Q Channel Receive Register

SQR Read Address 18H ........................................................................................... 55

8.1.26 S/Q Channel Transmit Register

SQX Read/Write Address 19H................................................................................ 55

8.1.27 Peripheral Control Register

PCTL Read/Write Address 1AH .................................................................................. 56

8.1.28 Monitor Receive Channel 0

MO0R Read Address 1BH ........................................................................................... 57

8.1.29 Monitor Transmit Channel 0

MO0X Read/Write Address 1CH................................................................................ 57

8.1.30 Monitor Channel 0 Interrupt Register

MO0I Read_clear Address 1DH ................................................................... 57

8.1.31 Monitor Channel 0 Control Register

MO0C Read/Write Address 1EH ................................................................... 58

8.1.32 GCI Mode Control/Status Register

GCR Read/Write Address 1FH.......................................................................... 58

8.1.33 Peripheral Data Register 1

XDATA1 Read/Write Address 3DH .............................................................................. 59

8.1.34 Peripheral Data Register 2

XDATA2 Read/Write Address 3EH............................................................................... 60

8.1.35 Monitor Receive Channel 1 Register

MO1R Read Address 40H ............................................................................. 60

8.1.36 Monitor Transmit Channel 1 Register

MO1X Read/Write Address 41H .................................................................. 61

8.1.37 Monitor Channel 1 Interrupt Register

MO1I Read_clear Address 42H.................................................................... 61

8.1.38 Monitor Channel 1 Control Register

MO1C Read/Write Address 43H.................................................................... 61

8.1.39 GCI IC1 Receive Register

IC1R Read Address 44H ................................................................................................ 62

8.1.40 GCI IC1 Transmit Register

IC1X Read/Write Address 45H ..................................................................................... 62

8.1.41 GCI IC2 Receive Register

IC2R Read Address 46H ................................................................................................ 62

8.1.42 GCI IC2 Transmit Register

IC2X Read/Write Address 47H ..................................................................................... 62

8.1.43 GCI CI1 Indication Register

CI1R Read Address 48H............................................................................................. 63

8.1.44 GCI CI1 Command Register

CI1X Read/Write Address 49H ................................................................................... 63

8.1.45 GCI Extended Interrupt Register

GCI_EXIR Read_clear Address 4AH ................................................................. 63

8.1.46 GCI Extended Interrupt Mask Register

GCI_EXIM Read/Write Address 4BH ....................................................... 64

8.2 B1 HDLC

CONTROLER

...................................................................................................................................................... 64

8.2.1 B1_ch receive FIFO

B1_RFIFO Read Address 20H.................................................................................................. 65

8.2.2 B1_ch transmit FIFO

B1_XFIFO Write Address 21H ............................................................................................... 65

8.2.3 B1_ch command register

B1_CMDR Read/Write Address 22H ................................................................................. 66

8.2.4 B1_ch Mode Register

B1_MODE Read/Write Address 23H ..................................................................................... 67

8.2.5 B1_ch Extended Interrupt Register

B1_EXIR Read_clear Address 24H .................................................................. 68

Data Sheet

W66910 PCI ISDN S/T-Controller

Publication Release Date: Feb,2001

Revision 1.0

-5 -

8.2.6 B1_ch Extended Interrupt Mask Register

B1_EXIM Read/Write Address 25H......................................................... 69

8.2.7 B1_ch Status Register

B1_STAR Read Address 26H ................................................................................................ 69

8.2.8 B1_ch Address Mask Register 1

B1_ADM1 Read/Write Address 27H....................................................................... 70

8.2.9 B1_ch Address Mask Register 2

B1_ADM2 Read/Write Address 28H....................................................................... 70

8.2.10 B1_ch Address Register 1

B1_ADR1 Read/Write Address 29H............................................................................... 70

8.2.11 B1_ch Address Register 2

B1_ADR2 Read/Write Address 2AH .............................................................................. 70

8.2.12 B1_ch Receive Frame Byte Count Low

B1_RBCL Read Address 2BH ................................................................... 71

8.2.13 B1_ch Receive Frame Byte Count High

B1_RBCH Read Address 2CH ................................................................. 71

8.2.14 B1_ch Transmit Idle Pattern

B1_IDLE Read/Write Address 2DH ......................................................................... 71

8.3 B2 HDLC

CONTROLLER

.................................................................................................................................................... 72

9. ELECTRICAL CHARACTERISTICS ............................................................................................................................... 73

9.1 A

BSOLUTE

AXIMUM

ATING

........................................................................................................................................... 73

9.2 P

OWER

UPPLY

.................................................................................................................................................................. 73

9.3 DC C

HARACTERISTICS

....................................................................................................................................................... 73

9.4 P

RELIMINARY

WITCHING

HARACTERISTICS

..................................................................................................................... 75

9.4.1 PCM Interface Timing ............................................................................................................................................... 75

9.4.2 8-bit Microprocessor Timing...................................................................................................................................... 76

9.5 AC T

IMING

EST

ONDITIONS

........................................................................................................................................... 78

10. ORDERING INFORMATION .......................................................................................................................................... 79

11. PACKAGE SPECIFICATIONS ........................................................................................................................................ 80

Электронный компонент: W66910CD