W6691 Preliminary
ISDN S/T Interface Transceiver
Publication Release Date: Sep 2001
1 Revision 1.1
W6691 ISDN S/T Interface Transceiver
Data Sheet
The information described in this document is the exclusive intellectual property of Winbond Electronics
Corp and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes for W6691-based system design. Winbond
assumes no responsibility for errors or omissions. All data and specifications are subject to change without
notice.
Preliminary W6691
Publication Release Date: Sep 2001
2 Revision 1.1
TABLE OF CONTENTS
REVISION HISTORY.............................................................................................................................. 7
1. GENERAL DESCRIPTION................................................................................................................. 8
2. FEATURES......................................................................................................................................... 9
3. PIN CONFIGURATIONS .................................................................................................................. 10
4. PIN DESCRIPTION .......................................................................................................................... 13
5. SYSTEM DIAGRAM AND APPLICATIONS..................................................................................... 16
6. BLOCK DIAGRAM ........................................................................................................................... 18
7. FUNCTIONAL DESCRIPTIONS....................................................................................................... 19
7.1.1 Main Block Functions ......................................................................................................................19
7.1.2 Interface and Operating Modes .......................................................................................................20
7.2.1 S/T Interface Transmitter/Receiver..................................................................................................20
7.2.2 Receiver Clock Recovery And Timing Generation ..........................................................................25
7.2.3 Layer 1 Activation/Deactivation .......................................................................................................26
7.2.4 Layer 1 Activation /Deactivation in LT-S Mode................................................................................32
7.2.5 D Channel Access Control ..............................................................................................................35
7.2.6 Frame Alignment .............................................................................................................................36
7.2.7Multiframe Synchronization ..............................................................................................................38
7.2.8Test Functions ..................................................................................................................................40
7.3 B Channel Switching ........................................................................................................................ 41
7.4 PCM Port .......................................................................................................................................... 42
7.5 D Channel HDLC Controller ............................................................................................................. 42
7.5.1 D Channel Message Transfer Modes ..............................................................................................44
7.5.2 Reception of Frames in D Channel .................................................................................................45
7.5.3 Transmission of Frames in D Channel ............................................................................................46
7.6 GCI Mode Serial Interface Bus......................................................................................................... 47
7.6.1 GCI Mode C/I Channel Handling .....................................................................................................49
7.6.2 GCI Mode Monitor Channel Handling..............................................................................................50
7.7 8-bit Microprocessor Interface ........................................................................................................ 52
8 REGISTER DESRCRIPTIONS.......................................................................................................... 53
8.1 D Channel HDLC Controller Register Address Map......................................................................... 53
8.2 GCI Bus Control Register Address Map........................................................................................... 54
8.3 Miscellaneous Register Address Map .............................................................................................. 55
8.4 D Channel HDLC Controller Register Memory Map ......................................................................... 55
Preliminary W6691
Publication Release Date: Sep 2001
3 Revision 1.1
8.5 GCI Bus Register Memory Map........................................................................................................ 57
8.6 Miscellaneous Register Memory Map .............................................................................................. 58
Table 8.6 Miscellaneous Register Memory Map .................................................................................... 58
8.7 D channel HDLC Controller Register Description............................................................................. 58
8.7.1 D_ch receive FIFO
D_RFIFO Read Address 00H......................................................................58
8.7.2 D_ch transmit FIFO
D_XFIFO Write Address 01H.....................................................................59
8.7.3 D_ch command register
D_CMDR Write Address 02H .............................................................59
8.7.4 D_ch Mode Register
D_MODE Read/Write Address 03H ..........................................................60
8.7.5 Interrupt Status Register
ISTA Read_clear Address 04H.......................................................61
8.7.6 Interrupt Mask Register
IMASK Read/Write Address 05H...........................................................63
8.7.7 D_ch Extended Interrupt Register
D_EXIR Read_clear Address 06H .......................................63
8.7.8 D_ch Extended Interrupt Mask Register
D_EXIM Read/Write Address 07
H
...............................64
8.7.9 D_ch Transmitter Status Register
D_XSTA Read Address 0AH..............................................65
8.7.10 D_ch Receive Status Register
D_RSTA Read Address 0BH ................................................65
8.7.11 D_ch SAPI Address Mask
D_SAM Read/Write Address 0EH ................................................66
8.7.12 D_ch SAPI1 Register
D_SAP1 Read/Write Address 0FH........................................................67
8.7.13 D_ch SAPI2 Register
D_SAP2 Read/Write Address 10H ........................................................67
8.7.14 D_ch TEI Address Mask
D_TAM Read/Write Address 11H ....................................................67
8.7.15 D_ch TEI1 Register
D_TEI1 Read/Write Address 12H..........................................................68
8.7.16 D_ch TEI2 Register
D_TEI2 Read/Write Address 13H..........................................................68
8.7.17 D_ch Receive Frame Byte Count High
D_RBCH Read Address 16H .....................................69
8.7.18 D_ch Receive Frame Byte Count Low
D_RBCL Read Address 17H....................................69
8.8 GCI Bus Register Description........................................................................................................... 70
8.8.1 Channel Selection Register
CSEL Read/Write Address 18H ................................................70
8.8.2 Command/Indication Receive Register
CIR Read Address 1AH...............................................70
8.8.3 Command/Indication Transmit Register
CIX Read/Write Address 1BH ...................................71
8.8.4 S/Q Channel Receive Register
SQR Read Address 1CH ...........................................................71
8.8.5 S/Q Channel Transmit Register
SQX Read/Write Address 1DH ...............................................72
8.8.6 Monitor Receive Channel 0
MO0R Read Address 20H..........................................................72
8.8.7 Monitor Transmit Channel 0
MO0X Read/Write Address 21H................................................72
8.8.8 Monitor Channel 0 Interrupt Register
MO0I Read_clear Address 22H .................................73
8.8.9 Monitor Channel 0 Control Register
MO0C Read/Write Address 23H .....................................73
8.8.10 GCI Mode Control/Status Register
GCR Read Address 26H .....................................74
8.8.11 Monitor Receive Channel 1 Register
MO1R Read Address 27H ...........................................75
8.8.12 Monitor Transmit Channel 1 Register
MO1X Read/Write Address 28H.......................75
8.8.13 Monitor Channel 1 Interrupt Register
MO1I Read_clear Address 29H ...............................76
8.8.14 Monitor Channel 1 Control Register
MO1C Read/Write Address 2AH ....................................76
8.8.14 GCI CI1 Indication Register
CI1R Read Address 31H ........................................................77
Preliminary W6691
Publication Release Date: Sep 2001
4 Revision 1.1
8.8.16 GCI CI1 Command Register
CI1X Read/Write Address 32H................................................77
8.8.17 GCI Extended Interrupt Register
GCI_EXIR Read_clear Address 34H.....................................78
8.8.18 GCI Extended Interrupt Mask Register GCI_EXIM
Read/Write Address 35H .........................78
8.9 Miscellaneous Register .................................................................................................................... 79
8.9.1 Timer 1 Register
TIMR1 Read/Write Address 38H ....................................................................79
8.9.2 Timer 2
TIMR2 Read/ Write Address 39H................................................................80
8.9.3 Peripheral Control Register
PCR Read/Write Address 3AH........................................................81
8.9.4 Peripheral I/O Data Register
PIODR Read/Write Address 3BH ............................................82
8.9.5 SFCTL Switch Functional Control Register
Read/Write
Address 3CH
83
8.9.6 ACTL1
Auxiliary Control Register 1 Read/Write Address 3DH ..................................................84
8.9.7 ACTL2
Auxiliary Control Register2 Read/Write Address 3EH ..................................................85
8.9.8 ACTL3 Auxiliary Control Register 3
Read/Write Address 3FH .................................................86
8.10 B1 Channel HDLC Controller Register Address MAP .................................................................... 86
8.11 B1 Channel HDLC controller Register Memory Map ...................................................................... 87
8.11.1 B1_ch receive FIFO
B1_RFIFO Read Address 50H ..........................................................87
8.11.2 B1_ch transmit FIFO
B1_XFIFO Write Address 51H ...........................................................87
8.11.3 B1_ch command register
B1_CMDR Read/Write Address 53H ................................................88
8.11.4 B1_ch Mode Register
B1_MODE Read/Write Address 54H....................................................89
8.11.5 B1_ch Extended Interrupt Register
B1_EXIR Read_clear Address 56H...................................90
8.11.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 57H ................91
8.11.7 B1_ch Status Register B1_STAR Read Address 58H.......................................................91
8.11.8 B1_ch Address Mask Register 1
B1_ADM1 Read/Write Address 59H ..................................92
8.11.9 B1_ch Address Mask Register 2
B1_ADM2 Read/Write Address 5AH .....................................93
8.11.10 B1_ch Address Register 1
B1_ADR1 Read/Write Address 5BH ...........................................93
8.11.11 B1_ch Address Register 2
B1_ADR2 Read/Write Address 5CH...........................................93
8.11.12 B1_ch Receive Frame Byte Count Low
B1_RBCL Read Address 5DH ................................93
8.11.13 B1_ch Receive Frame Byte Count High
B1_RBCH Read Address 5EH ...............................94
8.11.14B1_ch Transmit Idle Pattern
B1_IDLE Read/Write Address 5FH .............................................94
8.12 B2 Channel HDLC Controller Register Address Map..................................................................... 95
8.13 B2 Channel HDLC Controller Register Memory Map ..................................................................... 95
9. ELECTRICAL CHARACTERISTICS ................................................................................................ 97
9.1 Absolute Maximum Rating................................................................................................................ 97
9.2 Power Supply ................................................................................................................................... 97
9.3 DC Characteristics............................................................................................................................ 97
9.4 Preliminary Switching Characteristics .............................................................................................. 99
9.4.1 PCM Interface Timing......................................................................................................................99
9.4.2 8-bit Microprocessor Timing ..........................................................................................................101
Preliminary W6691
Publication Release Date: Sep 2001
5 Revision 1.1
9.5 AC Timing Test Conditions............................................................................................................. 104
10. ORDERING INFORMATION ........................................................................................................ 104
11. PACKAGE DIMENSIONS ............................................................................................................ 105
LIST OF FIGURES
FIG.3.1 W6691 PIN CONFIGURATION - INTEL BUS MODE ............................................................. 10
FIG.3.2 W6691 PIN CONFIGURATION MOTOROLA BUS MODE .................................................. 12
FIG.5.1 ISDN INTERNET PASSIVE S-CARD WITH TWO POTS CONNECTIONS ........................... 16
FIG.5.2 ISDN PAXB APPLICATION..................................................................................................... 17
FIG.6.1 W6691 FUNCTIONAL BLOCK DIAGRAM .............................................................................. 18
FIG.7.1 FRAME STRUCTURE AT S/T INTERFACE ........................................................................... 21
FIG.7.2 W6691 WIRING CONFIGURATION IN TE APPLICATIONS.................................................. 22
FIG.7.3 EXTERNAL TRANSMITTER CIRCUITRY .............................................................................. 23
FIG.7.4 EXTERNAL RECEIVER CIRCUITRY...................................................................................... 24
FIG.7.5 LAYER 1 ACTIVATION/DEACTION STATE DIAGRAM NORMAL MODE .......................... 30
FIG.7.6 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM - SPECIAL MODE ................... 31
FIG.7.7 LAYER 1 ACTIVATION/DEACTIVATION STATE DIAGRAM IN LT-S.................................... 34
FIG.7.9 SSP AND SCP TEST SIGNALS.............................................................................................. 41
FIG.7.10 GCI TE MODE CHANNEL STRUCTURE.............................................................................. 48
FIG.7.11 GCI NON TERMINAL MODE CHANNEL STRUCTURE..................................................... 49
LIST OF TABLES
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE ........................................................ 25
TABLE 7.2 LAYER 1 COMMAND CODES ........................................................................................... 28
TABLE 7.3 LAYER 1 INDICATION CODES ......................................................................................... 28
TABLE 7.4 LAYER 1 COMMAND CODES ........................................................................................... 33
TABLE 7.5 LAYER 1 INDICATION CODES ......................................................................................... 33
TABLE 7.8 D PRIORITY CLASSES ..................................................................................................... 35
TABLE 7.9 D PRIORITY COMMANDS/INDICATIONS ........................................................................ 35
TABLE 7.10 MULTIFRAME STRUCTURE IN S/T INTERFACE .......................................................... 39
TABLE 8.1 D CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................... 53
TABLE 8.2 GCI BUS CONTROL REGISTER ADDRESS MAP ........................................................... 54
TABLE 8.3 MISCELLANEOUS REGISTER ADDRESS MAP .............................................................. 55
TABLE 8.4 D CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP..................................... 55
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