W741L250

4-BIT MICROCONTROLLER

Publication Release Date: March 1998

- 1 -

Revision A2

Table of Contents--

GENERAL DESCRIPTION ..............................................................................................................................2

FEATURES......................................................................................................................................................2

PIN CONFIGURATION ....................................................................................................................................3

PIN DESCRIPTION..........................................................................................................................................4

BLOCK DIAGRAM ...........................................................................................................................................5

FUNCTIONAL DESCRIPTION ........................................................................................................................6

ABSOLUTE MAXIMUM RATINGS ................................................................................................................31

DC CHARACTERISTICS...............................................................................................................................32

AC CHARACTERISTICS ...............................................................................................................................33

PAD ASSIGNMENT & POSITIONS...............................................................................................................33

TYPICAL APPLICATION CIRCUIT................................................................................................................35

INSTRUCTION SET TABLE ..........................................................................................................................36

PACKAGE DIMENSION ................................................................................................................................84

W741L250

- 2 -

GENERAL DESCRIPTION

The W741L250 is a high-performance 4-bit microcontroller (

C) that provides an LCD driver. The

device contains a 4-bit ALU, two 8-bit timers, a divider, a 24

4 LCD driver, and five 4-bit I/O ports

(including 1 output port for high sink current). There are also five interrupt sources and 8-level
subroutine nesting for interrupt applications. The W741L250 operates on very low voltage and very
low current and has two power reduction modes, hold mode and stop mode, which help to minimize
power dissipation.

The W741L250 is suitable for handheld games, watches, clocks, speech synthesis LSI controllers,
and other products.

FEATURES

Operating voltage: 1.2V to 1.8V (LCD drive voltage: 3.0V or 4.5V)

Operating frequency up to 1 MHz

Crystal/RC oscillation circuit selectable by code option for system clock

Only low-frequency clock (32.768 KHz) for crystal mode

Memory

2048

16 bit program ROM (including 2K

4 bit look-up table)

128

4 bit data RAM (including 16 working registers)

4 LCD data RAM

21 input/output pins

Ports for input only: 2 ports/8 pins

Input/output ports: 2 ports/8 pins

Port for output only: 1 port /4 pins (high sink current)

MFP output pin: 1 pin (MFP)

Power-down mode

Hold function: no operation (except for oscillator)

Stop function: no operation (including oscillator)

Five types of interrupts

Three internal interrupts (Divider 0, Timer 0, Timer 1)

Two external interrupts (Port RC and

INT

pin)

LCD driver output

24 segment

4 common

Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be
selected

LCD driver output pins can be used as DC output port by code option

W741L250

Publication Release Date: March 1998

- 3 -

Revision A2

MFP output pin

Output is software selectable as modulating or nonmodulating frequency

Works as frequency output specified by Timer 1

Built-in 14-bit clock frequency divider circuit

Two built-in 8-bit programmable countdown timers

Timer 0: One of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)

Built-in 18/14-bit watchdog timer selectable for system reset

Powerful instruction set: 116 instructions

8-level subroutine (include interrupt) nesting

Up to 4

S instruction cycle (with 1 MHz operating frequency)

Packaged in 64-pin QFP

PIN CONFIGURATION

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

2 3

6 7

9 10 11 12 13 14 15 16 17 18 19

RD1

RD0

RC3

RC2

RC1

RC0

RB3

RB1

/
I
N
T

/
R
E
S

D N N

D C C

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

3 2

0 1

4 5

E E

R R

3 0

S S S

E E

G G

0 9

SEG9

SEG8

SEG7

SEG6

RB0

RA3

RA2

RA
1

RB2

2 1

W741L250

- 4 -

PIN DESCRIPTION

SYMBOL

I/O

FUNCTION

XIN

Input pin for oscillator.
Connected to crystal or resistor to generate system clock by code option.

XOUT

Output pin for oscillator.
Connected to crystal or resistor to generate system clock by code option.

RA0

RA3

I/O

Input/Output port.
Input/output mode specified by port mode 1 register (PM1).

RB0

RB3

I/O

Input/Output port.
Input/output mode specified by port mode 2 register (PM2).

RC0

RC3

4-bit port for input only.
Each pin has an independent interrupt capability.

RD0

RD3

4-bit port for input only.

RE0

RE3

Output port only.
This port provides high sink current.

MFP

Output pin only.
This pin can output modulating or nonmodulating frequency, or Timer 1
clock output specified by mode register 1 (MR1).

INT

External interrupt pin with pull-high resistor.

RES

System reset pin with pull-high resistor.

SEG0

SEG23

LCD segment output pins.
Also can be used as DC output ports specified by code option.

COM0

COM3

LCD common signal output pins.

Static

COM0

COM1

COM2

COM3

Used

Not Used

1/2 Duty

Not Used

1/3 Duty

Not Used

1/4 Duty

Used

The LCD alternating frequency can be selected by code option.

DH1, DH2

Connection terminals for voltage doubler (halver) capacitor.

DD1

DD2

DD3

Positive (+) supply voltage terminal.

Refer to Functional Description.

Positive power supply (+).

Negative power supply (-).

W741L250

Publication Release Date: March 1998

- 5 -

Revision A2

BLOCK DIAGRAM

LCD DRIVER

STACK

(8 Levels)

RAM

(128*4)

ALU

Timer 0

(8 Bit)

Timing Generator

PORT RA

PORT RB

PORT RD

PORT RC

Modulation
Frequency
Pulse

SEG0 to SEG23 COM0 to COM3

RA0 to 3

RB0 to 3

RD0 to 3

RC0 to 3

RE0 to 3

MFP

XIN

XOUT

VDD

VSS

VDD1 to 3 DH1 to 2

ROM

(2048*16)

(look_up table
2K*4)

Timer 1

(8 Bit)

ACC

RES

INT

Divider 0

(14 Bit)

Watchdog Timer

(4 Bit)

HCF

PEF

HEF

IEF

Central Control

Unit

EVF

SEF

PSR0

MR1

MUX

SEL

+1(+2)

PORT RE

W741L250

- 6 -

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses
of the 2048

16 on-chip ROM containing the program instruction words. When jump or subroutine

call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to
the instruction will be loaded into the program counter. The format used is shown below.

ITEM

ADDRESS

INTERRUPT PRIORITY

Initial Reset

000H

INT 0 (Divider 0)

004H

1st

INT 1 (Timer 0)

008H

2nd

INT 2 (Port RC)

00CH

3rd

INT 4 (

INT

pin)

014H

4th

INT 7 (Timer 1)

020H

5th

JP Instruction

XXXH

Subroutine Call

XXXH

Stack Register (STACK)

The stack register is organized as 11 bits

8 levels (first-in, last-out). When either a call subroutine or

an interrupt is executed, the program counter will be pushed onto the stack register automatically. At
the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed
to pop the contents of the stack register into the program counter. When the stack register is pushed
over the eighth level, the contents of the first level will be lost. In other words, the stack register is
always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048

4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but

the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up
table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.
There are two registers (TABL and TABH) to be used in look-up table addressing and they are
controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is
executed, the contents of the look-up table location address specified by TABH, TABL and ACC will
be read and transfered to the data RAM. Refer to the instruction table for more details. The
organization of the program memory is shown in Figure 1.

W741L250

Publication Release Date: March 1998

- 7 -

Revision A2

3 2 1 0

7FFH

600H

2048

address

000H

16 bits

2048 x 16-bit

ACC

TABL

TABH

ROM address = 600H + Offset/4

Offset

0 1 1 x x x x x

x x x x

- x x x

x x x x

x x y y

Each element (4 bits) of the look-up table

This area can be used to store both instruction code
and look-up table

Figure 1. Program Memory Organization

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128

4 bits. The data memory can

be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

Working Register

128

address

00H

4 bits

128 x 4-bit

7FH

0FH

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers
(WR). The other data memory is used as general memory and cannot operate directly with immediate
data. The relationship between data memory locations and the page register (PAGE) in indirect
addressing mode is described in the next section.

W741L250

- 8 -

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

PAGE

Note: R/W means read/write available.

Bit 3 is reserved.

Bit 2, Bit 1, Bit 0 are indirect addressing mode preselect bits:

000 = Page 0 (00H

0FH)

001 = Page 1 (10H

1FH)

010 = Page 2 (20H

2FH)

011 = Page 3 (30H

3FH)

100 = Page 4 (40H

4FH)

101 = Page 5 (50H

5FH)

110 = Page 6 (60H

6FH)

111 = Page 7 (70H

7FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

Logic operations: ANL, XRL, ORL

Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

Shift operations: SHRC, RRC, SHLC, RLC

Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. CF can be read out by executing MOVA R, CF.

Clock Generator

The W741L250 provides a crystal or RC oscillation circuit selected by option codes to generate the
system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic
resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate
frequency is needed. When a crystal oscillator is used, only low-frequency clock (32 KHz) can be
selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the
range of 28 K

to 1.6 M

must be connected to XIN and XOUT, as shown in Figure 3. The system

clock frequency range is from 32 KHz to 2 MHz. One machine cycle consists of a four-phase system
clock sequence and can run up to 4

S with a 1 MHz system clock.

XIN

XOUT

XIN

XOUT

Crystal

Resistor

32 KHz

Figure 3. Oscillator Configuration

W741L250

Publication Release Date: March 1998

- 9 -

Revision A2

Divider 0

Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as
shown in Figure 4. When the system starts, the divider is incremented by each system clock (F

OSC

When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt
enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag
has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be
reset by executing the CLR DIVR0 instruction.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set
to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F

OSC

/1024. The input clock of the WDT can be switched to F

OSC

/16384 (or F

OSC

/1024) by executing

the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.
The WDT minimun overflow period is 468.75 mS when the system clock (F

OSC

) is 32 KHz and WDT

clock input is F

OSC

/1024. When the corresponding option code bit of the WDT is set to 0, the WDT

function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

Q10 Q11 Q12

Q14

Q13

Fosc

HEF.0

IEF.0

1. Reset

2. CLR EVF, #01H

EVF.0

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

...

Overflow signal

WDT

Enable
/Disable

PMF.3

Fosc/1024

Fosc/16384

Mask Option

Qw1

Qw2

Qw4

Qw3

Divider0

System Reset

1. Reset

2. CLR WDT

3. CLR DIVR0

Figure 4. Organization of Divider 0 and Watchdog Timer

Timer/Counter

1. Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L
(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),
the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the
event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops
operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1
has been set (HEF.1 = 1). The Timer 0 clock input can be set as F

OSC

/1024 or F

OSC

/4 by setting

W741L250

- 10 -

MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is F

OSC

/4. The organization of Timer 0

is shown in Figure 5.

If the Timer 0 clock input is F

OSC

/4:

Desired Timer 0 interval = (preset value +1)

1/F

OSC

If the Timer 0 clock input is F

OSC

/1024:

Desired Timer 0 interval = (preset value +1)

1024

1/F

OSC

Preset value: Decimal number of Timer 0 preset value

OSC

: Clock oscillation frequency

Fosc/4

Fosc/1024

Enable

Disable

1. Reset

2. CLR EVF, #02H

8-bit Binary

Down Counter

HEF.1

IEF.1

Hold mode release (HCF.1)

Timer 0 interrupt (INT1)

1. Reset
2. CLR EVF, #02H

EVF.1

MR0.0

(Timer 0)

1. Set MR0.3 to 1

2. MOV TM0, #I

3. Reset MR0.3 to 0

3. Set MR0.3 to 1
4. MOV TM0, #I

MOV TM0H, R

MOV TM0L, R

4. MOV TM0L, R or MOV TM0H, R

MOV TM0, #I

Figure 5. Organization of Timer 0

2. Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can
be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The
input clock of Timer 1 can be one of three sources: F

OSC

/64, F

OSC

, or an external clock from the

RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At
initial reset, the Timer 1 clock input is F

OSC

. If an external clock is selected as the clock source of

Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L,
R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer
and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set
(MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1
starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is
executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-
reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count
by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and
be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is
executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if
the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can
be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make
Timer 1 stop or start counting.

W741L250

Publication Release Date: March 1998

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Revision A2

If the Timer 1 clock input is F

T, then

Desired Timer 1 interval = (preset value +1) / F

Desired frequency for MFP output pin = F

(preset value + 1)

2 (Hz)

Preset value: Decimal number of Timer 1 preset value, and
F

OSC

: Clock oscillation frequency

Auto-reload buffer

8 bits

MR1.1

External clock

via RC.0

1. MR1.3 = 1
2. MOV TM1, #I

Underflow

signal

EVF.7

MFP

MFP signal

MR1.2

output pin

8-bit Binary

Down Counter

circuit

Reset

Disable

Enable

Fosc/64

Fosc

MR1.0

(Timer 1)

1. Reset
2. INT 7 accept
3. CLR EVF, #80H

1. MR1.3 = 0

4. Set MR1.3 to 1

MOV TM1H, R

MOV TM1L, R

Set MR1.3 to 1

MOV TM1, #I

5. MOV TM1, #I

MOV TM1, #I

Figure 6. Organization of Timer 1

For example, when F

equals 32768 Hz, depending on the preset value of TM1, the MFP pin will

output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between
the tone frequency and the preset value of TM1 is shown in the table below.

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

130.81

7CH

131.07

261.63

3EH

260.06

523.25

1EH

528.51

138.59

75H

138.84

277.18

3AH

277.69

554.37

1CH

564.96

146.83

6FH

146.28

293.66

37H

292.57

587.33

1BH

585.14

155.56

68H

156.03

311.13

34H

309.13

622.25

19H

630.15

164.81

62H

165.49

329.63

31H

327.68

659.26

18H

655.36

174.61

5DH

174.30

349.23

2EH

372.36

698.46

16H

712.34

185.00

58H

184.09

369.99

2BH

390.09

739.99

15H

744.72

196.00

53H

195.04

392.00

29H

420.10

783.99

14H

780.19

207.65

4EH

207.39

415.30

26H

443.81

830.61

13H

819.20

220.00

49H

221.40

440.00

24H

442.81

880.00

12H

862.84

233.08

45H

234.05

466.16

22H

468.11

932.23

11H

910.22

246.94

41H

248.24

493.88

20H

496.48

987.77

10H

963.76

Note: Central tone is A4 (440 Hz).

W741L250

- 12 -

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control
the operation of Timer 0. The bit descriptions are as follows:

MR0

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 0 is F

OSC

/4.

= 1 The internal fundamental frequency of Timer 0 is F

OSC

/1024.

Bit 1 Reserved

Bit 2 Reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is F

OSC

= 1 The internal fundamental frequency of Timer 1 is F

OSC

/64.

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.

Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

Interrupts

The W741L250 provides three internal interrupt sources (Divider 0, Timer 0, Timer 1) and two

external interrupt sources (

INT

, port RC). Vector addresses for each of the interrupts are located in

the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are
used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF
and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the
interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also

W741L250

Publication Release Date: March 1998

- 13 -

Revision A2

be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the
hold mode will be released momentarily and the interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the

C will enter hold mode again. The operation

flow chart is shown in Figure 8. The control diagram is shown below.

Interrupt Event Control Diagram

IEF.0

IEF.1

Interrupt

Process

Circuit

Interrupt

Vector

Generator

004H

008H

014H

IEF.2

Initial Reset

MOV IEF, #I

Enable

EN INT

EVF.1

EVF.0

EVF.2

Initial Reset
CLR EVF, #I instruction

DIS INT instruction

Disable

Divider 0

overflow signal

Timer 0

underflow signal

Port RC

signal change

Timer 1

underflow signal

falling edge signal

IEF.4

EVF.4

IEF.7

EVF.7

INT pin

00CH

020H

Figure 7. Interrupt Event Control Diagram

Stop Mode Operation

In stop mode, all operations of the

C cease (including the operation of the oscillator). The

C enters

stop mode when the STOP instruction is executed and exits stop mode when an external trigger is

activated (by a low level on the

INT

pin or a falling signal on the RC port). When the designated

signal is accepted, the

C awakens and executes the next instruction (if the corresponding bits of IEF

and PEF have been set, It will enter the interrupt service routine after stop mode released). To
prevent erroneous execution, the NOP instruction should follow the STOP command.

W741L250

- 14 -

Hold Mode Operation

In hold mode, all operations of the

C cease, except for the operation of the oscillator, timer, and

LCD driver. The

C enters hold mode when the HOLD instruction is executed. The hold mode can be

released in one of five ways: by the action of Timer 0, Timer 1, Divider 0, the

INT

pin, or the RC port.

Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold
mode release conditions. For more details, refer to the instruction-set table and the following flow
chart.

Divider 0, Timer 0, Timer 1

HOLD
Mode?

IEF

Flag Set?

PC <- (PC+1)

IEF

Flag Set?

Yes

HOLD

HEF

Flag Set?

Reset EVF.n Flag

Execute

Interrupt Service Routine

Reset EVF.n Flag

Execute

Interrupt Service Routine

Port RC

INT, Signal Change on

Interrupt

Enable?

Interrupt

Enable?

Yes

Disable interrupt

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

(Note)

Figure 8. Hold Mode and Interrupt Operation Flow Chart

W741L250

Publication Release Date: March 1998

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Revision A2

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:

HEF

Note: W means write only.

HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released.

HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.

HEF.2 = 1 Signal change at port RC causes hold mode to be released.

HEF.3 Reserved

HEF.4 = 1 Falling edge signal at the

INT

pin causes hold mode to be released.

HEF.5 & HEF.6 are reserved.

HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used
to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these
interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are
unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I

EN INT

is executed again. Besides, these interrupts can be disable by executing DIS INT instruction.

The bit descriptions are as follows:

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from Divider 0.

IEF.1 = 1 Interrupt 1 is accepted by underflow from Timer 0.

IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.

IEF.3 Reserved

IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal on the

INT

pin.

IEF.5 & IEF.6 are reserved.

IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

W741L250

- 16 -

Port Enable Flag (PEF)

The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or perform an interrupt function, the content of the PEF must be set
first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

PEF

Note: W means write only.

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.

PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.

PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.

PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).
Before port RC may be used to make the device exit the stop mode, the content of the SEF must be
set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

SEF

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.

SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.

SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.

SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It
indicates by which interrupt source the hold mode has been released, and it is loaded by hardware.
The HCF can be read out by the MOVA R, HCFL

and MOVA R, HCFH instructions. When any of the

HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be
reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF
has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as
follows:

HCF

Note: R means read only.

W741L250

Publication Release Date: March 1998

- 17 -

Revision A2

HCF.0 = 1 Hold mode was released by overflow from Divider 0.

HCF.1 = 1 Hold mode was released by underflow from Timer 0.

HCF.2 = 1 Hold mode was released by a signal change on port RC.

HCF.3 Reservsd

HCF.4 = 1 Hold mode was released by a falling edge signal on the

INT

pin.

HCF.5 = 1 Hold mode was released by underflow from Timer 1.

HCF.6 & HCF.7 are reserved.

Event Flag (EVF)

The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset
by the CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

EVF

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred.

EVF.1 = 1 Underflow from Timer 0 occurred.

EVF.2 = 1 Signal change on port RC occurred.

EVF.3 Reserved

EVF.4 = 1 Falling edge signal on the

INT

pin occurred.

EVF.5 & EVF.6 are reserved.

EVF.7 = 1 Underflow from Timer 1 occurred.

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled
by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

PMF

Note: W means write only.

Bit 0, Bit1, Bit2

Reserved

Bit 3 = 0 The fundamental frequency of the watchdog timer is F

OSC

/1024.

= 1 The fundamental frequency of the watchdog timer is F

OSC

/16384.

W741L250

- 18 -

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used
to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction.
The bit descriptions are as follows:

PM0

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type.

Bit 0 = 1 RA port is NMOS open drain output type.

Bit 1 = 0 RB port is CMOS output type.

Bit 1 = 1 RB port is NMOS open drain output type.

Bit 2 = 0 RC port pull-high resistor is disabled.
Bit 2 = 1 RC port pull-high resistor is enabled.

Bit 3 = 0 RD port pull-high resistor is disabled.
Bit 3 = 1 RD port pull-high resistor is enabled.

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used
to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit
descriptions are as follows:

PM1

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin.

Bit 0 = 1 RA.0 works as input pin.

Bit 1 = 0 RA.1 works as output pin.

Bit 1 = 1 RA.1 works as input pin.

Bit 2 = 0 RA.2 works as output pin.

Bit 2 = 1 RA.2 works as input pin.

Bit 3 = 0 RA.3 works as output pin.

Bit 3 = 1 RA.3 works as input pin.

After initial reset, port RA is in input mode (PM1 = 1111B).

W741L250

Publication Release Date: March 1998

- 19 -

Revision A2

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used
to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit
descriptions are as follows:

PM2

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin.

Bit 0 = 1 RB.0 works as input pin.

Bit 1 = 0 RB.1 works as output pin.

Bit 1 = 1 RB.1 works as input pin.

Bit 2 = 0 RB.2 works as output pin.

Bit 2 = 1 RB.2 works as input pin.

Bit 3 = 0 RB.3 works as output pin.

Bit 3 = 1 RB.3 works as input pin.

After initial reset, port RB is in input mode (PM2 = 1111B).

Reset Function

The W741L250 is reset either by a power-on reset or by using the external

RES

pin. The initial state

of the W741L250 after the reset function is executed is described below.

Program Counter (PC)

000H

TM0, TM1

Reset

MR0, MR1, PM0, PAGE, PMF registers

Reset

PM1, PM2 registers

Set (1111B)

PSR0 register

Reset

IEF, HEF, HCF, PEF, EVF, SEF flags

Reset

Timer 0 input clock

OSC

Timer 1 input clock

OSC

MFP output

Low

Input/output ports RA, RB

Input mode

Output port RE

High

RA & RB ports output type

CMOS type

RC & RD ports pull-high resistors

Disabled

Input clock of the watchdog timer

OSC

/1024

LCD display

OFF

Segment output mode

LCD drive output

W741L250

- 20 -

External INT

The external interrupt

INT

pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the

falling edge of the

INT

pin will execute the hold mode release or interrupt subroutine. A low level on

the

INT

will release the stop mode.

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. After initial reset,
input/output ports RA and RB are both in input mode. When RA and RB are used as output ports,
CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or
RB can be specified as input or output mode independently by the PM1 and PM2 registers. The
MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV
RB, R operate the output functions. For more details, refer to the instruction table and Figure 9.

I/O PIN

RA.n(RB.n)

DATA

BUS

Buffer

Output

PM0.0 (or PM0.1)

PM1.n
(or PM2.n)

MOVA R, RA
(or MOVA R, RB)
instruction

MOV RA, R
(or MOV RB, R)
Instruction

Enable

Input/Output Pin of the RA(RB)

Figure 9. Architecture of Input/Output Pins

Input Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port
RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register
(PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change on the
specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status
register 0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up
the port. PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In
addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will
cause the device to exit the stop mode

Refer to Figure 10 and the instruction table for more details.

The RD port is used as input port only, it has no hold mode release, wake-up stop mode or interrupt
functions.

W741L250

Publication Release Date: March 1998

- 21 -

Revision A2

Reset

CLR PSR0

HCF.2

INT 2

Reset

CLR EVF, #I

EVF.2

HEF.2

IEF.2

MOV PEF, #I

Signal

change

detector

PEF.0

DATA BUS

PEF.3

Signal

change

detector

PEF.1

Signal

change

detector

PEF.2

Signal

change

detector

PSR0.0

PSR0.1

PSR0.2

PSR0.3

RC.3

PM0.2

RC.2

PM0.2

RC.1

PM0.2

RC.0

PM0.2

SEF.0

SEF.3

SEF.1

SEF.2

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Wake up from STOP mode

Figure 10. Architecture of Input Ports RC

Output Port RE

When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE.

Port RE (RE.0 to RE.3) also provides high sink current output.

Port Status Register 0 (PSR0)

Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

PSR0

Note: R means read only.

Bit 0 = 1 Signal change on RC.0.
Bit 1 = 1 Signal change on RC.1.
Bit 2 = 1 Signal change on RC.2.
Bit 3 = 1 Signal change on RC.3.

W741L250

- 22 -

MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is
determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of
MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal
from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz,
2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to
specify the modulation output combination. The data specified by the 8-bit operand and the MFP
output pin are shown as below:

OSC

= 32.768 KHz)

R7 R6

FUNCTION

Low level

128 Hz

64 Hz

0 0

8 Hz

4 Hz

2 Hz

1 Hz

High level

128 Hz

64 Hz

0 1

8 Hz

4 Hz

2 Hz

1 Hz

2048 Hz

2048 Hz * 128 Hz

2048 Hz * 64 Hz

1 0

2048 Hz * 8 Hz

2048 Hz * 4 Hz

2048 Hz * 2 Hz

2048 Hz * 1 Hz

4096 Hz

4096 Hz * 128 Hz

1 1

4096 Hz * 64 Hz

4096 Hz * 8 Hz

4096 Hz * 4 Hz

4096 Hz * 2 Hz

4096 Hz * 1 Hz

W741L250

Publication Release Date: March 1998

- 23 -

Revision A2

LCD Controller/Driver

The W741L250 can directly drive an LCD with 24 segment output pins and 4 common output pins for
a total of 24

4 dots. Option codes can be used to select one of five options for the LCD driving

mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure
12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In
addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to
segment 23) as a DC output port. The structure of the LCD alternating frequency (F

LCD

) is shown in

the figure below.

Timing

Generator

Q14

...

Fosc

Fosc/32

High frequency clock

Divider 0

Selector

Fw/512

Fw/256

Fw/128

Fw/64

Low frequency clock

LCD

Figure 11. LCD Alternating Frequency (F

LCD

) Circuit Diagram

LCD Data RAM

(24 x 4 bits)

Common

LCD Voltage
Controller

Segment

Data Bus

COM0 to 3

SEG0 to 23

Clock

Generator

LCD Mode
Controller

DH1

DH2

Option Codes

Driver

LCD Duty & Bias

LCD Frequency
Selection

LCD Drive
Mode
Selection

MOV LCDM, #I
Instruction

Driver/Controller

LCD

Waveform

LCD

DD1 to 3

Figure 12. LCD Driver/Controller Circuit Diagram

W741L250

- 24 -

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY

STATIC

1/2 DUTY

1/3 DUTY

1/4 DUTY

Fw/512 (64 Hz)

Fw/256 (128 Hz)

128

Fw/128 (256 Hz)

256

128

Fw/64 (512 Hz)

512

256

171

128

Corresponding to the 24 LCD drive output pins, there are 24 LCD data RAM segments (LCDR00 to
LCDR17). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR,
ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the
segment output pins automatically without program control. When the bit value of the LCD data RAM
is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," the LCD is turned off.
The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 23 pins by
a direct memory access. The relationship between the LCD data RAM and segment/common pins is
shown below.

COM3

COM2

COM1

COM0

LCD data RAM

Output pin

bit 3

bit 2

bit 1

bit 0

LCDR00

SEG0

0/1

LCDR01

SEG1

0/1

.
.
.

LCDR16

SEG22

0/1

LCDR17

SEG23

0/1

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction
turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state
ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON
must be executed. When the drive output pins are used as DC output ports (set by option codes,
please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS
output type can be selected by executing the instruction MOV LCDM, #I. The relation between the
LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to
the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD
data RAM segments can be used as normal data RAM to store data.

LCD DATA RAM

OUTPUT PIN

BIT 3

BIT 2

BIT 1

BIT 0

LCDR00

SEG3

SEG0

SEG3

SEG2

SEG1

SEG0

LCDR03

LCDR01

LCDR04

SEG7

SEG4

SEG7

SEG6

SEG5

SEG4

LCDR07

LCDR05

.
.
.

LCDR14

SEG23

SEG20

SEG23

SEG22

SEG21

SEG20

LCDR17

LCDR15

W741L250

Publication Release Date: March 1998

- 25 -

Revision A2

The relationship between the LCD drive mode and the maximum number of drivable LCD segments
is shown below.

LCD DRIVE MODE

MAX. NUMBER OF

DRIVABLE LCD SEGMENTS

CONNECTION AT

POWER INPUT

Static

24 (COM1)

Connect V

DD3,

DD2

DD1

1/2 bias 1/2 duty

48 (COM1

COM2)

Connect V

DD3

to V

DD2

1/2 bias 1/3 duty

72 (COM1

COM3)

Connect V

DD3

to V

DD2

1/3 bias 1/3 duty

72 (COM1

COM3)

1/3 bias 1/4 duty

96 (COM1

COM4)

LCD Output Mode Type Flag (LCDM)

The LCD output mode type flag is organized as a 6-bit binary register (LCDM.0 to LCDM.5). These
bits are used to control the LCD output pin architecture. When the LCD output pins are set to DC
output mode by option codes, the architecture of these output pins (segment 0 to segment 23) can be
selected as CMOS or NMOS type by the MOV LCDM, #I instruction. The bit descriptions are as
follows:

LCDM

Note: W means write only.

LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.

= 1 SEG0 to SEG3 work as NMOS output type.

LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.

= 1 SEG4 to SEG7 work as NMOS output type.

LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.

= 1 SEG8 to SEG11 work as NMOS output type.

LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.

= 1 SEG12 to SEG15 work as NMOS output type.

LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.

= 1 SEG16 to SEG19 work as NMOS output type.

LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.

= 1 SEG20 to SEG23 work as NMOS output type.

W741L250

- 26 -

The output waveforms for the five LCD driving modes are shown below.

Static Lighting System (Example)

Normal Operating Mode

COM0

Lit LCD driver

outputs

VDD2
VDD1
VSS

Unlit LCD driver

VDD2
VDD1
VSS

outputs

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

COM0

VDD2
VDD1
VSS

COM1

VDD2
VDD1
VSS

LCD driver

outputs for
seg. on COM0,
COM1 sides
being unlit

outputs for
only seg. on
COM0 side
being lit

VDD2
VDD1
VSS

LCD driver

outputs for
only seg. on
COM1 side
being lit

outputs for
seg. on COM0,
COM1 sides
being lit

W741L250

Publication Release Date: March 1998

- 27 -

Revision A2

1/2 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

VDD2
VDD1
VSS

COM2

COM0

COM1

VDD2
VDD1
VSS

LCD driver
outputs for all
seg. on COM0,1,2
sides being unlit

LCD driver
outputs for only
seg. on COM0
side being lit

VDD2
VDD1
VSS

LCD driver
outputs for only
seg. on COM1
side being lit

LCD driver
outputs for only
seg. on COM0,1
sides being lit

VDD2
VDD1
VSS

LCD driver
outputs for only
seg. on COM2
side being lit

LCD driver
outputs for only
seg. on COM0,2
sides being lit

W741L250

- 28 -

1/3 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

COM0

VDD2
VDD1
VSS

COM2

VDD3

VDD2
VDD1
VSS

VDD3

COM1

VDD2
VDD1
VSS

VDD3

VDD2
VDD1
VSS

VDD3

VDD2
VDD1
VSS

VDD3

VDD2
VDD1
VSS

VDD3

LCD driver
outputs for all
seg. on COM0,1,2
sides being unlit

LCD driver
outputs for only
seg. on COM0
side being lit

LCD driver
outputs for only
seg. on COM1
side being lit

VDD2
VDD1
VSS

VDD3

LCD driver
outputs for seg.
on COM0,2
sides being lit

VDD2
VDD1
VSS

VDD3

VDD2
VDD1
VSS

VDD3

LCD driver
outputs for seg.
on COM1,2
sides being lit

LCD driver
outputs for seg.
on COM0,1,2
sides being lit

W741L250

- 30 -

1/3 Bias 1/4 Duty Normal Lighting System, continued

VDD2
VDD1
VSS

VDD3

VDD2
VDD1
VSS

VDD3

LCD driver
outputs for
seg. on COM1
COM2 sides
being lit

LCD driver
outputs for
seg. on COM0
COM2,3 sides
being lit

VDD2
VDD1
VSS

VDD3

LCD driver
outputs for
seg. on COM0
COM1,2,3 sides
being lit

The power connections for each LCD driving mode, which are determined by a mask option, are
shown below.

DH1

DH2

VSS

VDD1

VDD

VDD2

VDD3

VDD

C
H
I
P

Static LCD Configuration

VDD1 = VDD2 = VDD3 = VDD(1.5 V)

DH1

DH2

VSS

VDD1

VDD

VDD2

VDD3

0.1uF

VDD

C
H
I
P

1/2 Bias LCD Configuration

VDD1 = VDD(1.5 V),
VDD2 = VDD3 = 2 VDD(3.0 V)

DH1, DH2 floating

W741L250

Publication Release Date: March 1998

- 31 -

Revision A2

LCD Configuration, continued

DH1

DH2

VSS

VDD1

VDD

VDD2

VDD3

0.1uF

VDD

C
H
I
P

1/3 Bias LCD Configuration

VDD1 = VDD(1.5 V), VDD2 =2 VDD(3.0 V), VDD3 = 3 VDD(4.5 V)

0.1uF

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNIT

Supply Voltage to Ground Potential

-0.3 to +7.0

Applied Input/Output Voltage

-0.3 to +7.0

Power Dissipation

120

Ambient Operating Temperature

0 to +70

Storage Temperature

-55 to +150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.

W741L250

- 32 -

DC CHARACTERISTICS

= 1.5V, F

OSC

. = 32.768 KHz, T

= 25

C; unless otherwise specified)

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Op. Voltage

1.2

1.8

Op. Current (Crystal type)

OP1

No load (Ext-V)

Op. Current (RC type)

OP2

No load (Ext-V)

Hold Current (Crystal type)

HM1

Hold mode
No load (Ext-V)

Hold Current (RC type)

HM2

Hold mode
No load (Ext-V)

Stop Current (Crystal type)

SM1

Stop mode
No load (Ext-V)

0.1

Stop Current (RC type)

SM2

Stop mode
No load (Ext-V)

0.1

Input Low Voltage

0.3 V

Input High Voltage

0.7 V

MFP Output Low Voltage

= 0.9mA

0.3

MFP Output High Voltage

= -0.75mA

1.2

Port RA, RB Output Low
Voltage

ABL

= 1.0mA

0.3

Port RA, RB Output High
Voltage

ABH

= -0.5mA

1.2

LCD Supply Current

LCD

All Seg. On

SEG0

SEG23 Sink Current

(work as LCD output pins)

= 0.05V

LCD

= 0.0V

SEG0

SEG23 Drive Current

(work as LCD output pins)

= 4.45V

LCD

= 4.5V

1.5

SEG0

SEG23 Output Low

Voltage (work as DC output
pins)

= 150

0.15

SEG0

SEG23 Output High

Voltage (work as DC output
pins)

= -1.0

1.35

Port RE Sink Current

= 0.3V

Port RE Source Current

= 1.2V

0.35

Input Port Pull-up Resistor

Port RC, RD

500

1000

1500

INT

Pull-up Resistor

INT

500

1000

1500

RES

Pull-up Resistor

RES

200

500

800

W741L250

Publication Release Date: March 1998

- 33 -

Revision A2

AC CHARACTERISTICS

= 1.5V, T

= 25

C; unless otherwise specified)

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

MAX. UNI

RC type

1000

Op. Frequency

OSC

Crystal type (Option
low-speed type only)

32.768

KHz

Oscillator Start-up Time

=1.2 V, F

OSC

32.768 KHz

Instruction Cycle Time

One machine cycle

4/F

OSC

Reset Active Width

RAW

OSC

= 32.768 KHz

Interrupt Active Width

IAW

OSC

= 32.768 KHz

PAD ASSIGNMENT & POSITIONS

51 50 49 48 47

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

53 52

55 54

57 56

59 58

(0,0)

2820 m

3030 m

Note: The chip substrate must be connected to system ground (V

W741L250

- 34 -

Pad Assignment & Positions, continued

PAD NO.

PAD NAME

PAD NO.

PAD NAME

RD2

-912.10

1297.50

COM0

-1209.00

-414.00

RD3

-1209.00

756.00

SEG0

-1209.00

-544.00

RE0

-1209.00

626.00

SEG1

-1209.00

-674.00

RE1

-1209.00

496.00

SEG2

-1209.00

-804.00

RE2

-1209.00

366.00

SEG3

-1209.00

-934.00

RE3

-1209.00

236.00

SEG4

-1209.00

-1064.00

-1209.00

106.00

SEG5

-912.10

-1314.00

COM3

-1209.00

-24.00

SEG6

-782.10

-1314.00

COM2

-1209.00

-154.00

SEG7

-652.10

-1314.00

COM1

-1209.00

-284.00

SEG8

-522.10

-1314.00

SEG9

-392.10

-1314.00

1201.50

106.00

SEG10

-262.10

-1314.00

OUT

1201.50

236.00

SEG11

-132.10

-1314.00

1201.50

366.00

SEG12

-2.1

-1314.00

RES

1201.50

496.00

SEG13

127.90

-1314.00

INT

1201.50

626.00

SEG14

257.90

-1314.00

MFP

1201.50

756.00

SEG15

387.90

-1314.00

RA0

907.90

1297.50

SEG16

517.90

-1314.00

RA1

777.90

1297.50

SEG17

647.90

-1314.00

RA2

647.90

1297.50

SEG18

777.90

-1314.00

RA3

517.90

1297.50

SEG19

907.90

-1314.00

RB0

387.90

1297.50

SEG20

1201.50

-1064.00

RB1

257.90

1297.50

SEG21

1201.50

-934.00

RB2

127.90

1297.50

SEG22

1201.50

-804.00

RB3

-2.10

1297.50

SEG23

1201.50

-674.00

RC0

-132.10

1297.50

DD3

1201.50

-544.00

RC1

-262.10

1297.50

DD2

1201.50

-414.00

RC2

-392.10

1297.50

DD1

1201.50

-284.00

RC3

-522.10

1297.50

DH2

1201.50

-154.00

RD0

-652.10

1297.50

DH1

1201.50

-24.00

RD1

-782.10

1297.50

W741L250

- 36 -

INSTRUCTION SET TABLE

Symbol Description

ACC:

Accumulator

ACC.n:

Accumulator bit n

WR:

Working Register

PAGE:

Page Register

MR1:

Mode Register 1

PM0:

Port Mode 0

PM1:

Port Mode 1

PM2:

Port Mode 2

PSR0:

Port Status Register 0

Memory (RAM) of address R

LCDR:

LCD data RAM of address LDR

R.n:

Memory bit n of address R

Constant parameter

Branch or jump address

CF:

Carry Flag

ZF:

Zero Flag

PC:

Program Counter

TM0:

Timer 0

TM1:

Timer 1

IEF.n:

Interrupt Enable Flag n

HCF.n:

HOLD mode release Condition Flag n

HEF.n:

HOLD mode release Enable Flag n

SEF.n:

STOP mode wake-up Enable Flag n

PEF.n:

Port Enable Flag n

EVFn:

Event Flag n

BF:

Backup Flag

! =:

Not equal

AND

W741L250

Publication Release Date: March 1998

- 37 -

Revision A2

Symbol Description, continued

EX:

Exclusive OR

Transfer direction, result

[PAGE*10H+()]: Contents of address PAGE(bit2, bit1, bit0)*10H+()

[P()]:

Contents of port P()

INSTRUCTION SET TABLE 1

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

Arithmetic

ADD

R, ACC

ACC

(R) + (ACC)

ZF, CF

ADD

WR, #I

ACC

(WR) + I

ZF, CF

ADDR

R, ACC

ACC, R

(R) + (ACC)

ZF, CF

ADDR

WR, #I

ACC, WR

(WR) + I

ZF, CF

ADC

R, ACC

ACC

(R) + (ACC) + (CF)

ZF, CF

ADC

WR, #I

ACC

(WR) + I + (CF)

ZF, CF

ADCR

R, ACC

ACC, R

(R) + (ACC) + (CF)

ZF, CF

ADCR

WR, #I

ACC, WR

(WR) + I + (CF)

ZF, CF

ADU

R, ACC

ACC

(R) + (ACC)

ADU

WR, #I

ACC

(WR) + I

ADUR

R, ACC

ACC, R

(R) + (ACC)

ADUR

WR, #I

ACC, W R

(WR) + I

SUB

R, ACC

ACC

(R) - (ACC)

ZF, CF

SUB

WR, #I

ACC

(WR) - I

ZF, CF

SUBR

R, ACC

ACC, R

(R) - (ACC)

ZF, CF

SUBR

WR, #I

ACC, WR

(WR) - I

ZF, CF

SBC

R, ACC

ACC

(R) - (ACC) - (CF)

ZF, CF

SBC

WR, #I

ACC

(WR) - I - (CF)

ZF, CF

SBCR

R, ACC

ACC, R

(R) - (ACC) - (CF)

ZF, CF

SBCR

WR, #I

ACC, WR

(WR) - I - (CF)

ZF, CF

INC

ACC, R

(R) + 1

ZF, CF

DEC

ACC, R

(R) - 1

ZF, CF

W741L250

- 38 -

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

Logic Operations

ANL

R, ACC

ACC

(R) & (ACC)

ANL

WR, #I

ACC

(WR) & I

ANLR

R, ACC

ACC, R

(R) & (ACC)

ANLR

WR, R #I

ACC, WR

(WR) & I

ORL

R, ACC

ACC

(R)

(ACC)

ORL

WR, #I

ACC

(WR)

ORLR

R, ACC

ACC, R

(R)

(ACC)

ORLR

WR, #I

ACC, WR

(WR)

XRL

R, ACC

ACC

(R) EX (ACC)

XRL

WR, #I

ACC

(WR) EX I

XRLR

R, ACC

ACC, R

(R) EX (ACC)

XRLR

WR, #I

ACC, WR

(WR) EX I

Branch

JMP

PC10

PC0

L10

JB0

PC10

PC0

L10

L0; if ACC.0 = "1"

JB1

PC10

PC0

L10

L0; if ACC.1 = "1"

JB2

PC10

PC0

L10

L0; if ACC.2 = "1"

JB3

PC10

PC0

L10

L0; if ACC.3 = "1"

PC10

PC0

L10

L0; if ACC = 0

JNZ

PC10

PC0

L10

L0; if ACC ! = 0

PC10

PC0

L10

L0; if CF = "1"

JNC

PC10

PC0

L10

L0; if CF ! = "1"

DSKZ

ACC, R

(R) - 1; skip if ACC = 0

ZF, CF

DSKNZ

ACC, R

(R) - 1; skip if ACC ! = 0

ZF, CF

SKB0

Skip if R.0 = "1"

SKB1

Skip if R.1 = "1"

SKB2

Skip if R.2 = "1"

SKB3

Skip if R.3 = "1"

W741L250

Publication Release Date: March 1998

- 39 -

Revision A2

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

Data Move

MOV

WR, R

(R)

MOV

R, WR

(WR)

MOVA

WR, R

ACC, WR

(R)

MOVA

R, WR

ACC, R

(WR)

MOV

R, ACC

(ACC)

MOV

ACC, R

ACC

(R)

MOV

R, #I

MOV

WR, @R

[PR (bit2, bit1, bit0)

10H + (R)]

MOV

@R, WR

[PR (bit2, bit1, bit0)

10H +(R)]

MOV

TABH, R

TAB High addresss

MOV

TABL, R

TAB Low addresss

MOVC

[ TAB

10H + (ACC)]

MOVC

WR, #I

[(I6 ~ I0)

10H + (ACC)]

Input & Output

MOVA

R, RA

ACC, R

[RA]

MOVA

R, RB

ACC, R

[RB]

MOVA

R, RC

ACC, R

[RC]

MOVA

R, RD

ACC, R

[RD]

MOV

RA, R

[RA]

(R)

MOV

RB, R

[RB]

(R)

MOV

RE, R

[RT]

(R)

MOV

MFP, #I

[MFP]

Flag & Register

MOVA

R, PAGE

ACC, R

PAGE (Page Register)

MOV

PAGE, R

PAGE

(R)

MOV

PAGE, #I

PAGE

MOV

MR0, #I

MR0

MOV

MR1, #I

MR1

W741L250

- 40 -

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

MOVA

R, CF

ACC.0, R.0

MOV

CF, R

(

R.0)

MOVA

R, HCFL

ACC, R

HCF0

HCF3

MOVA

R, HCFH

ACC, R

HCF4

HCF7

CLR

PMF, #I

Clear Parameter Flag if In = 1

SET

PMF, #I

Set Parameter Flag if In = 1

MOV

PM0, #I

Port Mode 0

MOV

PM1, #I

Port Mode 1

MOV

PM2, #I

Port Mode 2

CLR

EVF, #I

Clear Event Flag if In = 1

MOV

PEF, #I

Set/Reset Port Enable Flag

MOV

IEF, #I

Set/Reset Interrupt Enable Flag

MOV

HEF, #I

Set/Reset HOLD mode release Enable Flag

MOV

SEF, #I

Set/Reset STOP mode wake-up Enable Flag
for RC port

MOVA

R, PSR0

ACC, R

Port Status Register 0

CLR

PSR0

Clear Port Status Register 0

SET

Set Carry Flag

CLR

Clear Carry Flag

CLR

DIVR0

Clear last 4 bits of Divider 0

CLR

WDT

Clear Watchdog Timer

Shift & Rotate

SHRC

ACC.n, R.n

(R.n

);

ACC.3, R.3

0; CF

R.0

ZF, CF

RRC

ACC.n, R.n

(R.n

);

ACC.3, R.3

CF; CF

R.0

ZF, CF

SHLC

ACC.n, R.n

(R.n

-1

);

ACC.0, R.0

0; CF

R.3

ZF, CF

RLC

ACC.n, R.n

(R.n

-1

);

ACC.0, R.0

CF; CF

R.3

ZF, CF

W741L250

Publication Release Date: March 1998

- 41 -

Revision A2

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

LCD

MOV

LCDR, #I

LCDR

MOV

WR, LCDR

(LCDR)

MOV

LCDR, WR

LCDR

(WR)

MOV

LCDR, ACC

LCDR

(ACC)

MOV

LCDM, #I

Select LCD output mode type

LCDON

LCD ON

LCDOFF

LCD OFF

Timer

MOV

TM0H, R

Timer 0 High register

MOV

TM0L, R

Timer 0 Low register

MOV

TM0, #I

Timer 0 set

MOV

TM1H, R

Timer 1 High register

MOV

TM1L, R

Timer 1 Low register

MOV

TM1, #I

Timer 1 set

Subroutine

CALL

STACK

(PC)+1;

PC10

PC0

L10

RTN

(PC)

STACK

Other

HOLD

Enter Hold mode

STOP

Enter Stop mode

NOP

No Operation

INT

Enable Interrupt Function

DIS

INT

Disable Interrupt Function

W741L250

- 42 -

INSTRUCTION SET TABLE 2

ADC R, ACC

Add R to ACC with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) + (ACC) + (CF)

The contents of the data memory location addressed by R6 to R0, ACC,
and CF are binary added and the result is loaded into the ACC.

CF & ZF

ADC WR, #I

Add immediate data to WR with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) + I + (CF)

The contents of the Working Register (WR), I, and CF are binary added
and the result is loaded into the ACC.

CF & ZF

ADCR R, ACC

Add R to ACC with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) + (ACC) + (CF)

The contents of the data memory location addressed by R6 to R0, ACC,
and CF are binary added and the result is placed in the ACC and the data
memory.

CF & ZF

W741L250

Publication Release Date: March 1998

- 43 -

Revision A2

Instruction Set Table 2, continued

ADCR WR, #I

Add immediate data to WR with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) + I + (CF)

The contents of the Working Register (WR), I, CF are binary added and the
result is placed in the ACC and the WR.

CF & ZF

ADD R, ACC

Add R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is loaded into the ACC.

CF & ZF

ADD WR, #I

Add immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is loaded into the ACC.

CF & ZF

W741L250

- 44 -

Instruction Set Table 2, continued

ADDR R, ACC

Add R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is placed in the ACC and the data memory.

CF & ZF

ADDR WR, #I

Add immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is placed in the ACC and the WR.

CF & ZF

ADU R, ACC

Add R to ACC and Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is loaded into the ACC.

W741L250

Publication Release Date: March 1998

- 45 -

Revision A2

Instruction Set Table 2, continued

ADU WR, #I

Add immediate data to WR and Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is loaded into the ACC.

ADUR R, ACC

Add R to ACC and Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) + (ACC)

The contents of the data memory location addressed by R6 to R0 and ACC
are binary added and the result is placed in the ACC and the data memory.

ADUR WR, #I

Add immediate data to WR and Carry Flag unchanged

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) + I

The contents of the Working Register (WR) and the immediate data I are
binary added and the result is placed in the WR and the ACC.

W741L250

- 46 -

Instruction Set Table 2, continued

ANL R, ACC

And R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) & (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ANDed and the result is loaded into the ACC.

ANL WR, #I

And immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) & I

The contents of the Working Register (WR) and the immediate data I are
ANDed and the result is loaded into the ACC.

ANLR R, ACC

And R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) & (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ANDed and the result is placed in the data memory and the ACC.

W741L250

Publication Release Date: March 1998

- 47 -

Revision A2

Instruction Set Table 2, continued

ANLR WR, #I

And immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) & I

The contents of the Working Register (WR) and the immediate data I are
ANDed and the result is placed in the WR and the ACC.

CALL L

Call subroutine

Machine Code:

Machine Cycle:

Operation:

Description:

L10

STACK

(PC)+1;

PC10

PC0

L10

The next program counter (PC10 to PC0) is saved in the STACK and then
the direct address (L10 to L0) is loaded into the program counter.

A subroutine is called.

CLR CF

Clear CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

Clear CF

Clear Carry Flag to 0.

W741L250

- 48 -

Instruction Set Table 2, continued

CLR DIVR0

Reset the last 4 bits of the DIVideR0

Machine Code:

Machine Cycle:

Operation:

Description:

Reset the last 4 bits of Divider 0

When this instruction is executed, the last 4 bits of Divider 0 (14 bits) are
reset.

CLR EVF, #I

Clear EVent Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Clear event flag

The condition corresponding to the data specified by I7 to I0 is controlled.

I0 to I8

Mode after execution of instruction

I0 = 1

EVF0 caused by overflow from Divider 0 is reset.

I1 = 1

I2 = 1

I3 = 1

I7 = 1

EVF1 caused by underflow from Timer 0 is reset.

EVF2 caused by signal change on port RC is reset.

EVF4 caused by falling edge signal on the INT pin is reset.

I4 = 1

Reserved

I5, I6

Reserved

EVF7 caused by underflow from Timer 1 is reset.

W741L250

Publication Release Date: March 1998

- 49 -

Revision A2

Instruction Set Table 2, continued

CLR PMF, #I

Clear ParaMeter Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Clear Parameter Flag

Description of each flag:

I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/1024.

CLR PSR0

Clear Port Status Register 0 (RC port signal change flag)

Machine Code:

Machine Cycle:

Operation:

Description:

Clear Port Status Register 0 (RC port signal change flag)

When this instruction is executed, the RC port signal change flag (PSR0) is
cleared.

CLR WDT

Reset the last 4 bits of the WatchDog Timer

Machine Code:

Machine Cycle:

Operation:

Description:

Reset the last 4 bits of the watchdog timer

When this instruction is executed, the last 4 bits of the watchdog timer are
reset.

W741L250

- 50 -

Instruction Set Table 2, continued

DEC R

Decrement R content

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) - 1

Decrement the data memory content and load result into the ACC and the
data memory.

CF & ZF

DIS INT

Disable interrupt function

Machine Code:

Machine Cycle:

Operation:

Description:

Disable interrupt function

Interrupt function is inhibited by executing this instruction.

DSKNZ R

Decrement R content then skip if ACC ! = 0

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) - 1;

(PC) + 2 if ACC ! = 0

Decrement the data memory content and load result into the ACC and the
data memory. If ACC ! = 0, the program counter is incremented by 2 and
produces a skip.

CF & ZF

W741L250

Publication Release Date: March 1998

- 51 -

Revision A2

Instruction Set Table 2, continued

DSKZ R

Decrement R content then skip if

ACC is zero

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) - 1;

(PC) + 2 if ACC = 0

Decrement the data memory content and load result into the ACC and the
data memory. If ACC = 0, the program counter is incremented by 2 and
produces a skip.

CF & ZF

EN INT

Enable interrupt function

Machine Code:

Machine Cycle:

Operation:

Description:

Enable interrupt function

This instruction enables the interrupt function.

HOLD

Enter the HOLD mode

Machine Code:

Machine Cycle:

Operation:

Description:

Enter the HOLD mode

The following two conditions cause the HOLD mode to be released.

(1) An interrupt is accepted.

(2) The HOLD release condition specified by the HEF is met.

In HOLD mode, when an interrupt is accepted the HOLD mode will be
released and the interrupt service routine will be executed. After
completing the interrupt service routine by executing the RTN instruction,
the

C will enter HOLD mode again.

W741L250

- 52 -

Instruction Set Table 2, continued

INC R

Increment R content

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

R1 R0

ACC, R

(R) + 1

Increment the data memory content and load the result into the ACC and
the data memory.

CF & ZF

JB0 L

Jump when bit 0 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC.0 = "1"

If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC
is "0," the program counter (PC) is incremented.

JB1 L

Jump when bit 1 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC.1 = "1"

If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC
is "0," the program counter (PC) is incremented.

W741L250

Publication Release Date: March 1998

- 53 -

Revision A2

Instruction Set Table 2, continued

JB2 L

Jump when bit 2 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC.2 = "1"

If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC
is "0," the program counter (PC) is incremented.

JB3 L

Jump when bit 3 of ACC is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC.3 = "1"

If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC
is "0," the program counter (PC) is incremented.

JC L

Jump when CF is "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if CF = "1"

If CF is "1," PC10 to PC0 of the program counter are replaced with the data
specified by L10 to L0 and a jump occurs. If the CF is "0," the program
counter (PC) is incremented.

W741L250

- 54 -

Instruction Set Table 2, continued

JMP L

Jump absolutely

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

PC10 to PC0 of the program counter are replaced with the data specified
by L10 to L0 and an unconditional jump occurs.

JNC L

Jump when CF is not "1"

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if CF = "0"

If CF is "0," PC10 to PC0 of the program counter are replaced with the data
specified by L10 to L0 and a jump occurs. If CF is "1," the program counter
(PC) is incremented.

JNZ L

Jump when ACC is not zero

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC ! = 0

If the ACC is not zero, PC10 to PC0 of the program counter are replaced
with the data specified by L10 to L0 and a jump occurs. If the ACC is zero,
the program counter (PC) is incremented.

W741L250

Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

JZ L

Jump when ACC is zero

Machine Code:

Machine Cycle:

Operation:

Description:

L10

PC10

PC0

L10

L0; if ACC = 0

If the ACC is zero, PC10 to PC0 of the program counter are replaced with
the data specified by L10 to L0 and a jump occurs. If the ACC is not zero,
the program counter (PC) is incremented.

LCDON

LCD ON

Machine Code:

Machine Cycle:

Operation:

Description:

LCD ON

Turn on LCD display.

LCDOFF

LCD OFF

Machine Code:

Machine Cycle:

Operation:

Description:

LCD OFF

Turn off LCD display.

W741L250

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Instruction Set Table 2, continued

MOV ACC, R

Move R content to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the ACC.

MOV CF, R

Move R.0 content to CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

(R.0)

The bit 0 content of the data memory location addressed by R6 to R0 is
loaded into CF.

W741L250

Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

MOV HEF, #I

Set/Reset Hold mode release Enable Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Hold mode release enable flag control

I0 to I7

Operation

I0 = 1

I1 = 1

I2 = 1

I3 = 1

I4 = 1

I5 & I6

HEF2 is set so that signal change on port RC will cause the
HOLD mode to be released.

HEF0 is set so that overflow from Divider 0 will cause the

HOLD mode to be released.

HEF1 is set so that underflow from Timer 0 will cause the

HOLD mode to be released.

Reserved

I7 = 1

will cause the HOLD mode to be released.

HEF4 is set so that the falling edge signal on the INT pin

Reserved

HEF7 is set so that underflow from Timer 1 will cause the

HOLD mode to be released.

W741L250

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Instruction Set Table 2, continued

MOV IEF, #I

Set/Reset Interrupt Enable Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Interrupt Enable flag Control

The interrupt enable flag corresponding to the data specified by I7

I0 is

controlled:

I0 to I5

Operation

I0 = 1

I1 = 1

I2 = 1

I3 = 1

I4 = 1

I5 & I6

The IEF0 is set so that interrupt 0 (overflow from Divider 0)
is accepted.

The IEF1 is set so that interrupt 1 (underflow from Timer 0)
is accepted.

The IEF2 is set so that interrupt 2 (signal change on port
RC) is accepted.

The IEF4 is set so that interrupt 4 (falling edge signal on

Reserved

I7 = 1

The IEF7 is set so that interrupt 7 (underflow from Timer 1)
is accepted.

the INT pin) is accepted.

MOV LCDM, #I

Select LCD output Mode type

Machine Code:

Machine Cycle:

Operation:

Description:

Select LCD output mode type

When LCD output pins are set to DC output mode, user can select CMOS
or NMOS as output type.

I5 = 0 => CMOS type; I0

I5 = 1 => NMOS type

W741L250

Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

MOV LCDR, ACC

Move ACC content to LCDR

Machine Code:

Machine Cycle:

Operation:

Description:

LCDR

(ACC)

The contents of the ACC are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

MOV LCDR, WR

Load WR content to LCDR

Machine Code:

Machine Cycle:

Operation:

Description:

W3 W2 W1 W0

LCDR

(WR)

The contents of the WR are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

MOV LCDR, #I

Load immediate data to LCDR

Machine Code:

Machine Cycle:

Operation:

Description:

LCDR

The immediate data I are loaded to the LCD data RAM (LCDR) location
addressed by D4 to D0.

W741L250

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Instruction Set Table 2, continued

MOV MFP, #I

Modulation Frequency Pulse generator

Machine Code:

Machine Cycle:

Operation:

Description:

[MFP]

If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at
the MFP output pin (MFP). The relation between the waveform and
immediate data I areas follows:

I5~I0

I0 = 1

I1 = 1

I2 = 1

I3 = 1

I4 = 1

I5 = 1

Signal

Fosc

256

Fosc

512

Fosc
4096

Fosc

8192

Fosc

16384

Fosc

32768

Signal

Low

High

Fosc/16

Fosc/8

MOV MR0, #I

Load immediate data to Mode Register 0 (MR0)

Machine Code:

Machine Cycle:

Operation:

Description:

MR0

The immediate data I are loaded to the MR0.

MR0 bits description:

bit 0

= 0 Timer 0 stop down-counting
= 1 Timer 0 start down-counting

= 0 The fundamental frequency of Timer 0 is Fosc/4

= 1 The fundamental frequency of Timer 0 is Fosc/1024

Reserved

bit 1

bit 2

bit 3

Reserved

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Revision A2

Instruction Set Table 2, continued

MOV MR1, #I

Load immediate data to Mode Register 1 (MR1)

Machine Code:

Machine Cycle:

Operation:

Description:

MR1

The immediate data I are loaded to the MR1.

MR1 bit description:

bit0

= 1 The internal fundamental frequency of Timer 1 is Fosc/64

= 0 The internal fundamental frequency of Timer 1 is Fosc

= 0 The fundamental frequency source of Timer 1 is
internal clock
= 1 The fundamental frequency source of Timer 1 is
external clock via RC.0 input pin

= 0 The specified waveform of the MFP generator is
delivered at the MFP output pin

= 1 The specified frequency of the Timer 1 is delivered at
the MFP output pin

bit1

bit2

bit3

= 0 Timer 1 stop down-counting
= 1 Timer 1 start down-counting

MOV PAGE, #I

Load immediate data to Page Register

Machine Code:

Machine Cycle:

Operation:

Description:

Page Register

The immediate data I are loaded to the PR.

Bit 3 is reserved.

W741L250

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Instruction Set Table 2, continued

Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits:

bit1

bit0

= Page 0 (00H to 0FH)

= Page 1 (10H to 1FH)

= Page 2 (20H to 2FH)

= Page 3 (30H to 3FH)

bit2

= Page 4 (40H to 4FH)

= Page 5 (50H to 5FH)

= Page 6 (60H to 6FH)

= Page 7 (70H to 7FH)

MOV PEF, #I

Set/Reset Port Enable Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Port enable flag control

The data specified by I can cause HOLD mode to be released or an
interrupt to occur. The signal change on port RC is specified.

I0 to I3

I0 = 1

I1 = 1

I2 = 1

I3 = 1

Signal change at port RC

RC0

RC1

RC2

RC3

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Revision A2

Instruction Set Table 2, continued

MOV PM0, #I

Set/Reset Port Mode 0 register

Machine Code:

Machine Cycle:

Operation:

Description:

Set/Reset Port mode 0 register

I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type.

I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type.

I2 = 0: RC port pull-high resistor is disabled;

I2 = 1: RC port pull-high resistor is enabled.

I3 = 0: RD port pull-high resistor is disabled;

I3 = 1: RD port pull-high resistor is enabled.

MOV PM1, #I

RA port independent Input/Output control

Machine Code:

Machine Cycle:

Operation:

Description:

Input/output control of 4 RA port pins is independent.

I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin.

I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin.

I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin.

I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin.

Default condition RA port is input mode (PM1 = 1111B).

W741L250

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Instruction Set Table 2, continued

MOV PM2, #I

RB port independent Input/Output control

Machine Code:

Machine Cycle:

Operation:

Description:

Input/output control of 4 RB port pins is independent.

I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin.
I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin.
I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin.
I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin.

Default condition RB port is input mode (PM2 = 1111B).

MOV R, ACC

Move ACC content to R

Machine Code:

Machine Cycle:

Operation:

Description:

(ACC)

The contents of the ACC are loaded to the data memory location
addressed by R6 to R0.

MOVA R, RA

Input RA port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC , R

[RA]

The data on port RA are loaded into the data memory location addressed
by R6 to R0 and the ACC.

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Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

MOVA R, RB

Input RB port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC , R

[RB]

The data on port RB are loaded into the data memory location addressed
by R6 to R0 and the ACC.

MOVA R, RC

Input RC port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC , R

[RC]

The input data on input port RC are loaded into the data memory location
addressed by R6 to R0 and the ACC.

MOVA R, RD

Input RD port data to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC , R

[RD]

The input data on input port RD are loaded into the data memory location
addressed by R6 to R0 and the ACC.

W741L250

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Instruction Set Table 2, continued

MOV R, WR

Move WR content to R

Machine Code:

Machine Cycle:

Operation:

Description:

W0 R6

(WR)

The contents of the WR are loaded to the data memory location addressed
by R6 to R0.

MOV R, #I

Load immediate data to R

Machine Code:

Machine Cycle:

Operation:

Description:

The immediate data I are loaded to the data memory location addressed by
R6 to R0.

MOV RA, R

Output R content to RA port

Machine Code:

Machine Cycle:

Operation:

Description:

[RA]

(R)

The data in the data memory location addressed by R6 to R0 are output to
port RA.

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Revision A2

Instruction Set Table 2, continued

MOV RB, R

Output R content to RB port

Machine Code:

Machine Cycle:

Operation:

Description:

[RB]

(R)

The contents of the data memory location addressed by R6 to R0 are
output to port RB.

MOV RE, R

Output R content to port RE

Machine Code:

Machine Cycle:

Operation:

Description:

[RE]

(R)

The contents of the data memory location addressed by R6 to R0 are
output to port RE.

MOV SEF, #I

Set/Reset STOP mode wake-up Enable Flag for port RC

Machine Code:

Machine Cycle:

Operation:

Description:

Set/reset STOP mode wake-up enable flag for port RC

The data specified by I cause a wake-up from the STOP mode. The falling-
edge signal on port RC can be specified independently.

I0 to I3

I0 = 1

I1 = 1

I2 = 1

I3 = 1

Falling edge signal on port RC

RC0

RC1

RC2

RC3

W741L250

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Instruction Set Table 2, continued

MOV TM0, #I

Timer 0 set

Machine Code:

Machine Cycle:

Operation:

Description:

Timer 0 set

The data specified by I7 to I0 is loaded to the Timer 0 to start the timer.

MOV TM0L, R

Move R contents to TM0L

Machine Code:

Machine Cycle:

Operation:

Description:

TM0L

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM0L.

MOV TM0H, R

Move R contents to TM0H

Machine code:

Machine Cycle:

Operation:

Description:

TM0H

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM0H.

MOV TM1, #I

Timer 1 set

Machine Code:

Machine Cycle:

Operation:

Description:

Timer 1 set

The data specified by I7 to I0 is loaded to the Timer 1 to start the timer.

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Revision A2

Instruction Set Table 2, continued

MOV TM1L, R

Move R contents to TM1L

Machine Code:

Machine Cycle:

Operation:

Description:

TM1L

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM1L.

MOV TM1H, R

Move R contents to TM1H

Machine code:

Machine Cycle:

Operation:

Description:

TM1H

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded into the TM1H.

MOV WR, LCDR

Load LCDR content to WR

Machine Code:

Machine Cycle:

Operation:

Description:

W3 W2 W1 W0

(LCDR)

The contents of the LCD data RAM location addressed by D4 to D0 are
loaded to the WR.

MOV WR, R

Move R content to WR

Machine Code:

Machine Cycle:

Operation:

Description:

W0 R6

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the WR.

W741L250

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Instruction Set Table 2, continued

MOV WR, @R

Indirect load from R to WR

Machine Code:

Machine Cycle:

Operation:

Description:

W0 R6

[PR (bit2, bit1, bit0)

10H + (R)]

The data memory contents of address [PR (bit2, bit1, bit0)

10H + (R)] are

loaded to the WR.

MOV @R, WR

Indirect load from WR to R

Machine Code:

Machine Cycle:

Operation:

Description:

W0 R6

[PR (bit2, bit1, bit0)

10H + (R)]

The contents of the WR are loaded to the data memory location addressed
by [PR (bit2, bit1, bit0)

10H + (R)].

MOV PAGE, R

Move R content to Page Register

Machine Code:

Machine Cycle:

Operation:

Description:

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the PR.

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Revision A2

Instruction Set Table 2, continued

MOVA R, CF

Move CF content to ACC.0 & R.0

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC.0, R.0

(CF)

The content of CF is loaded to bit 0 of the data memory location addressed
by R6 to R0 and the ACC. The other bits of the data memory and ACC are
reset to "0."

MOVA R, HCFH

Move HCF4

7 to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

HCF4

The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data
memory location addressed by R6 to R0 and the ACC. The ACC contents
and the meaning of the bits after execution of this instruction are as
follows:

Bit 0

Bit 1

Bit 3

Bit 2

HCF4: "1" when the HOLD mode is released by a falling signal on the INT pin.

Reserved.

HCF5: "1" when the HOLD mode is released by underflow from Timer 1.

Reserved.

MOVA R, HCFL

Move HCF0

3 to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

ACC, R

HCF0

The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data
memory location addressed by R6 to R0 and the ACC. The ACC contents
and the meaning of the bits after execution of this instruction are as
follows:

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Instruction Set Table 2, continued

Flag Affected:

Bit 0

Bit 1

Bit 3

Bit 2

HCF0: "1" when the HOLD mode is released by
overflow from Divider 0.

HCF2: "1" when the HOLD mode is released by
a signal change on port RC.

Reserved

HCF1: "1" when the HOLD mode is released by
underflow from Timer 0.

MOVA R, PAGE

Move Page Register content to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC , R

(Page Register)

The contents of the Page Register (PR) are loaded to the data memory
location addressed by R6 to R0 and the ACC.

MOVA R, PSR0

Move Port Status Register 0 content to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

RC port signal change flag (PSR0)

The contents of the RC port signal change flag (PSR0) are loaded to the
data memory location addressed by R6 to R0 and the ACC. When the
signal changes on any pin of the RC port, the corresponding signal change
flag should be set to 1. Otherwise, it should be 0.

W741L250

Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

MOVA R, WR

Move WR content to ACC & R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W0 R6

ACC, R

(WR)

The contents of the WR are loaded to the ACC and the data memory
location addressed by R6 to R0.

MOVA WR, R

Move R content to ACC & WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W0 R6

ACC, WR

(R)

The contents of the data memory location addressed by R6 to R0 are
loaded to the WR and the ACC.

MOVC R

Move look-up table ROM addressed by TABL and TABH to R

Machine code:

Machine Cycle:

Operation:

Description:

[((TABH)

100H + (TABL))

10H + ACC ]

The contents of the look-up table ROM location addressed by TABH, TABL
and ACC are loaded to R.

W741L250

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Instruction Set Table 2, continued

MOVC WR, #I

Move look-up table ROM addressed by #I and ACC to WR

Machine code:

Machine Cycle:

Operation:

Description:

W3 W2 W1

W0 I6

[(I6 ~ I0)

10H + (ACC)]

The contents of the look-up table ROM location addressed by I6 to I0 and
the ACC are loaded to R.

NOP

No Operation

Machine Code:

Machine Cycle:

Operation:

No Operation

ORL R, ACC

OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R)

(ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ORed and the result is loaded into the ACC.

ORL WR , #I

OR immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR)

The contents of the Working Register (WR) and the immediate data I are
ORed and the result is loaded into the ACC.

W741L250

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Revision A2

Instruction Set Table 2, continued

ORLR R, ACC

OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R)

(ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are ORed and the result is placed in the data memory and the ACC.

ORLR WR , #I

OR immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR)

The contents of the Working Register (WR) and the immediate data I are
ORed and the result is placed in the WR and the ACC.

RLC R

Rotate Left R with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC.n, R.n

R.n-1; ACC.0, R.0

CF; CF

R.3

The contents of the ACC and the data memory location addressed by R6 to
R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0
(LSB). The same contents are loaded into the ACC.

CF & ZF

W741L250

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Instruction Set Table 2, continued

RRC R

Rotate Right R with CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC.n, R.n

R.n+1; ACC.3, R.3

CF; CF

R.0

The contents of the ACC and the data memory location addressed by R6 to
R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into
bit 3 (MSB). The same contents are loaded into the ACC.

CF & ZF

RTN

Return from subroutine

Machine Code:

Machine Cycle:

Operation:

Description:

(PC)

STACK

The program counter (PC10 to PC0) is restored from the stack. A return
from a subroutine occurs.

SBC R, ACC

Subtract ACC from R with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) - (ACC) - (CF)

The contents of the ACC and CF are binary subtracted from the contents of
the data memory location addressed by R6 to R0 and the result is loaded
into the ACC.

CF & ZF

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Revision A2

Instruction Set Table 2, continued

SBC WR, #I

Subtract immediate data from WR with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) - I - (CF)

The immediate data I and CF are binary subtracted from the contents of
the WR and the result is loaded into the ACC.

CF & ZF

SBCR R, ACC

Subtract ACC from R with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) - (ACC) - (CF)

The contents of the ACC and CF are binary subtracted from the contents of
the data memory location addressed by R6 to R0 and the result is placed in
the ACC and the data memory.

CF & ZF

SBCR WR, #I

Subtract immediate data from WR with Borrow

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, R

(WR) - I - (CF)

The immediate data I and CF are binary subtracted from the contents of
the WR and the result is placed in the ACC and the WR.

CF & ZF

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Instruction Set Table 2, continued

SET CF

Set CF

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

Set CF

Set Carry Flag to 1.

SET PMF, #I

Set ParaMeter Flag

Machine Code:

Machine Cycle:

Operation:

Description:

Set Parameter Flag

Description of each flag:

I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/16384.

SHLC R

SHift Left R with CF and LSB = 0

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC.n, R.n

R.n-1; ACC.0, R.0

0; CF

R.3

The contents of the ACC and the data memory location addressed by R6 to
R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is
replaced with "0." The same contents are loaded into the ACC.

CF & ZF

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Revision A2

Instruction Set Table 2, continued

SHRC R

SHift Right R with CF and MSB = 0

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC.n, R.n

R.n+1; ACC.3, R.3

0; CF

R.0

The contents of the ACC and the data memory location addressed by R6 to
R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is
replaced with "0." The same contents are loaded into the ACC.

CF & ZF

SKB0 R

If bit 0 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

(PC) + 2; if R.0 = "1"

If bit 0 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is
incremented.

SKB1 R

If bit 1 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

(PC) + 2; if R.1 = "1"

If bit 1 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is
incremented.

W741L250

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Instruction Set Table 2, continued

SKB2 R

If bit 2 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

(PC) + 2; if R.2 = "1"

If bit 2 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is
incremented.

SKB3 R

If bit 3 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

Operation:

Description:

(PC) + 2; if R.3 = "1"

If bit 3 of R is equal to 1, the program counter is incremented by 2 and a
skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is
incremented.

STOP

Enter the STOP mode

Machine Code:

Machine Cycle:

Operation:

Description:

STOP oscillator

Device enters STOP mode. When signal on the

INT

pin goes low or the

falling edge signal of RC port is accepted, the

C will wake up and execute

the next instruction.

W741L250

Publication Release Date: March 1998

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Revision A2

Instruction Set Table 2, continued

SUB R, ACC

Subtract ACC from R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) - (ACC)

The contents of the ACC are binary subtracted from the contents of the
data memory location addressed by R6 to R0 and the result is loaded into
the ACC.

CF & ZF

SUB WR , #I

Subtract immediate data from WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) - I

The immediate data I are binary subtracted from the contents of the WR
and the result is loaded into the ACC.

CF & ZF

SUBR R, ACC

Subtract ACC from R

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) - (ACC)

The contents of the ACC are binary subtracted from the contents of the
data memory location addressed by R6 to R0 and the result is placed in the
ACC and the data memory.

CF & ZF

W741L250

- 82 -

Instruction Set Table 2, continued

SUBR WR , #I

Subtract immediate data from WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) - I

The immediate data I are binary subtracted from the contents of the WR
and the result is placed in the ACC and the WR.

CF & ZF

XRL R, ACC

Exclusive OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC

(R) EX (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are exclusive-ORed and the result is loaded into the ACC.

XRL WR, #I

Exclusive OR immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC

(WR) EX I

The contents of the Working Register (WR) and the immediate data I are
exclusive-ORed and the result is loaded into the ACC.

W741L250

Publication Release Date: March 1998

- 83 -

Revision A2

Instruction Set Table 2, continued

XRLR R, ACC

Exclusive OR R to ACC

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

ACC, R

(R) EX (ACC)

The contents of the data memory location addressed by R6 to R0 and the
ACC are exclusive-ORed and the result is placed in the data memory and
the ACC.

XRLR WR, #I

Exclusive OR immediate data to WR

Machine Code:

Machine Cycle:

Operation:

Description:

Flag Affected:

W3 W2 W1 W0

ACC, WR

(WR) EX I

The contents of the Working Register (WR) and the immediate data I are
exclusive-ORed and the result is placed in the WR and the ACC.

W741L250

- 84 -

PACKAGE DIMENSION

64-Lead QFP (14

2.75mm footprint 4.8mm)

Seating Plane

See Detail F

Detail F

0.10

0.004

2.40

1.40

19.10

1.20

18.80

1.00

18.49

0.094

0.055

0.752

0.047

0.740

0.039

0.728

1.00

14.13

0.25

0.50

2.97

3.30

14.00

2.85

13.87

0.10

0.35

2.73

0.10

0.556

0.010

0.020

0.117

0.130

0.551

0.112

0.039

0.546

0.004

0.014

0.107

0.004

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

b
c
D

0.016

0.006

0.15

0.40

0.782

0.787

0.792

19.87

20.00

20.13

0.964

0.976

0.988

24.49

24.80

25.10

0.033

0.045

0.85

1.15

0.087

0.103

2.21

2.62

0.130

0.787

0.130

0.787

W741L250

- 86 -

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W741L250