W742C818

4-BIT MICROCONTROLLER

Publication Release Date:October 2000

- 1 - Revision A2

GENERAL DESCRIPTION ...................................................................................................... 3

FEATURES ............................................................................................................................. 3

PIN CONFIGURATION............................................................................................................ 5

W742C818 PIN DESCRIPTION............................................................................................... 6

FUNCTIONAL DESCRIPTION................................................................................................. 7

5.1

Program Counter (PC) ......................................................................................................... 7

5.2

Stack Register (STACK)....................................................................................................... 7

5.3

Program Memory (ROM)...................................................................................................... 8

5.3.1

ROM Page Register (ROMPR)...................................................................................... 8

5.3.2

ROM Addressing Mode ................................................................................................. 9

5.4

Data Memory (RAM) .......................................................................................................... 10

5.4.1

Architecture................................................................................................................. 10

5.4.2

RAM Page Register (PAGE)........................................................................................ 11

5.4.3

WR Page Register (WRP)........................................................................................... 12

5.4.4

Data Bank Register (DBKRH, DBKRL) ........................................................................ 12

5.4.5

RAM Addressing Mode................................................................................................ 13

5.5

Accumulator (ACC) ............................................................................................................ 14

5.6

Arithmetic and Logic Unit (ALU) ......................................................................................... 14

5.7

Main Oscillator ................................................................................................................... 15

5.8

Sub-Oscillator .................................................................................................................... 15

5.9

Dividers.............................................................................................................................. 15

5.10

Dual-clock operation ....................................................................................................... 16

5.11

Watchdog Timer (WDT) ................................................................................................. 17

5.12

Timer/Counter ................................................................................................................ 18

5.12.1

Timer 0 (TM0) ............................................................................................................. 18

5.12.2

Timer 1 (TM1) ............................................................................................................. 19

5.12.3

Mode Register 0 (MR0) ............................................................................................... 21

5.12.4

Mode Register 1 (MR1) ............................................................................................... 21

5.13

Interrupts ........................................................................................................................ 21

5.14

Stop Mode Operation...................................................................................................... 23

5.14.1

Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) ...................................... 23

5.15

Hold Mode Operation...................................................................................................... 23

5.15.1

Hold Mode Release Enable Flag (HEF,HEFD) ............................................................ 24

5.15.2

Interrupt Enable Flag (IEF).......................................................................................... 25

5.15.3

Port Enable Flag (PEF,P1EF) ..................................................................................... 25

5.15.4

Hold Mode Release Condition Flag (HCF,HCFD) ........................................................ 26

5.15.5

Event Flag (EVF,EVFD) .............................................................................................. 27

5.16

Reset Function ............................................................................................................... 27

5.17

Input/Output Ports RA, RB & P0 ..................................................................................... 28

5.17.1

Port Mode 0 Register (PM0)........................................................................................ 29

5.17.2

Port Mode 1 Register (PM1)........................................................................................ 29

5.17.3

Port Mode 2 Register (PM2)........................................................................................ 30

5.17.4

Port Mode 6 Register (PM6)........................................................................................ 30

5.18

Serial I/O interface.......................................................................................................... 30

5.19

Input Ports RC ................................................................................................................ 33

W742C818

Publication Release Date: October 2000

- 2 - Revision A2

5.19.1

Port Status Register 0 (PSR0) ..................................................................................... 34

5.20

Input Ports RD ................................................................................................................ 35

5.20.1

Port Status Register 1 (PSR1)..................................................................................... 36

5.21

Output Port RE & RF ...................................................................................................... 37

5.22

Input Port P1 .................................................................................................................. 37

5.23

DTMF Output Pin (DTMF) .............................................................................................. 37

5.23.1

DTMF register ............................................................................................................. 38

5.23.2

Dual Tone Control Register (DTCR) ............................................................................ 38

5.24

MFP Output Pin (MFP) ................................................................................................... 38

5.25

LCD Controller/Driver ..................................................................................................... 39

5.25.1

LCD RAM addressing method ..................................................................................... 40

5.25.2

LCD voltage and contrast adjusting ............................................................................. 41

5.25.3

LCD Power Connection ............................................................................................... 41

5.25.4

The output waveforms for the LCD driving mode......................................................... 42

ABSOLUTE MAXIMUM RATINGS......................................................................................... 44

DC CHARACTERISTICS....................................................................................................... 45

AC CHARACTERISTICS ....................................................................................................... 46

INSTRUCTION SET TABLE .................................................................................................. 47

10.

PACKAGE DIMENSIONS...................................................................................................... 56

11.

Option Code Definition: ......................................................................................................... 57

Figure 5-1 Program Memory Organization ........................................................................................ 8

Figure 5-2 Data Memory Organization ............................................................................................ 11

Figure 5-3 System clock oscillator Configuration ............................................................................. 15

Figure 5-4 Organization of the dual-clock operation mode............................................................... 17

Figure 5-5 Organization of Divider0 and watchdog timer ................................................................. 18

Figure 5-6 Organization of Timer 0 ................................................................................................. 19

Figure 5-7 Organization of Timer 1 ................................................................................................. 20

Figure 5-8 Interrupt event control diagram ...................................................................................... 22

Figure 5-9 Hold Mode and Interrupt Operation Flow Chart............................................................... 24

Figure 5-10 Architecture of RA (RB) Input/Output Pins.................................................................... 28

Figure 5-11 Architecture of P0 Input/Output pins............................................................................. 29

Figure 5-12 Timing of the Serial Input Function (SIP R) .................................................................. 32

Figure 5-13 Timing of the Serial Output Function (SOP R).............................................................. 32

Figure 5-14 Architecture of Input Ports RC ..................................................................................... 34

Figure 5-15 Architecture of Input Ports RD ...................................................................................... 36

Figure 5-16 The relation between the touch tone keypad and the frequency.................................... 37

Figure 5-17 LCD alternating frequency (F

LCD

) circuit diagram.......................................................... 40

Figure 5-18 1/4 Bias LCD Power Connection.................................................................................... 41

Figure 5-19 1/3 Bias LCD Power Connection.................................................................................... 42

Figure 5-20 1/4 bias,18 duty, A type LCD waveform......................................................................... 43

Figure 5-21 1/4 bias, 1/8 duty, B type LCD waveform....................................................................... 44

Table 1 Vector address and interrupt priority ...................................................................................... 7

Table 2 The relation between the tone frequency and the preset value of TM1 ............................... 20

Table 3 The initial state after the reset function is executed ............................................................ 28

Table 4 The relation between the MFP output frequency and the data specified by 8-bit operand ... 39

Table 5 The relationship between the F

LCD

and the duty cycle ......................................................... 40

W742C818

Publication Release Date: October 2000

- 3 - Revision A2

Table 6 The relation between the LCDR and segment/common pins ................................................ 40

1. GENERAL DESCRIPTION

The W742C818 (SA5696) is a high-performance 4-bit micro-controller (

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C) that built in 224-dot

LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers in dual-clock
operation, a 28

�

8 LCD driver, ten 4-bit I/O ports (including 2 output port for LED driving),

multiple frequency output (MFP), and one channel DTMF generator. There are also eleven
interrupt sources and 16-level stack buffer. The W742C818 operates on very low current and
has three power reduction modes, hold mode, stop mode and slow mode, which help to
minimize power dissipation.

2. FEATURES

�

Operating voltage

2.4V - 6.0V for mask type

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Dual-clock operation

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Main oscillator

3.58MHz or 400khz can be selected by code option

Crystal or RC oscillator can be selected by code option

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Sub-oscillator

Connect to 32.768KHz crystal only

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Memory

16384(16K) x 16 bit program ROM (including 64K x 4 bit look-up table)

4096(4K) x 4 bit data RAM (including 16 nibbles x 16 pages working registers)

28 x 8 LCD data RAM

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32 input/output pins

Port for input only: 3 ports/12 pins

Input/output ports: 3 ports/12 pins

High sink current output port for LED driving: 2 port /8 pins

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Power-down mode

Hold mode: no operation (main oscillator and sub-oscillator still operate)

Stop mode: no operation (main oscillator and sub-oscillator are stopped)

Slow mode: main oscillator is stopped, system is operated by the sub-oscillator

(32.768KHz)

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Eleven interrupt sources

Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1)

Seven external interrupts (RC.0-3, P1.2(/INT0), Serial Port, P1.3(/INT1))

W742C818

Publication Release Date: October 2000

- 4 - Revision A2

�

LCD driver output

28 segments x 8 commons

1/8 duty, 1/3 or 1/4 bias driving mode by option code

Clock source should be the sub-oscillator clock in the dual-clock operation mode

16 level software LCD contrast adjusting

LCD operating voltage by internal pump

LCD wave form type A or type B by option code

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MFP output pin

Output is software controlled to generate modulating or non-modulating frequency

Works as frequency output specified by Timer 1

Key tone generator

�

DTMF output pin

Output is one channel Dual Tone Multi-Frequency signal for dialing

�

8-bit Serial I/O Interface

8-bit transmit/receive mode by internal or external clock source

�

Two built-in 14-bit frequency dividers

Divider0: the clock source is the main oscillator (Fosc)

Divider1: the clock source is the sub-oscillator (Fs)

�

Two built-in 8-bit programmable countdown timers

Timer 0: one of two internal clock frequencies (F

OSC

/4 or F

OSC

/1024) can be selected

Timer 1: with auto-reload function and one of three internal clock frequencies (F

OSC

/64 or Fs) can be selected (signal output through MFP pin)

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Built-in 18/115-bit watchdog timer selectable for system reset, enable/disable by code option

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Powerful instruction set: 1XX instructions

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16-level stack buffer

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Package type : 100-pin QFP

W742C818

Publication Release Date: October 2000

- 5 - Revision A2

3. PIN CONFIGURATION

W742C818

3
3

3
6

3
7

NC
NC
NC
NC

VLCD5

VLCD3

VLCD2

P01
P00

P11

P12

P13

SEG02

SEG08

COM02
COM03
COM04
COM05
COM06
COM07

SEG00

VLCD4

VLCD1

COM00

MFP

RA0

SEG07

100-PIN

COM01

NC
NC

RA2
RA3
RB0
RB1
RB2
RB3

XOUT2

XIN2

VSS

P02

P03

P10

SEG01

SEG03

SEG04

SEG05

SEG06

SEG09

SEG10

QFP

RA1

DTMF

[Data_IO]

[Vpp]

[mode]

W742C818

Publication Release Date: October 2000

- 6 - Revision A2

4. W742C818 PIN DESCRIPTION

SYMBOL

I/O

FUNCTION

XIN2

Input pin for sub-oscillator.
Connected to 32.768 Khz crystal only.

XOUT2

Output pin for sub-oscillator with internal oscillation capacitor. Connected to
32.768 Khz crystal only.

XIN1

Input pin for main-oscillator.
Connected to 3.58MHz crystal or resistor to generate system clock.

XOUT1

Output pin for main-oscillator.
Connected to 3.58MHz crystal or resistor to generate system clock.

RA0-RA3
Data_IO

I/O

Input/Output port.
Input/output mode specified by port mode 1 register (PM1).

RA.3: serial data Input/Output for electrical erasable EPROM type

RB0-RB3

I/O

Input/Output port.
Input/output mode specified by port mode 2 register (PM2).

RC0-RC3

Input port only.
Each pin has an independent interrupt capability.

RD0-RD3

Input port only.
This port can release hold mode but can not occur interrupt service routine.

RE0-RE3
RF0-RF3

Output port only. CMOS type with high sink current capacity for the LED
application.

P00-P03

I/O

Input/Output port.
Input/output mode specified by port mode 6 register (PM6).
P0.0 and P0.1 can be a serial I/O interface selected by SIR register. P0.0
indicates serial clock, P0.1indicates serial data.

P10-P13
Mode

Input port only.
P1.2 & P1.3 indicates hardware interrupt(/INT0 & /INT1)
P1.3: Mode select for electrical erasable EPROM type

MFP

Output pin only, default in low state.
This pin can output modulating or non-modulating frequency, or Timer 1
clock output specified by mode register 1 (MR1).

DTMF

This pin can output dual-tone multi-frequency signal for dialing.

RES

Vpp

System reset pin with internal pull-high resistor.
Vpp : Supply programming voltage, without internal pull-high resistor
for electrical erasable EPROM type for avoiding high voltage
programming damage

SEG0-
SEG27

LCD segment output pins.

COM0-
COM7

LCD common signal output pins.
The LCD alternating frequency can be selected by code option.

CP,CN

Connection terminals for LCD voltage doubler capacitor(0.1uF), tuning the
capacitor value can reduce the LCD driving current .

VLCD1-5

Positive LCD voltage supply terminals.

VDD

Positive power supply (+).

VSS

Negative power supply (-).

W742C818

Publication Release Date: October 2000

- 7 - Revision A2

5. FUNCTIONAL DESCRIPTION

5.1 Program Counter (PC)

Organized as an 14-bit binary counter (PC0 to PC13), the program counter generates the
addresses of the 16384 (16K)

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16 on-chip ROM containing the program instruction words.

When the interrupt or initial reset conditions are to be executed, the corresponding address
will be loaded into the program counter directly. From address 0000h to 0023h are reserved
for reset and interrupt service routine. The format used is shown below.

ITEM

ADDRESS

INTERRUPT PRIORITY

Initial Reset

0000H

INT 0 (Divider0)

0004H

1st

INT 1 (Timer 0)

0008H

2nd

INT 2 (Port RC)

000CH

3rd

INT 3 (Port 1.2(/INT0))

0010H

4th

INT 4 (Divider1)

0014H

5th

INT 5 (Serial I/O)

0018H

6th

INT 6 (Port1.3(/INT1))

001CH

7th

INT 7 (Timer 1)

0020H

8th

code start

0024H

Table 1 Vector address and interrupt priority

5.2 Stack Register (STACK)

The stack register is organized as 51 bits x 16 levels (first-in, last-out). When either a call
subroutine or an interrupt is executed, the program
counter(PC) ,TAB0 ,TAB1 ,TAB2 ,TAB3 ,DBKRL ,DBKRH ,WRP ,ROMPR ,PAGE ,ACC and
CF will be pushed into the stack register automatically. At the end of a call subroutine or an
interrupt service subroutine, the RTN (only restore the program counter) and RTN #I instruction
could pop the contents of the stack register into the corresponding registers. It can restore part
of contents of stack buffer. When the stack register is pushed over the 16th level, the contents
of the first level will be overwritten. In the other words, the stack register is always 16 levels
deep. The bit definition of #I is listed below.

I=0000 0000

Pop PC from stack only

bit0=1

Pop TAB0, TAB1, TAB2, TAB3 from stack

bit1=1

Pop DBKRL, DBKRH from stack

bit2=1

Pop WRP from stack

bit3=1

Pop ROMPR from stack

bit4=1

Pop PAGE from stack

bit5=1

Pop ACC from stack

bit6=1

Pop CF from stack

W742C818

Publication Release Date: October 2000

- 8 - Revision A2

5.3 Program Memory (ROM)

The read-only memory (ROM) is used to store program codes or the look-up table that can be
arranged up to 65536(64K)

�

4 bits. The program ROM is divided into eight pages; the size of

each page is 2048(2K)

�

16 bits. So the total ROM size is 16384(16K)

�

16 bits. Before the jump

or subroutine call instructions are to be executed, the destination ROM page register (ROMPR)
must be determined firstly. The ROM page can be selected by executing the MOV ROMPR, #I
or MOV ROMPR,RAM instructions. But the branch decision instructions (e.g. JB0, SKB0, JZ,
JC, ...) must jump into the same ROM page. Each look-up table element is composed of 4 bits,
so the look-up table can be addressed up to 65536(64K) elements. It uses instructions MOV
TAB0,R MOV TAB1,R MOV TAB2,R MOV TAB3,R to determine the look-up table element
address. The look-up table address is 4 times PC counter. Instruction MOVC R is used to read
the look-up table content and save data into the RAM. The organization of the program
memory is shown in Figure 5-1.

0000
H

16 bits

16384 * 16 bits

0FFFH

0800H

Each element (4 bits) of the look-up table

07FFH

1000H

1FFFH

1800H

17FFH

2000H

2FFFH

2800H

27FFH

3800H

37FFH

3000H

3FFFH

All Program memory can be used to store instruction code or look-up table

Page 0

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Figure 5-1 Program Memory Organization

5.3.1 ROM Page Register (ROMPR)

The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows:

W742C818

Publication Release Date: October 2000

- 10 - Revision A2

Bit 13-0 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

jmp into the same page

Example:
JB0 Lable_A0
JB1 Lable_A1
JB2 Lable_A2
JB3 Lable_A3
JZ Label_Az
JNZ Label_Anz
JC Label_Ac
JNC Label_Anc

4. Look-up Table

Bit 15-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TA33 TA32 TA31 TA30 TA23 TA22 TA21 TA20 TA13 TA12 TA11 TA10 TA03 TA02 TA01 TA00

Table address

Look-up table address = (TAB3, TAB2, TAB1, TAB0)

Example:
TABLE TAB_addr ; Real_TAB_addr (PC value) = TAB_addr/4
00h, 01h, 02h, 0Ah, 0Ch, 0Dh, 0Eh, 0Fh
ENDT

MOV TAB0, TAB_addr_B0_3 ;set Look-up table address
MOV TAB1, TAB_addr_B4_7
MOV TAB2, TAB_addr_B8_11
MOV TAB3, TAB_addr_B12_15
MOVC RAM ;get Look-up table value to RAM

5.4 Data Memory (RAM)

5.4.1 Architecture

The static data memory (RAM) used to store data is arranged up to 4096(4K)

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4 bits. The data

RAM is divided into 32 banks; each bank has 128

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4 bits. Executing the MOV DBKRL,WR,

MOV DBKRH,WR or MOV DBKRL,#I, MOV DBKRH,#I instructions can determine which data
bank is used. The data memory can be accessed directly or indirectly and the data bank
register has to be confirmed firstly. In the indirect addressing mode, each data bank will be
divided into eight pages. The RAM page register has to be setting when in the indirect
accessing RAM. The instructions MOV WRn,@WRq MOV @WRq,WRn could Read or Write

W742C818

Publication Release Date: October 2000

- 11 - Revision A2

the whole memory in the indirect addressing mode. The RAM address of @WRq indicates to
(DBKRH)*800H + (DBKRL)*80H + (RAM page)*10H + (WRq). The organization of the data
memory is shown in Figure 5-2.

data bank 00

4096

address

0000H

4 bits

4096 * 4 bits

007FH
0080H

00FFH

data bank 01

0F80H

0FFFH

data bank 31

(or Working Registers bank)

00H

0FH
10H

1FH
20H

2FH

70H

7FH

:
:

1st data RAM page

(or 1st WR page)

2nd data RAM page

(or 2nd WR page)

8th data RAM page

(or 8th WR page)

3rd data RAM page

(or 3rd WR page)

(or Working Registers bank)

Figure 5-2 Data Memory Organization

The 1st and 2nd data bank (00H to 7FH & 80H to 0FFH) in the data memory can also be used
as the working registers (WR). It is also divided into sixteen pages. Each page contains 16
working registers. When one page is used as Working Register, the others can be used as the
normal data memory. The WR page register can be switched by executing the MOV WRP,R or
MOV WRP,#I instructions. The data memory can not do the logical operation directly with the
immediate data, it has to via the Working Register.

5.4.2 RAM Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

PAGE

Note: R/W means read/write available.

Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 RAM page bits:
000 = Page 0 (00H - 0FH)
001 = Page 1 (10H - 1FH)
010 = Page 2 (20H - 2FH)
011 = Page 3 (30H - 3FH)
100 = Page 4 (40H - 4FH)
101 = Page 5 (50H - 5FH)
110 = Page 6 (60H - 6FH)
111 = Page 7 (70H - 7FH)

W742C818

Publication Release Date: October 2000

- 12 - Revision A2

5.4.3 WR Page Register (WRP)

The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W

WRP

R/W

Note: R/W means read/write available.

Bit 3, Bit 2, Bit 1, Bit 0 Working registers page bits:
0000 = WR Page 0 (00H - 0FH)
0001 = WR Page 1 (10H - 1FH)
0010 = WR Page 2 (20H - 2FH)
0011 = WR Page 3 (30H - 3FH)
0100 = WR Page 4 (40H - 4FH)
0101 = WR Page 5 (50H - 5FH)
0110 = WR Page 6 (60H - 6FH)
0111 = WR Page 7 (70H - 7FH)

1000 = WR Page 8 (80H - 8FH)
1001 = WR Page 9 (90H - 9FH)
1010 = WR Page A (A0H - AFH)
1011 = WR Page B (B0H - BFH)
1100 = WR Page C (C0H - CFH)
1101 = WR Page D (D0H - DFH)
1110 = WR Page E (E0H - EFH)

1111 = WR Page F (F0H - FFH)

5.4.4 Data Bank Register (DBKRH, DBKRL)

The data bank register is organized as two 4-bit binary register. The bit descriptions are as follows:

R/W

DBKRL

R/W

DBKRH

Note: R/W means read/write available.

Bit5 must keep zero.
Bit5, Bit 4, Bit3, Bit 2, Bit 1, Bit 0 Data memory bank bits:

000000 = Data bank 0 (000H - 07FH)
000001 = Data bank 1 (080H - 0FFH)
000010 = Data bank 2 (100H - 17FH)

W742C818

Publication Release Date: October 2000

- 13 - Revision A2

000011 = Data bank 3 (180H - 1FFH)
000100 = Data bank 4 (200H - 27FH)
000101 = Data bank 5 (280H - 2FFH)
000110 = Data bank 6 (300H - 37FH)
000111 = Data bank 7 (380H - 3FFH)

001000 = Data bank 8 (400H - 47FH)
001001 = Data bank 9 (480H - 4FFH)
001010 = Data bank 10 (500H - 57FH)
001011 = Data bank 11 (580H - 5FFH)
001100 = Data bank 12 (600H - 67FH)
001101 = Data bank 13 (680H - 6FFH)
001110 = Data bank 14 (700H - 77FH)
001111 = Data bank 15 (780H - 7FFH)

010000 = Data bank 16 (800H - 87FH)
010001 = Data bank 17 (880H - 8FFH)
010010 = Data bank 18 (900H - 97FH)
010011 = Data bank 19 (980H - 9FFH)
010100 = Data bank 20 (0A00H - 0A7FH)
010101 = Data bank 21 (0A80H - 0AFFH)
010110 = Data bank 22 (0B00H - 0B7FH)
010111 = Data bank 23 (0B80H - 0BFFH)

011000 = Data bank 24 (0C00H - 0C7FH)
011001 = Data bank 25 (0C80H - 0CFFH)
011010 = Data bank 26 (0D00H - 0D7FH)
011011 = Data bank 27 (0D80H - 0DFFH)
011100 = Data bank 28 (0E00H - 0E7FH)
011101 = Data bank 29 (0E80H - 0EFFH)
011110 = Data bank 30 (0F00H - 0F7FH)
011111 = Data bank 31 (0F80H - 0FFFH)

5.4.5 RAM Addressing Mode

1. Direct Addressing

Bit 11-0 11 10 9 8 7 6 5 4 3 2 1 0

BH0 BL3 BL2 BL1 BL0 RA6 RA5 RA4 RA3 RA2 RA1 RA0

RAM addr

RA0-6 is RAM address ; BL0-3 is DBKRL register ; BH0 is DBKRH register

Example:

MOV DBKRL,#BL_value ;set RAM bank

W742C818

Publication Release Date: October 2000

- 14 - Revision A2

MOV DBKRH,#BH_value

MOV A,RAM ;get RAM data to ACC

2. Working register Addressing

Bit 7-0 7 6 5 4 3 2 1 0

WP3 WP2 WP1 WP0 WA3 WA2 WA1 WA0

RAM addr

WA0-3 is Working register address ; WP0-3 is WR page register(WRP)

Example:

MOV DBKRL,#BL_value ;set RAM bank

MOV DBKRH,#BH_value

MOV WRP,#I ;set WR page register

MOVA WRn,RAM ;mov RAM data to Working register and ACC

3. Indirect Addressing

Bit 12-0 11 10 9 8 7 6 5 4 3 2 1 0

BH0 BL3 BL2 BL1 BL0 DP2 DP1 DP0 (WA3 WA2 WA1 WA0)

RAM addr

(WA0-3) is Working register contents ; DP0-3 is RAM page register(PAGE)
BL0-3 is DBKRL register ; BH0 is DBKRH register

Example:

MOV DBKRL,BL_value ;set RAM bank

MOV DBKRH,BH_value

MOV PAGE,#Ip ;set RAM page address,(0-07H)

MOV WRq,#In ;set WR pointer address;(0-0FH)

MOV WRn,@WRq ;get the contents of WRq pointing addr to WRn

5.5 Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

5.6 Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

�

Logic operations: ANL, XRL, ORL

W742C818

Publication Release Date: October 2000

- 15 - Revision A2

�

Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

�

Shift operations: SHRC, RRC, SHLC, RLC

�

Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions is executed, the status of the carry flag (CF) and zero flag (ZF)
is stored in the internal registers. CF can be read out by executing MOV R, CF.

5.7 Main Oscillator

The W742C818 provides a crystal oscillation circuit to generate the system clock through
external connections. The 3.58 Mhz or 400Khz crystal must be connected to XIN1 and
XOUT1, see Figure 5-3 and a capacitor must be connected to XIN1 and V

if an accurate

frequency is needed.

XIN1

XOUT1

Crystal

3.58MHz

Figure 5-3 System clock oscillator Configuration

5.8 Sub-Oscillator

The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just
only the 32768 Hz crystal could be connected to XIN2 and XOUT2.

5.9 Dividers

Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic
interrupt. When the main clock starts action, the Divider0 is incremented by each clock (F

OSC

The main clock can come from main oscillator or sub-oscillator by setting SCR register. When
an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0
interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold
release enable flag has been set (HEF.0 = 1), the hold state is terminated. And the last 4-stage
of the Divider0 can be reset by executing CLR DIVR0 instruction. If the main clock is
connected to the 32.768K Hz crystal, the EVF.0 will be set to 1 periodically at the period of
500mS.
Divider 1 is organized with 13/12 bits up-counter that only has sub-oscillator clock source. If the
sub-oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow
occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable
flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has
been set (HEF.4 = 1), the hold state is terminated. And the last 4-stage of the Divider1 can be
reset by executing CLR DIVR1 instruction. There are two period time (125mS & 250mS) that
can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 250mS period time is
selected; SCR.3 = 1, the 125 mS period time is selected.

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Publication Release Date: October 2000

- 16 - Revision A2

5.10 Dual-clock operation

In this dual-clock mode, the normal operation is performed by generating the system clock
from the main-oscillator clock (Fm). As required, the slow operation can be performed by
generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal
operation and the slow operation is performed by setting the bit 0 of the System clock Control
Register (SCR). If the SCR.0 is set to 0, the clock source of the system clock generator is
main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is
sub-oscillator clock. In the dual-clock mode, the main-oscillator can stop oscillating when the
SCR.1 is set to 1. When the main clock switch, we must care the following cases:
1. X000B

X011B(Fosc=Fm

Fosc=Fs): we should not exchange the F

OSC

from Fm into Fs

and disable Fm simultaneously. We could first exchange the F

OSC

from Fm into Fs, then

disable the main-oscillator. So it should be X000B

X001B

X011B.

2. X011B

X000B(Fosc=Fs

Fosc=Fm): we should not enable Fm and exchange the F

OSC

from Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is
calling a delay subroutine to wait the main-oscillator oscillating stably; then exchange the F

OSC

from Fs into Fm is the last step. So it should be X011B

X001B

delay the Fm oscillating

stable time

X000B.

We must remember that the X010B state is inhibitive, because it will induce the system
shutdown.
The organization of the dual-clock operation mode is shown in Figure 5-4.

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Publication Release Date: October 2000

- 17 - Revision A2

System Clock

Generator

Main Oscillator

XIN1

XOUT1

Sub-oscillator

XIN2

XOUT2

Fosc

Divider 0

SCR : System clock Control Register ( default = 00H

)

Bit0

Bit1

Bit2

Bit3

0 : Fosc = Fm

1 : Fosc = Fs
0 : Fm enable

1 : Fm disable
0 : WDT input clock is Fosc/1024

1 : WDT input clock is Fosc/16384

enable/disable

SCR.1

STOP

HOLD

SCR.0

LCD Frequency

Selector

LCD

Divider 1

INT4
HCF.4

SCR.3(13/12 bit)

1 : 12 bit

0 : 13 bit

Daul clock operation mode :

- SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs

- Flcd=Fs, In STOP mode LCD is turned off.

Figure 5-4 Organization of the dual-clock operation mode

5.11 Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program

from unknown errors. The WDT can be enabled by mask option code. If the WDT overflows,
the chip will be reset. At initial reset, the input clock of the WDT is F

OSC

/1024. The input clock

of the WDT can be switched to F

OSC

/16384 by setting SCR.2 register. The contents of the

WDT can be reset by the instruction CLR WDT. In normal operation, the application program
must reset WDT before it overflows. A WDT overflow indicates that operation is not under
control and the chip will be reset. The WDT overflow period is about 500 mS when the system
clock (F

OSC

) is 32 KHz and WDT clock input is F

OSC

/1024. The organization of the Divider0

and watchdog timer is shown in Figure 5-5. The minimum WDT time interval is
1/(Fosc/16384x16) - 1/(Fosc/16384).

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Publication Release Date: October 2000

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Q10 Q11 Q12

Q14

Q13

Fosc

HEF.0

IEF.0

1. Reset

2. CLR EVF,#01H

EVF.0

Hold mode release (HCF.0)

Divider interrupt

...

Overflow signal

WDT

Enable

Disable

SCR.2

Fosc/2048

Fosc/16384

Option code is reset to "0"

Qw1

Qw2

Qw4

Qw3

Divider0

System Reset

1. Reset

2. CLR WDT

3. CLR DIVR0

Option code is set to "1"

Figure 5-5 Organization of Divider0 and watchdog timer

5.12 Timer/Counter

5.12.1 Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be
loaded into TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV
TM0L(TM0H),R instructions are executed, it will stop the TM0 down-counting (if the TM0 is
down-counting) and reset the start bit (MR0.3) to 0, and the specified value is loaded into TM0.
Then we can set MR0.3 to 1 to cause the event flag 1 (EVF.1) is reset and the TM0 starts to
down count. When it decrements to FFH from 00H, Timer 0 stops down-counting and
generates an underflow flag (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been
set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set
(HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as F

OSC

/1024 or

OSC

/4 by setting MR0 bit 0. The default timer value is F

OSC

/4. The organization of Timer 0 is

shown in Figure 5-6.

If the Timer 0 clock input is F

OSC

/4:

Desired Timer 0 interval = (preset value +1)

�

1/F

OSC

If the Timer 0 clock input is F

OSC

/1024:

Desired Timer 0 interval = (preset value +1)

�

1024

�

1/F

OSC

Preset value: Decimal number of Timer 0 preset value
F

OSC

: Clock oscillation frequency

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Publication Release Date: October 2000

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Fosc/4

Fosc/1024

Enable

Disable

1. Reset

2. CLR EVF,#02H

8-Bit Binary

Down Counter

S
R

HEF.1

IEF.1

Hold mode release (HCF.1)

Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF,#02H

EVF.1

MR0.0

(Timer 0)

Set MR0.3 to 1

3. Reset MR0.3 to 0

3.Set MR0.3 to 1

MOV TM0H,R

MOV TM0L,R

4.MOV TM0L,R or MOV TM0H,R

Figure 5-6 Organization of Timer 0

5.12.2 Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 5-7.
Timer 1 can output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be
one of three sources: F

OSC

/64, F

OSC

or F

. The source can be selected by setting bit 0 and bit

1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is F

OSC.

When the MOV

TM1L, R or MOV TM1H,R instruction is executed, the specified value is loaded into the auto-
reload buffer and the TM1 down-counting will be disabled that is the start bit (MR1.3) is reset to
0 simultaneously. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the auto-reload buffer
will be loaded into the TM1 down counter, and Timer 1 starts to down count, and the event flag
7 is reset (EVF.7=0). When the timer decrements to 0FFH from 00H, it will generate an
underflow (EVF.7 = 1) and auto-reload the specified data then continue to count down. When
Timer1 underflows, if interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is
executed; if hold mode release enable flag 7 is set to 1 (HEF.7 = 1), the hold state is
terminated. The specified frequency of Timer 1 can be delivered to the MFP output pin by
programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

In a case where Timer 1 clock input is F

Desired Timer 1 interval = (preset value +1) / F

Desired frequency for MFP output pin = F

�

(preset value + 1)

�

2 (Hz)

Preset value: Decimal number of Timer 1 preset value
F

OSC

: Clock oscillation frequency

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Publication Release Date: October 2000

- 20 - Revision A2

Auto-reload buffer

8 bits

MR1.3

Underflow signal

EVF.7

MFP

MFP signal

MR1.2

output pin

8-Bit Binary

Down Counter

circuit

Reset

Disable

Enable

Fosc/64

Fosc

MR1.0

(Timer 1)

1. Reset
2. INT7 accept

3. CLR EVF, #80H

MOV TM1L,R or MOV TM1H,R

4. Set MR1.3 to 1

MOV TM1H,R

MOV TM1L,R

Set MR1.3 to 1

MR1.1

Figure 5-7 Organization of Timer 1

For example, when F

equals 32768 Hz, depending on the preset value of TM1, the MFP pin

will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The
relation between the tone frequency and the preset value of TM1 is shown in the table below.

C
C

TM1 preset value
& MFP frequency

3rd octave

4th octave

5th octave

261.63

277.18

293.66

311.13

329.63

349.23

369.99

392.00

415.30

440.00

466.16

493.88

523.25

554.37

587.33

622.25

659.26

698.46

739.99

783.99

830.61

880.00

932.23

987.77

260.06

277.69

292.57

309.13

327.68

348.58

372.35

390.08

420.10

442.81

3EH

3AH

37H

34H

31H

2EH

2BH

29H

26H

22H

24H

20H

468.11

496.48

1EH

1CH

1BH

19H

18H

16H

15H

14H

13H

12H

11H

10H

528.51

564.96

585.14

630.15

655.36

712.34

744.72

780.19

819.20

862.84

910.22

963.76

130.81

138.59

146.83

155.56

164.81

174.61

185.00

196.00

207.65

220.00

233.08

246.94

7CH

75H

6FH

68H

62H

5DH

58H

53H

4EH

45H

49H

41H

131.07

138.84

146.28

156.03

165.49

174.30

184.09

195.04

207.39

221.40

234.05

248.24

Tone

frequency

Tone

frequency

TM1 preset value
& MFP frequency

Tone

frequency

TM1 preset value
& MFP frequency

Note: Central tone is A4 (440 Hz).

Table 2 The relation between the tone frequency and the preset value of TM1

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Publication Release Date: October 2000

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5.12.3 Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to
control the operation of Timer 0. The bit descriptions are as follows:

MR0

Note: W means write only.

Bit 0 = 0 The fundamental frequency of Timer 0 is F

OSC

/4.

= 1 The fundamental frequency of Timer 0 is F

OSC

/1024.

Bit 1 & Bit 2 are reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

5.12.4 Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to
control the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is F

OSC

= 1 The internal fundamental frequency of Timer 1 is F

OSC

/64.

Bit 1 = 0 The fundamental frequency source of Timer1 is the internal clock.

= 0 The fundamental frequency source of Timer1 is the sub-oscillator frequency

Fs(32.768KHz).

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.

Bit 3 = 0 Timer 1 stops down-counting.
= 1 Timer 1 starts down-counting.

5.13 Interrupts

The W742C818 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1)
and seven external interrupt source (port P1.2(/INT 0), RC.0-3, Serial port, P1.3(/INT1)).
Vector addresses for each of the interrupts are located in the range of program memory (ROM)
addresses 004H to 023H. The flags IEF, PEF, and EVF are used to control the interrupts.
When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set
by software, an interrupt is generated. When PC jumps to an interrupt vector by interrupt
event, the corresponding bit of EVF will be clear, and all of the interrupts will be
inhibited until the EN INT or MOV IEF,#I instruction is invoked. Normally, the EN INT
instruction will be asserted before the RTN instruction. The interrupts can also be disabled
by executing the DIS INT instruction. When an interrupt is generated in the hold mode, the
hold mode will be released momentarily and interrupt service routine will be executed. After

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Publication Release Date: October 2000

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5.14 Stop Mode Operation

In stop mode, all operations of the

�

C cease. The

�

C enters stop mode when the STOP

instruction is executed and exits stop mode when an external trigger is activated (by a falling
signal on the RC or RD port). When the designated signal is accepted, the

�

C awakens and

executes the next instruction. In the dual-clock slow operation mode, the STOP instruction will
disable both the main-oscillator and sub-oscillator oscillating; To avoid erroneous execution,
the NOP instruction should follow the STOP command.

5.14.1 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF)

The stop mode wake-up flag for port RC and RD is organized as an 8-bit binary register (SEF.0
to SEF.7). Before port RC and RD can be used to exit the stop mode, the content of the SEF
must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions
are as follows:

SEF

Note: W means write only.

SEF.0 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.0

SEF.1 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.1

SEF.2 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.2

SEF.3 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.3

SEF.4 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.0

SEF.5 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.1

SEF.6 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.2

SEF.7 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.3

5.15 Hold Mode Operation

In hold mode, all operations of the

�

C cease, except for the operation of the oscillator, Timer,

Divider, and LCD driver. The

�

C enters hold mode when the HOLD instruction is executed.

The hold mode can be released in one of nine ways: by the action of timer 0, timer 1, divider 0,
divider 1, RC port, P1.2(/INT0), Serial I/O, P1.3(/INT1) and RD port. Before the device enters
the hold mode, the HEF,HEFD, PEF, and IEF flags must be set to control the hold mode
release conditions. When any of the HCF bits is "1," the hold mode will be released. Regarding
to RC and RD port, PSR0 and PSR1 registers indicate signal change on which pin of the port.
The HCF and HCFD are set by hardware and clear by software. When EVF,EVFD and
HEF,HEFD have been reset by the CLR EVF,#I CLR EVFD and MOV HEF,#I CLR HEFD
instructions, the corresponding bit of HCF,HCFD is reset simultaneously. The HCF and HCFD
should be clear every time before enter the hold mode. For more details, refer to the following
flow chart.

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Publication Release Date: October 2000

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HEF

HEFD

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released.

HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released.

HEF.2 = 1 Signal change at port RC causes Hold mode to be released.

HEF.3 = 1 Falling edge signal at port P1.2(/INT0) causes Hold mode to be released.

HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released.

HEF.5 = 1 Serial I/O

HEF.6 = 1 Falling edge signal at port P1.3(/INT1) causes Hold mode to be released.

HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.

HEFD = 1 Signal change at port RD causes Hold mode to be released.

5.15.2 Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7). These bits are
used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When
one of these interrupts is occurred, the corresponding event flag will be clear, but the other bits
are unaffected. In interrupt subroutine, these interrupts will be disable till the instruction MOV
IEF, #I or EN INT is executed again. However, these interrupts can be disable by executing
DIS INT instruction. The bit descriptions are as follows:

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.

IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.

IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC.

IEF.3 = 1 Interrupt 3 is accepted by a falling edge signal at port P1.2(/INT0).

IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1.

IEF.5 = 1 Interrupt 5 is accepted by Serial I/O signal

IEF.6 = 1 Interrupt 6 is accepted by a falling edge signal at port P1.3(/INT1).

IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

5.15.3 Port Enable Flag (PEF,P1EF)

The port enable flag is organized as 8-bit binary register (PEF.0 to PEF.7) and 4-bit register
(P1EF.2 and P1EF.3). Before port RC,RD may be used to release the hold mode , the content of
the PEF must be set first. The PEF and P1EF are controlled by the MOV PEF, #I MOV P1EF,#I

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instructions. The bit descriptions are as follows. Besides release hold mode, the RC port can be bit
controlled individually to perform interrupt function.

PEF

P1EF

Note: W means write only.

PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt.

PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt.

PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt.

PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.

PEF.4: Enable/disable the signal change at pin RD.0 to release hold mode.

PEF.5: Enable/disable the signal change at pin RD.1 to release hold mode.

PEF.6: Enable/disable the signal change at pin RD.2 to release hold mode.

PEF.7: Enable/disable the signal change at pin RD.3 to release hold mode.

P1EF.2: Enable/disable the falling edge signal at P1.2 to release hold mode.

P1EF.3: Enable/disable the falling edge signal at P1.3 to release hold mode.

5.15.4 Hold Mode Release Condition Flag (HCF,HCFD)

The hold mode release condition flag is organized as 8-bit binary register (HCF.0 to HCF.7)and
HCFD. It indicates which one releases the hold mode, and is set by hardware. The HCF can be
read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is
"1," the hold mode will be released. But the HCFD can not be read, it is only for internal flag. It
records the port RD releases hold mode. The HCF and HCFD are set by hardware and cleared
when EVF or HEF are cleared. The HCF and HCFD should be clear every time before enter
the hold mode. When EVF, EVFD and HEF, HEFD have been reset, the corresponding bit of
HCF,HCFD is reset simultaneously. The bit descriptions are as follows:

HCF

HCFD: internal flag, can not be read

Note: R means read only.

HCF.0 = 1 Hold mode was released by overflow from the divider 0.

HCF.1 = 1 Hold mode was released by underflow from the timer 0.

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Publication Release Date: October 2000

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HCF.2 = 1 Hold mode was released by a signal change at port RC.

HCF.3 = 1 Hold mode was released by a signal change at port P1.2(/INT0).

HCF.4 = 1 Hold mode was released by overflow from the divider 1.

HCF.5 = 1 Hold mode was released by Serial I/O signal.

HCF.6 = 1 Hold mode was released by a signal change at port P1.3(/INT1).

HCF.7 = 1 Hold mode was released by underflow from the timer 1.

HCFD = 1 Hold mode was released by a signal change at port RD.

5.15.5 Event Flag (EVF,EVFD)

The event flag is organized as a 8-bit binary register (EVF.0 to EVF.7) and EVFD. It is set by
hardware and reset by CLR EVF,#I ,CLR EVFD instructions or the interrupt occurrence. The bit
descriptions are as follows:

R/W

EVF

R/W

EVFD

R/W

Note: R/W means read/write.

EVF.0 = 1 Overflow from divider 0 occurred.

EVF.1 = 1 Underflow from timer 0 occurred.

EVF.2 = 1 Signal change at port RC occurred.

EVF.3 = 1 Falling edge signal at port P1.2(/INT0) occurred.

EVF.4 = 1 Overflow from divider 1 occurred.

EVF.5 = 1 Serial I/O occurred.

EVF.6 = 1 Falling edge signal at port P1.3(/INT1) occurred.

EVF.7 = 1 Underflow from Timer 1 occurred.

EVFD = 1 Signal change at port RD occurred.

5.16 Reset Function

The W742C818 is reset either by a power-on reset or by pulling low the external RES pin. The
initial state of the W742C818 after the reset function is executed is described below.

Program Counter (PC)

000H

TM0, TM1

Reset

MR0, MR1, PAGE registers

Reset

PSR0, PSR1, PSR2, SCR registers

Reset

IEF, HEF,HEFD, HCF, PEF, P1EF, EVF, EVFD, SEF flags Reset

WRP, DBKR register

Reset

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Publication Release Date: October 2000

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Timer 0 input clock

OSC

Timer 1 input clock

OSC

MFP output

Low

DTMF output

Hi-Z

Input/output ports RA,RB, P0

Input mode

Output port RE & RF

High

RA, RB & P0 ports output type

CMOS type

RC,RD ports pull-high resistors

Disable

Input clock of the watchdog timer

OSC

/1024

LCD display

OFF

Table 3 The initial state after the reset function is executed

5.17 Input/Output Ports RA, RB & P0

Port RA consists of pins RA.0 to RA.3. Port RB consists of pins RB.0 to RB.3. Port P0 consists
of pins P0.0 to P0.3. At initial reset, input/output ports RA, RB and P0 are all in input mode.
When RA and RB are used as output ports, CMOS or NMOS open drain output type can be
selected by the PM0 register. But when P0 is used as output port, the output type is always
CMOS output type. Each pin of port RA, RB and P0 can be specified as input or output mode
independently by the PM1, PM2 and PM6 registers. The MOVA R, RA or MOVA R, RB or
MOVA R, P0 instructions operate the input functions and the MOV RA, R or MOV RB, R or
MOV P0, R operate the output functions. For more detail port structure, refer to the and Figure
5-10 and Figure 5-10.

Input/Output Pin of the RA(RB)

I/O PIN

RA.n(RB.n)

DATA

BUS

Buffer

Output

PM0.0(PM0.1)

PM1.n (PM2.n)

MOVA R,RA(MOVA R,RB) instruction

MOV RA,R(MOV RB,R)

instruction

Enable

Figure 5-10 Architecture of RA (RB) Input/Output Pins

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Publication Release Date: October 2000

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Input/Output Pin of the P0

I/O PIN

P0.n

DATA

BUS

Buffer

Output

PM6.n

MOVA R,P0 instruction

MOV P0,R instruction

Enable

Figure 5-11 Architecture of P0 Input/Output pins

5.17.1 Port Mode 0 Register (PM0)

The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be
used to determine the port structure; it is controlled by the MOV PM0, #I instruction. The bit
description is as follows:

PM0

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type.

Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type.

Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled.

Bit 3 = 0 RD port pull-high resistor is disabled. Bit 3 = 1 RD port pull-high resistor is enabled.

5.17.2 Port Mode 1 Register (PM1)

The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be
used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I
instruction. The bit description is as follows:

PM1

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin
Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin
Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin
Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin

W742C818

Publication Release Date: October 2000

- 30 - Revision A2

At initial reset, port RA is input mode (PM1 = 1111B).

5.17.3 Port Mode 2 Register (PM2)

The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used
to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The
bit description is as follows:

PM2

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin
Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin
Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin
Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B).

5.17.4 Port Mode 6 Register (PM6)

The port mode 6 register is organized as 4-bit binary register (PM6.0 to PM6.3). PM6 can be
used to control the input/output mode of port P0. PM6 is controlled by the MOV PM6, #I
instruction. The bit description is as follows:

PM6

Note: W means write only.

Bit 0 = 0 P0.0 works as output pin; Bit 0 = 1 P0.0 works as input pin
Bit 1 = 0 P0.1 works as output pin; Bit 1 = 1 P0.1 works as input pin
Bit 2 = 0 P0.2 works as output pin; Bit 2 = 1 P0.2 works as input pin
Bit 3 = 0 P0.3 works as output pin; Bit 3 = 1 P0.3 works as input pin
At initial reset, the port P0 is input mode (PM6 = 1111B).

5.18 Serial I/O interface

The bit 0 and bit 1 of port P0 can be used as a serial input/output port. P0.0 is the serial clock
I/O pin and P0.1 is the serial data I/O pin. A 4-bit binary register, Serial Interface Control
register(SIC), controls the serial port. SIC is controlled by the MOV SIC,#I instruction. The bit
definition is as follow:

SIC

=0 P0.0 & P0.1 work as normal input/output pin

Bit0

=1 P0.0 & P0.1 work as serial port function

W742C818

Publication Release Date: October 2000

- 31 - Revision A2

=0 P0.0 works as serial clock input pin

Bit1

=1 P0.0 works as serial clock output pin
=0 Serial data latched/changed at falling edge of clock

Bit2

=1 Serial data latched/changed at rising edge of clock
=0 Serial clock output frequency is fosc/2

Bit3

=1 Serial clock output frequency is fosc/256

At initial reset, SIC= 0000B.

The serial I/O functions are controlled by the instructions SOP R and SIP R. The two
instructions are described below:
(1) When in the first time the SIP R instruction is executed, the data will be loaded to

the ACC and RAM from the serial input buffer. But this data is not meaningful, it is
used to enable serial port. There are two methods to get the serial data, one is interrupt
and the other is polling. When enable the serial input, the bit 1 of port status register
2(PRS2) will automatically be set to "1" (BUSYI = 1). Then the P0.0 pin will send out 8
clocks or accept 8 clocks from external device and the data from the P0.1 pin will be
loaded to SIB buffer at the rising or falling edge of the P0.0 pin. After the 8 bits have been
received, BUSYI

will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has

been set (IEF.5 = 1), an interrupt is executed then the SIP R instruction can get the correct
data from the serial input buffer(SIB), low nibble of SIB moves to ACC register and the
high nibble moves to RAM; if HEF.5 has been set (HEF.5 = 1), the hold state is
terminated. The polling method is to check the status of PSR2.1 (BUSYI) to know whether
the serial input process is completed or not. If a serial input process is not completed, but
the SIP R instruction is executed again, the data will be lost. The timing is shown in Figure
5-12.

P0.0

Data latch

BUSYI

(PSR2.1)

EVF5

Ins.

P0.1

rising latch

P0.0

falling latch

NOTE: The serial clock frequency is fosc/2

SIP R

W742C818

Publication Release Date: October 2000

- 32 - Revision A2

Figure 5-12 Timing of the Serial Input Function (SIP R)

(2) When the

SOP R instruction is executed,

the data will be loaded to the serial output buffer

(SOB) from ACC and the RAM, the low nibble data of SOB is from ACC register and the
high nibble data is from RAM, and bit 3 of port status register 2(PSR2) will be set to "1"
(BUSY

= 1). Then the P0.0 pin will send out 8 clocks or accept 8 clocks from external

device and the data in SOB will be sent out at the rising or falling edge of the P0.1 pin.
After the 8 clocks have been sent, BUSY

will be reset to "0" and EVF.5 will be set to "1."

At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5 has been
set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.3
(BUSYO) to know whether the serial output process is completed or not. If a serial output
process is not completed, but the SOP R instruction is executed again, the data will be
lost. The timing is shown in Figure 5-13.

P0.0

Data latch

BUSYO

(PSR2.3)

EVF5

Ins.

P0.1

data changed at falling edge

P0.0

NOTE: The serial clock frequency is fosc/2

SOP R

data changed at rising edge

Figure 5-13 Timing of the Serial Output Function (SOP R)

Port Status Register 2 (PSR2)

Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is
controlled by the MOVA R, PSR2, and CLR PSR2 instructions. The bit descriptions are as
follows:

PSR2

W742C818

Publication Release Date: October 2000

- 37 - Revision A2

PSR1

Note: R means read only.

Bit 0 = 1 Signal change at RD.0

Bit 1 = 1 Signal change at RD.1

Bit 2 = 1 Signal change at RD.2

Bit 3 = 1 Signal change at RD.3

5.21 Output Port RE & RF

Output port RE and RF are used as output of the internal RT port. When the MOV RE, R or
MOV RF, R instruction is executed, the data in the RAM will be output to port RT through port
RE or RF. They provide high sink current to drive LED.

5.22 Input Port P1

Input port P1 is a multi-function input port. When the MOVA R, P1 instruction is executed, the
P1 data is passed to the RAM and A register. The P1.2 and P1.3 can be configured as the
external interrupt /INT0 and /INT1 by set P1EF.2 and P1EF.3.

5.23 DTMF Output Pin (DTMF)

W742C818 provides a DTMF generator which outputs the dual tone multi-frequency signal to
the DTMF pin. The DTMF generator can work well at the operating frequency of 3.58MHz. A
DTMF register specify the desired low/high frequency. And the Dual Tone Control Register
(DTCR) can control whether the dual tone will be output or not. The tones are divided into two
groups (low group and high group). The relation between the DTMF signal and the
corresponding touch tone keypad is shown in Figure 5-16

Row/Col

Frequency

697 Hz

770 Hz

852 Hz

941 Hz

1209 Hz

1336 Hz

1477 Hz

1633 Hz

Figure 5-16 The relation between the touch tone keypad and the frequency

C2 C3

W742C818

Publication Release Date: October 2000

- 38 - Revision A2

5.23.1 DTMF register

DTMF register is organized as 4-bit binary register. By controlling the DTMF register, one tone
of the low/high group can be selected. The MOV DTMF,R instruction can specify the wanted
tones. The bit descriptions are as follows:

DTMF

Note: W means write only.

Selected tone

1209 Hz

High

1336 Hz

group

1477 Hz

(Col)

1633 Hz

697 Hz

Low

770 Hz

group

852 Hz

(Row)

941 Hz

Note: X means this bit do not care.

5.23.2 Dual Tone Control Register (DTCR)

Dual tone control register is organized as 4-bit binary register. The output of the dual or single
tone will be controlled by this register. The MOV DTCR,#I instruction can specify the wanted
status. The bit descriptions are as follows:

DTCR

Note: W means write only.

Bit 0 = 1 Low group tone output is enabled.
Bit 1 = 1 High group tone output is enabled.
Bit 2 = 1 DTMF output is enabled. When Bit 2 is reset to 0, the DTMF output pin will be Hi-Z
state.
Bit 3 is reserved.

5.24 MFP Output Pin (MFP)

The MFP output pin can select the output of the Timer 1 clock or the modulation frequency; the
output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in
Figure 5-7. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output
in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals
from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (the clock source is from 32.768 KHz
crystal). The MOV MFP, #I instruction is used to specify the modulation output combination.
The data specified by the 8-bit operand and the MFP output pin are shown in next page.

(Fosc = 32.768 KHz)

W742C818

Publication Release Date: October 2000

- 39 - Revision A2

R7 R6

FUNCTION

Low level

128 Hz

64 Hz

0 0

8 Hz

4 Hz

2 Hz

1 Hz

High level

128 Hz

64 Hz

0 1

8 Hz

4 Hz

2 Hz

1 Hz

2048 Hz

2048 Hz * 128 Hz

2048 Hz * 64 Hz

1 0

2048 Hz * 8 Hz

2048 Hz * 4 Hz

2048 Hz * 2 Hz

2048 Hz * 1 Hz

4096 Hz

4096 Hz * 128 Hz

4096 Hz * 64 Hz

1 1

4096 Hz * 8 Hz

4096 Hz * 4 Hz

4096 Hz * 2 Hz

4096 Hz * 1 Hz

Table 4 The relation between the MFP output frequency and the data specified by 8-bit
operand

5.25 LCD Controller/Driver

The W742C818 can directly drive an LCD with 28 segment output pins and 8 common output
pins for a total of 28 x 8 dots. The LCD driving mode is 1/8 duty and 1/3 or 1/4 bias selected by
option code. The alternating frequency of the LCD can be set as Fw/16, Fw/32, Fw/64, or
Fw/128. The structure of the LCD alternating frequency (F

LCD

) is shown in the Figure 5-17.

W742C818

Publication Release Date: October 2000

- 40 - Revision A2

Selector

Fw/128

Fw/64

Fw/32

Fw/16

Sub-oscillator clock

LCD

Figure 5-17 LCD alternating frequency (F

LCD

) circuit diagram

Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD Frequency

1/8 duty

Fw/128 (256 Hz)

Fw/64 (512 Hz)

Fw/32 (1024 Hz)

128

Fw/16 (2048 Hz)

256

Table 5 The relationship between the F

LCD

and the duty cycle

Corresponding to the 28 LCD drive output pins, there are 56 LCD data RAM segments.
Instructions such as MOV LPL,R, MOV LPH,R, MOV @LP,R, and MOV R,@LP are used to
control the LCD data RAM. The data in the LCD data RAM are transferred to the segment
output pins automatically without program control. When the bit value of the LCD data RAM is
"1," the LCD is turned on. When the bit value of the LCD data RAM is "0", LCD is turned off.
The contents of the LCD data RAM (LCDR) are sent out through the segment0 to segment27
pins by a direct memory access. The relation between the LCD data RAM and
segment/common pins is shown below.

OUTPUT

LCD

COM7 COM6 COM5 COM4

LCD

COM3 COM2 COM1 COM0

PIN

RAM

BIT3

BIT2

BIT1

BIT0

RAM

BIT3

BIT2

BIT1

BIT0

SEG0

LCDR01

0/1

LCDR00

0/1

SEG1

LCDR03

0/1

LCDR02

0/1

:
:

SEG26

LCDR35

0/1

LCDR34

0/1

SEG27

LCDR37

0/1

LCDR36

0/1

Table 6 The relation between the LCDR and segment/common pins

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF
instruction turns the LCD display off. At the initial reset state, the LCD display is turned off
automatically. To turn on the LCD display, the instruction LCDON must be executed.

5.25.1 LCD RAM addressing method

There are 56 LCD RAMs (LCDR00H � LCDR37H) that should be indirectly addressed. The
LCD RAM pointer (LP) is used to point to the address of the wanted LCD RAM but it is not
readable. The LP is organized as 8-bit binary register. The MOV LPL,R and MOV LPH,R

W742C818

Publication Release Date: October 2000

- 41 - Revision A2

instructions can load the LCD RAM address from RAM to the LP register. The

MOV @LP,R

and MOV R,@LP instructions can access the pointed LCD RAM content.

5.25.2 LCD voltage and contrast adjusting

An internal voltage pump is enable/disable by option code. If the voltage pump is enable, set
LCDON high to pump voltage and the signals of Com/Segment output to LCD pins according
the LCD memory, clear LCDON low to turn off the voltage pump. The voltage of internal
regulator is the base voltage of the voltage pump which pumps 3 or 4 times of the base
voltage. The output voltage of the regulator is tunable by setting LCD contrast control register
(LCDCC) by instruction MOV LCDCC,#I. When LCDCC is equal to 0AH, the output voltage is
about 1.0V. The higher value of LCDCC the lower voltage output of regulator. The adjustable
voltage range is about from 0.74V to 1.53V. Accordingly, the LCD contrast is controlled by
LCDCC register. The variation of the voltage depends on the V

5.25.3 LCD Power Connection

The LCD power connection of bias is shown in Figure 5-18 and Figure 5-19.

VSS

VLCD4

VLCD3

0.1uF

C
H
I
P

1/4 Bias

Regulator

C1=C2=C3=C4=C5=0.1uF

VLCD2

VLCD1

VLCD5

VLCD2 and VLCD3 are shorted internally

Figure 5-18 1/4 Bias LCD Power Connection

W742C818

Publication Release Date: October 2000

- 45 - Revision A2

7. DC CHARACTERISTICS

(VDD-VSS = 3.0 V, Fm = 3.58MHz, Fs = 32.768 KHz, Ta = 25

�

C, LCD on,

INTERNAL PUMP DISABLE; unless otherwise

specified)

PARAMETER

SYM

CONDITIONS

MIN. TYP. MAX. UNIT

OP. Voltage (W742C813)

VDD

2.4

6.0

Op. Voltage (W742E813)

2.4

4.8

Op. Current (Crystal type)

OP1

No load (Ext-V)

In dual-clock normal

operation

0.5

1.0

Op. Current (Crystal type)

OP3

No load (Ext-V)

In dual-clock slow

operation and Fm is

stopped

�

Hold Current (Crystal type)

HM1

Hold mode No load (Ext-

In dual-clock normal

operation

400

500

�

Hold Current (Crystal type)

HM3

Hold mode No load (Ext-

In dual-clock slow

operation and Fm is

stopped

�

Hold Current (Crystal type)

HM5

Hold mode No load (Ext-

=5V; In dual-clock

slow operation and Fm is

stopped

�

Stop Current

SM1

Stop mode No load (Ext-

Fm and Fs are stopped

�

Input Low Voltage

0.3V

Input High Voltage

0.7V

MFP Output Low Voltage

= 3.5mA

0.4

MFP Output High Voltage

= 3.5mA

2.4

Port RA, RB, RD Output Low
Voltage

ABL

= 2.0mA

0.4

Port RA, RB, RD Output High
Voltage

ABH

= 2.0mA

2.4

LCD Supply Current

LCD

All Seg. ON

�

SEG0-SEG27 Sink Current
(Used as LCD output)

OL1

= 0.4V

LCD

= 0.0V

�

SEG0-SEG27 Drive Current
(Used as LCD output)

OH1

= 2.4V

LCD

= 3.0V

�

Port RE, RF Sink Current

= 0.9V

W742C818

Publication Release Date: October 2000

- 49 - Revision A2

Machine code

Mnemonic

Function

Flag affected W/C

Arithmetic

0001 1000 0xxx xxxx

ADD

R, ACC

ACC

(R) + (ACC)

ZF, CF

1/1

0001 1100 i i i i nnnn

ADD

WRn, #I

ACC

(WRn) + I

ZF, CF

1/1

0001 1001 0xxx xxxx

ADDR

R, ACC

ACC, R

(R) + (ACC)

ZF, CF

1/1

0001 1101 i i i i nnnn

ADDR

WRn, #I

ACC, WRn

(WRn) + I

ZF, CF

1/1

0000 1000 0xxx xxxx

ADC

R, ACC

ACC

(R) + (ACC) + (CF)

ZF, CF

1/1

0000 1100 i i i i nnnn

ADC

WRn, #I

ACC

(WRn) + I + (CF)

ZF, CF

1/1

0000 1001 0xxx xxxx

ADCR

R, ACC

ACC, R

(R) + (ACC) + (CF)

ZF, CF

1/1

0000 1101 i i i i nnnn

ADCR

WRn, #I

ACC, WRn

(WRn) + I + (CF)

ZF, CF

1/1

0010 1000 0xxx xxxx

ADU

R, ACC

ACC

(R) + (ACC)

1/1

0010 1100 i i i i nnnn

ADU

WRn, #I

ACC

(WRn) + I

1/1

0010 1001 0xxx xxxx

ADUR

R, ACC

ACC, R

(R) + (ACC)

1/1

0010 1101 i i i i nnnn

ADUR

WRn, #I

ACC, WRn

(WRn) + I

1/1

0001 1010 0xxx xxxx

SUB

R, ACC

ACC

(R) - (ACC)

ZF, CF

1/1

0001 1110 i i i i nnnn

SUB

WRn, #I

ACC

(WRn) - I

ZF, CF

1/1

0001 1011 0xxx xxxx

SUBR

R, ACC

ACC, R

(R) - (ACC)

ZF, CF

1/1

0001 1111 i i i i nnnn

SUBR

WRn, #I

ACC, WR

(WR) - I

ZF, CF

1/1

0000 1010 0xxx xxxx

SBC

R, ACC

ACC

(R) - (ACC) - (CF)

ZF, CF

1/1

0000 1110 i i i i nnnn

SBC

WRn, #I

ACC

(WRn) - I - (CF)

ZF, CF

1/1

0000 1011 0xxxxxxx

SBCR

R, ACC

ACC, R

(R) - (ACC) - (CF)

ZF, CF

1/1

0000 1111 i i i i nnnn

SBCR

WRn, #I

ACC, WRn

(WRn) - I - (CF)

ZF, CF

1/1

0100 1010 0xxx xxxx

INC

ACC, R

(R) + 1

ZF, CF

1/1

0100 1010 1xxx xxxx

DEC

ACC, R

(R) - 1

ZF, CF

1/1

W742C818

Publication Release Date: October 2000

- 50 - Revision A2

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected W/C

Logic

0010 1010 0xxx xxxx

ANL

R, ACC

ACC

(R) & (ACC)

1/1

0010 1110 i i i i nnnn

ANL

WRn, #I

ACC

(WRn) & I

1/1

0010 1011 0xxx xxxx

ANLR

R, ACC

ACC, R

(R) & (ACC)

1/1

0010 1111 i i i i nnnn

ANLR

WRn, #I

ACC, WRn

(WRn) & I

1/1

0011 1010 0xxx xxxx

ORL

R, ACC

ACC

(R)

(ACC)

1/1

0011 1110 i i i i nnnn

ORL

WRn, #I

ACC

(WRn)

1/1

0011 1011 0xxx xxxx

ORLR

R, ACC

ACC, R

(R)

(ACC)

1/1

0011 1111 i i i i nnnn

ORLR

WRn, #I

ACC, WRn

(WRn)

1/1

0011 1000 0xxx xxxx

XRL

R, ACC

ACC

(R) EX (ACC)

1/1

0011 1100 i i i i nnnn

XRL

WRn, #I

ACC

(WRn) EX I

1/1

0011 1001 0xxx xxxx

XRLR

R, ACC

ACC, R

(R) EX (ACC)

1/1

0011 1101 i i i i nnnn

XRLR

WRn, #I

ACC, WRn

(WRn) EX I

1/1

Branch

0111 0

aaa aaaa aaaa

JMP

PC13~PC0

(ROMPR)

�

800H+L10~L0

1/1

1000 0

aaa aaaa aaaa

JB0

PC10~PC0

L10~L0; if ACC.0 = "1"

1/1

1001 0

aaa aaaa aaaa

JB1

PC10~PC0

L10~L0; if ACC.1 = "1"

1/1

1010 0

aaa aaaa aaaa

JB2

PC10~PC0

L10~L0; if ACC.2 = "1"

1/1

1011 0

aaa aaaa aaaa

JB3

PC10~PC0

L10~L0; if ACC.3 = "1"

1/1

1110 0

aaa aaaa aaaa

PC10~PC0

L10~L0; if ACC = 0

1/1

1100 0

aaa aaaa aaaa

JNZ

PC10~PC0

L10~L0; if ACC ! = 0

1/1

1111 0

aaa aaaa aaaa

PC10~PC0

L10~L0; if CF = "1"

1/1

1101 0

aaa aaaa aaaa

JNC

PC10~PC0

L10~L0; if CF != "1"

1/1

0100 1000 0xxx xxxx

DSKZ

ACC, R

(R) - 1; PC

(PC) + 2 if ACC = 0

ZF, CF

1/1

0100 1000 1xxx xxxx

DSKNZ R

ACC, R

(R) - 1; PC

(PC) + 2 if ACC != 0

ZF, CF

1/1

1010 1000 0xxx xxxx

SKB0

(PC) + 2 if R.0 = "1"

1/1

1010 1000 1xxx xxxx

SKB1

(PC) + 2 if R.1 = "1"

1/1

1010 1001 0xxx xxxx

SKB2

(PC) + 2 if R.2 = "1"

1/1

1010 1001 1xxx xxxx

SKB3

(PC) + 2 if R.3 = "1"

1/1

W742C818

Publication Release Date: October 2000

- 52 - Revision A2

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

Data move

1110 1nnn nxxx xxxx

MOV

WRn, R

WRn

(R)

1/1

1111 1nnn nxxx xxxx

MOV

R, WRn

(WRn)

1/1

0110 1nnn nxxx xxxx

MOVA

WRn, R

ACC, WRn

(R)

1/1

0111 1nnn nxxx xxxx

MOVA

R, WRn

ACC, R

(WRn)

1/1

0101 1001 1xxx xxxx

MOV

R, ACC

(ACC)

1/1

0100 1110 1xxx xxxx

MOV

ACC, R

ACC

(R)

1/1

1011 1 i i i i xxx xxxx

MOV

R, #I

1/1

1100 1nnn n000 qqqq

MOV

WRn, @WRq WRn

[(DBKRH)x800H+(DBKRL)

�

80H+(PA

GE)x10H +(WRq)]

1/2

1101 1nnn n000 qqqq

MOV

@WRq, WRn [(DBKRH)x800H+(DBKRL)

�

80H+(PAGE)x10

H +(WRq)]

WRn

1/2

1000 1100 0xxx xxxx

MOV

TAB0, R

TAB0

(R)

1/1

1000 1100 1xxx xxxx

MOV

TAB1, R

TAB1

(R)

1/1

1000 1110 0xxx xxxx

MOV

TAB2, R

TAB2

(R)

1/1

1000 1110 1xxx xxxx

MOV

TAB3, R

TAB3

(R)

1/1

1000 1101 0xxx xxxx

MOVC

[(TAB3)

�

1000H+(TAB2)

�

100H+(TAB1)

x10H + (TAB0)]/4

1/2

Input & Output

0101 1011 0xxx xxxx

MOVA

R, RA

ACC, R

[RA]

1/1

0101 1011 1xxx xxxx

MOVA

R, RB

ACC, R

[RB]

1/1

0100 1011 0xxx xxxx

MOVA

R, RC

ACC, R

[RC]

1/1

0100 1011 1xxx xxxx

MOVA

R, RD

ACC, R

[RD]

1/1

0101 1100 0xxx xxxx

MOVA

R, P0

ACC, R

[P0]

1/1

0101 1100 0xxx xxxx

MOVA

R, P1

ACC, R

[P1]

1/1

0101 1010 0xxx xxxx

MOV

RA, R

[RA]

(R)

1/1

0101 1010 1xxx xxxx

MOV

RB, R

[RB]

(R)

1/1

1010 1100 0xxx xxxx

MOV

RC, R

[RC]

(R)

1/1

1010 1100 1xxx xxxx

MOV

RD, R

[RD]

(R)

1/1

0101 1110 0xxx xxxx

MOV

RE, R

[RE]

(R)

1/1

1010 1110 0xxx xxxx

MOV

RF, R

[RF]

(R)

1/1

1010 1101 0xxx xxxx

MOV

P0, R

[P0]

(R)

1/1

0001 0010 i i i i i i i i

MOV

MFP, #I

[MFP]

1/1

W742C818

Publication Release Date: October 2000

- 53 - Revision A2

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

Flag & Register

0101 1111 1xxx xxxx

MOVA

R, PAGE

ACC, R

PAGE (Page Register)

1/1

0101 1110 1xxx xxxx

MOV

PAGE, R

PAGE

(R)

1/1

0101 0110 1000 0i i i

MOV

PAGE, #I

PAGE

1/1

1001 1101 1xxx xxxx

MOV

R, WRP

WRP

1/1

1001 1100 1xxx xxxx

MOV

WRP, R

WRP

(R)

1/1

0011 0101 1000 i i i i

MOV

WRP, #I

WRP

1/1

0011 0101 0000 i i i i

MOV

DBKRL, #I

DBKRL

1/1

0011 0101 0100 000 i

MOV

DBKRH, #I

DBKRH

1/1

1001 1101 0000nnnn

MOV

WRn,DBKRL

WRn

DBKRL

1/1

1001 1101 0100nnnn

MOV

WRn,DBKRH WRn

DBKRH

1/1

1001 1100 0000nnnn

MOV

DBKRL, WRn DBKRL

WRn

1/1

1001 1100 0100nnnn

MOV

DBKRH, WRn DBKRH

WRn

1/1

0011 0100 0000 0 i i i

MOV

ROMPR, #I

ROMPR

1/1

1000 1000 0xxx xxxx

MOV

ROMPR, R

ROMPR

(R)

1/1

1000 1001 0xxx xxxx

MOV

R, ROMPR

(ROMPR)

1/1

0001 0011 1000 i 0 0 i

MOV

MR0, #I

MR0

1/1

0001 0011 0000 i i i i

MOV

MR1, #I

MR1

1/1

0101 1001 0xxx xxxx

MOVA

R, CF

ACC.0, R.0

1/1

0101 1000 0xxx xxxx

MOV

CF, R

(R.0)

1/1

0100 1001 0xxx xxxx

MOVA

R, HCFL

ACC, R

HCF.0~HCF.3

1/1

0100 1001 1xxx xxxx

MOVA

R, HCFH

ACC, R

HCF.4~HCF.7

1/1

0101 0011 0000 i i i i

MOV

PM0, #I

Port Mode 0

1/1

0101 0111 0000 i i i i

MOV

PM1, #I

Port Mode 1

1/1

0101 0111 1000 i i i i

MOV

PM2, #I

Port Mode 2

1/1

0011 0111 0000 i i i i

MOV

PM4, #I

Port Mode 4

1/1

0011 0111 1000 i i i i

MOV

PM5, #I

Port Mode 5

1/1

0101 0011 1000 i i i i

MOV

PM6, #I

Port Mode 6

1/1

0100 0000 i 0 0 i i i i i

CLR

EVF, #I

Clear Event Flag if In = 1

1/1

0011 0000 0000 0000

CLR

EVFD

Clear RD Event Flag if In = 1

1/1

W742C818

Publication Release Date: October 2000

- 54 - Revision A2

Instruction set, continued

Machine code

Mnemonic

Function

Flag affected

W/C

Flag & Register

0101 1101 0xxx xxxx

MOVA

R, EVFL

ACC, R

EVF.0 - EVF.3

1/1

0101 1101 1xxx xxxx

MOVA

R, EVFH

ACC, R

EVF.4 - EVF.7

1/1

0100 0001 ii ii i i i i

MOV

HEF, #I

Set/Reset HOLD mode release Enable Flag

1/1

0011 0001 0000 000 i

MOV

HEFD,#I

Set/Reset RD HOLD mode release Enable
Flag

1/1

0101 0001 i i i i i i i i

MOV

IEF, #I

Set/Reset Interrupt Enable Flag

1/1

0100 0011 0000 i i i i

MOV

PEF, #I

Set/Reset Port Enable Flag

1/1

0011 0011 0000 i i 00

MOV

P1EF, #I

Set/Reset P1 Port Enable Flag

1/1

0101 0010 i i i i i i i i

MOV

SEF, #I

Set/Reset STOP mode wake-up Enable Flag
for RC,RD port

1/1

0101 0100 0000 i i i i

MOV

SCR, #I

SCR

1/1

0100 1111 0xxx xxxx

MOVA

R, PSR0

ACC, R

Port Status Register 0

1/1

0100 1111 1xxx xxxx

MOVA

R, PSR1

ACC, R

Port Status Register 1

1/1

0101 1111 0xxx xxxx

MOVA

R, PSR2

ACC, R

Port Status Register 2

1/1

0100 0010 0000 0000

CLR

PSR0

Clear Port Status Register 0

1/1

0100 0010 1000 0000

CLR

PSR1

Clear Port Status Register 1

1/1

0100 0010 1100 0000

CLR

PSR2

Clear Port Status Register 2

1/1

0101 0000 0100 0000

SET

Set Carry Flag

1/1

0101 0000 0000 0000

CLR

Clear Carry Flag

1/1

0001 0111 0000 0000

CLR

DIVR0

Clear the last 4-bit of the Divider 0

1/1

0101 0101 1000 0000

CLR

DIVR1

Clear the last 4-bit of the Divider 1

1/1

0001 0111 1000 0000

CLR

WDT

Clear WatchDog Timer

1/1

Shift & Rotate

0100 1101 0xxx xxxx

SHRC

ACC.n, R.n

(R.n+1);

ACC.3, R.3

0; CF

R.0

ZF, CF

1/1

0100 1101 1xxx xxxx

RRC

ACC.n, R.n

(R.n+1);

ACC.3, R.3

CF; CF

R.0

ZF, CF

1/1

0100 1100 0xxx xxxx

SHLC

ACC.n, R.n

(R.n-1);

ACC.0, R.0

0; CF

R.3

ZF, CF

1/1

0100 1100 1xxx xxxx

RLC

ACC.n, R.n

(R.n-1);

ACC.0, R.0

CF; CF

R.3

ZF, CF

1/1

W742C818

Publication Release Date: October 2000

- 55 - Revision A2

Instruction set, continued

Machine code

Mnemonic Function

Flag affected

W/C

LCD

1001 1000 0xxx xxxx

MOV

LPL, R

LPL

(R)

1/1

1001 1000 1xxx xxxx

MOV

LPH, R

LPH

(R)

1/1

1001 1010 0xxx xxxx

MOV

@LP, R

[(LPH)

�

10H+(LPL)]

(R)

1/1

1001 1011 0xxx xxxx

MOV

R, @LP

[

(LPH)

�

10H+(LPL)]

1/1

0000 0010 0000 0000

LCDON

LCD ON

1/1

0000 0010 1000 0000

LCDOFF

LCD OFF

1/1

0000 0011 0000 0 i i i

MOV

LCDCC, #I

LCD contrast control

1/1

Serial I/O

0011 0010 0000 i i i i

MOV

SIC, #I

Serial Interface Control

1/1

1010 1111 0xxx xxxx

SOP

P0.1

R(high nibble),A(low nibble) Serially

1/1

1001 1111 0xxx xxxx

SIP

R(high nibble), A(low nibble)

P0.1 Serially

1/1

DTMF

0011 0100 1000 i i i i

MOV

DTCR, #I

DTMF Enable Control

1/1

1001 1110 1xxx xxxx

MOV

DTMF, R

Select DTMF frequency

1/1

Timer

1010 1010 0xxx xxxx

MOV

TM0L, R

TM0L

(R)

1/1

1010 1010 1xxx xxxx

MOV

TM0H, R

TM0H

(R)

1/1

1010 1011 0xxx xxxx

MOV

TM1L, R

TM1L

(R)

1/1

1010 1011 1xxx xxxx

MOV

TM1H, R

TM1H

(R)

1/1

1000 1111 0xxx xxxx

MOV

R, TM0L

(R)

TM0L

1/1

1000 1111 1xxx xxxx

MOV

R, TM0H

(R)

TM0H

1/1

1001 1001 0xxx xxxx

MOV

R, TM1L

(R)

TM1L

1/1

1001 1001 1xxx xxxx

MOV

R, TM1H

(R)

TM1H

1/1

Other

0000 0000 1000 0000

HOLD

Enter Hold mode

1/1

0000 0000 1100 0000

STOP

Enter Stop mode

1/1

0000 0000 0000 0000

NOP

No operation

1/1

0101 0000 1100 0000

INT

Enable interrupt function

1/1

0101 0000 1000 0000

DIS

INT

Disable interrupt function

1/1

Электронный компонент: W742C818