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Электронный компонент: W78C33

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Preliminary W78C33B
8-BIT MICROCONTROLLER
Publication Release Date: June 1998
- 1 -
Revision A1
GENERAL DESCRIPTION
The W78C33B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is functional compatible with the industry standard 80C32 microcontroller series except
the one extra 4-bit bit-addressable I/O port (Port 4).
The W78C33B contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C33B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
8-bit CMOS microcontroller
Fully static design
Low standby current at full supply voltage
DC-40 MHz operation
256 bytes of on-chip scratchpad RAM
ROMless operation
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
One extra
4-bit bidirectional port
Three 16-bit timer/counters
One full duplex serial port
Boolean processor
Six-
source, two-level interrupt capability
Built-in power management
Packages:
-
PLCC 44: W78C33BP-24/40
-
QFP 44: W78C33BF-24/40
-
TQFP 44: W78C33BM-24/40
Preliminary W78C33B
- 2 -
PIN CONFIGURATIONS
44-Pin QFP/TQFP (W78C33BF/W78C33BM)
34
40 39 38 37 36 35
44 43 42 41
33
32
31
30
29
28
27
26
25
24
23
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
22
21
20
19
18
17
16
15
14
13
12
11
4
3
2
1
8
7
6
5
10
9
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
1
.
2
V
C
C
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
T
2
E
X
,
P
1
.
1
P
1
.
3
P
1
.
4
P
4
.
0
P
4
.
2
P4.1
P4.3
44-Pin PLCC (W78C33BP)
40
2 1 44 43 42 41
6 5
4 3
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
10
9
8
7
14
13
12
11
16
15
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
1
.
2
V
C
C
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
T
2
E
X
,
P
1
.
1
P
1
.
3
P
1
.
4
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P4.1
P
4
.
0
P4.3
P
4
.
2
Preliminary W78C33B
Publication Release Date: June 1998
- 3 -
Revision A1
PIN DESCRIPTION
P0.0
-
P0.7
Port 0, Bits 0 through 7. Port 0 is a bi-directional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0
-
P1.7
Port 1, Bits 0 through 7. Port 1 is a bi-directional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0
-
P2.7
Port 2, Bits 0 through 7. Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0
-
P3.7
Port 3, Bits 0 through 7. Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
ALTERNATE FUNCTION
P3.0
RXD Serial Receive Data
P3.1
TXD Serial Transmit Data
P3.2
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
P3.4
T0 Timer 0 Input
P3.5
T1 Timer 1 Input
P3.6
WR Data Write Strobe
P3.7
RD Data Read Strobe
P4.0
-
P4.3
Port 4, Bits 0 through 3. Port 4 is a bi-directional I/O port with internal pull-ups.
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C33B operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
Preliminary W78C33B
- 4 -
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
PSEN
Program Store Enable Output, active low.
PSEN
enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations.
PSEN
goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
V
SS
, V
CC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P3.0
~
P3.7
P1.0
~
P1.7
ALU
Port 0
Latch
Port 1
Latch
Timer
1
Timer
0
Timer
2
Port
1
UART
XTAL1
PSEN
ALE
GND
VCC
RST
XTAL2
Oscillator
Interrupt
PSW
Instruction
Decoder
&
Sequencer
Reset Block
Bus & Clock
Controller
SFR RAM
Address
Power control
256 bytes
RAM & SFR
Stack
Pointer
B
Addr. Reg.
Incrementor
PC
DPTR
Temp Reg.
T2
T1
ACC
Port 3
Latch
Port 4
Latch
Port
3
Port 2
Latch
P4.0
~
P4.3
Port
4
Port
0
Port
2
P2.0
~
P2.7
P0.0
~
P0.7
Preliminary W78C33B
Publication Release Date: June 1998
- 5 -
Revision A1
FUNCTIONAL DESCRIPTION
The W78C33B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the
W78C33B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78C33B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C33B relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C33B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Preliminary W78C33B
- 6 -
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C33B is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1.
Example: P4
REG
0D8H
MOV
P4, #0AH
; Output data "A" through P4.0
-
P4.3.
MOV
A, P4
; Read P4 status to Accumulator.
SETB
P4.0
; Set bit P4.0
CLR
P4.1
; Clear bit P4.1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
DC Power Supply
V
CC
-
V
SS
-0.3
+7.0
V
Input Voltage
V
IN
V
SS
-0.3
V
CC
+0.3
V
Operating Temperature
T
A
0
70
C
Storage Temperature
T
ST
-55
+150
C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Preliminary W78C33B
Publication Release Date: June 1998
- 7 -
Revision A1
DC CHARACTERISTICS
(V
DD
-V
SS
= 5V
10%, T
A
= 25
C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
Operating Voltage
V
DD
4.5
5.5
V
Operating Current
I
DD
-
20
mA
No load
V
DD
= 5.5V
Idle Current
I
IDLE
-
6
mA
Idle mode
V
DD
= 5.5V
Power Down Current
I
PWDN
-
50
A
Power-down mode
V
DD
= 5.5V
Input Current
P1, P2, P3, P4
I
IN1
-50
+10
A
V
DD
= 5.5V
V
IN
= 0V or V
DD
Input Current
RST
I
IN2
-10
+300
A
V
DD
= 5.5V
0 < V
IN
< V
DD
Input Leakage Current
P0, EA
I
LK
-10
+10
A
V
DD
= 5.5V
0V <V
IN
< V
DD
Logic 1 to 0 Transition
Current
P1, P2, P3, P4
I
TL
[*4]
-500
-200
A
V
DD
= 5.5V
V
IN
=2.0V
Input Low Voltage
P0, P1, P2, P3, P4, EA
V
IL1
0
0.8
V
V
DD
= 4.5V
Input Low Voltage
RST
V
IL2
0
0.8
V
V
DD
= 4.5V
Input Low Voltage
XTAL1[*4]
V
IL3
0
0.8
V
V
DD
= 4.5V
Input High Voltage
P0, P1, P2, P3, P4, EA
V
IH1
2.4
V
DD
+0.2
V
V
DD
= 5.5V
Input High Voltage
RST
V
IH2
3.5
V
DD
+0.2
V
V
DD
= 5.5V
Input High Voltage
XTAL1 [*4]
V
IH3
3.5
V
DD
+0.2
V
V
DD
= 5.5V
Output Low Voltage
P1, P2, P3, P4
V
OL1
-
0.45
V
V
DD
= 4.5V
I
OL
= +2 mA
Preliminary W78C33B
- 8 -
DC Characteristics, continued
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
Output Low Voltage
P0, ALE, PSEN [*3]
V
OL2
-
0.45
V
V
DD
= 4.5V
I
OL
= +4mA
Sink Current
P1, P2, P3, P4
I
SK1
4
8
mA
V
DD
= 4.5V
Vs = 0.45V
Sink Current
P0, ALE, PSEN
I
SK2
10
14
mA
V
DD
= 4.5V
Vs = 0.45V
Output High Voltage
P1, P2, P3, P4
V
OH1
2.4
-
V
V
DD
= 4.5V
I
OH
= -100
A
Output High Voltage
P0, ALE, PSEN [*3]
V
OH2
2.4
-
V
V
DD
= 4.5V
I
OH
= -400
A
Source Current
P1, P2, P3, P4
I
SR1
-120
-180
A
V
DD
= 4.5V
Vs = 2.4V
Source Current
P0, ALE, PSEN
I
SR2
-10
-14
mA
V
DD
= 4.5V
Vs = 2.4V
Notes:
*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 K
.
*3. P0, ALE and /PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V
IN
approximates to 2V.
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
CP
), and actual parts will
usually experience less than a
20 nS variation. The numbers below represent the performance
expected from a 1.2 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
Preliminary W78C33B
Publication Release Date: June 1998
- 9 -
Revision A1
Continued
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
F
OP
0
-
40
MHz
1
Clock Period
T
CP
25
-
-
nS
2
Clock High
T
CH
10
-
-
nS
3
Clock Low
T
CL
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
T
AAS
1 T
CP
-
-
-
nS
4
Address Hold after ALE Low
T
AAH
1 T
CP
-
-
-
nS
1, 4
ALE Low to PSEN Low
T
APL
1 T
CP
-
1Tcp
1Tcp+
nS
4
PSEN Low to Data Valid
T
PDA
-
-
2 T
CP
nS
2
Data Hold after PSEN High
T
PDH
0
-
1 T
CP
nS
3
Data Float after PSEN High
T
PDZ
0
-
1 T
CP
nS
ALE Pulse Width
T
ALW
2 T
CP
-
2 T
CP
-
nS
4
PSEN
Pulse Width
T
PSW
3 T
CP
-
3 T
CP
-
nS
4
Notes:
1. P0.0
-
P0.7, P2.0
-
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to PSEN going high.
4. "
" ( due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
T
DAR
3 T
CP
-
-
3 T
CP+
nS
1, 2
RD Low to Data Valid
T
DDA
-
-
4 T
CP
nS
1
Data Hold after RD High
T
DDH
0
-
2 T
CP
nS
Data Float after RD High
T
DDZ
0
-
2 T
CP
nS
RD Pulse Width
T
DRD
6 T
CP
-
6 T
CP
-
nS
2
Notes:
1. Data memory access time is 8 T
CP
.
2. "
" (due to buffer driving delay and wire loading) is 20 nS.
Preliminary W78C33B
- 10 -
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
T
DAW
3 T
CP
-
-
3 T
CP+
nS
Data Valid to WR Low
T
DAD
1 T
CP
-
-
-
nS
Data Hold from WR High
T
DWD
1 T
CP
-
-
-
nS
WR Pulse Width
T
DWR
6 T
CP
-
6 T
CP
-
nS
Note: "
" ( due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
T
PDS
1 T
CP
-
-
nS
Port Input Hold from ALE Low
T
PDH
0
-
-
nS
Port Output to ALE
T
PDA
1 T
CP
-
-
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
TIMING WAVEFORMS
Program Fetch Cycle
S1
XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PORT 2
A0-A7
A0-A7
Data
A0-A7
Code
T
A0-A7
Data
Code
PORT 0
PSEN
PDH,
T
PDZ
T
PDA
T
AAH
T
AAS
T
PSW
T
APL
T
ALW
Preliminary W78C33B
Publication Release Date: June 1998
- 11 -
Revision A1
Timing Waveforms, continued
Data Read Cycle
S2
S3
S5
S6
S1
S2
S3
S4
S5
S6
S1
S4
XTAL1
ALE
PSEN
DATA
A8-A15
PORT 2
PORT 0
A0-A7
RD
T
DDH,
T
DDZ
T
DDA
T
DRD
T
DAR
Data Write Cycle
S2
S3
S5
S6
S1
S2
S3
S4
S1
S5
S6
S4
XTAL1
ALE
PSEN
A8-A15
DATA OUT
PORT 2
PORT 0
A0-A7
WR
T
T
DAW
DAD
T
DWR
T
DWD
Preliminary W78C33B
- 12 -
Timing Waveforms, continued
Port Access Cycle
XTAL1
ALE
S5
S6
S1
DATA OUT
T
T
PORT
INPUT
T
SAMPLE
PDA
PDH
PDS
Preliminary W78C33B
Publication Release Date: June 1998
- 13 -
Revision A1
TYPICAL APPLICATION CIRCUIT
Using External Program Memory and Crystal
AD0
A0
A0
A0
10
A1
9
A2
8
A3
7
A4
6
A5
5
A6
4
A7
3
A8
25
A9
24
A10
21
A11
23
A12
2
A13
26
A14
27
A15
1
CE
20
OE
22
O0 11
O1 12
O2 13
O3 15
O4 16
O5 17
O6 18
O7 19
27512
AD0
D0
3
Q0 2
D1
4
Q1 5
D2
7
Q2 6
D3
8
Q3 9
D4
13
Q4 12
D5
14
Q5 15
D6
17
Q6 16
D7
18
Q7 19
OC
1
G
11
74LS373
AD0
EA
35
XTAL1
21
XTAL2
20
RST
10
INT0
14
INT1
15
T0
16
T1
17
P1.0
2
P1.1
3
P1.2
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
19
WR
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
18
PSEN 32
ALE
33
TXD
13
RXD
11
W78C33BP
10 u
8.2 K
V
CRYSTAL
C1
C2
R
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
A1
A2
A3
A4
A5
A6
A7
A1
A2
A3
A4
A5
A6
A7
A8
A9
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A10
A11
A12
A13
A14
A15
GND
A9
A10
A11
A12
A13
A14
A15
CC
P4.0
P4.1
P4.2
P4.3
44-pin PLCC
23
34
1
12
Figure A
CRYSTAL
C1
C2
R
16 MHz
30P
30P
-
24 MHz
15P
15P
-
33 MHz
10P
10P
6.8K
40 MHz
5P
5P
6.8K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
Preliminary W78C33B
- 14 -
PACKAGE DIMENSIONS
44-pin PLCC
44
40
39
29
28
18
17
7
6
1
L
c
1
b
2
A
H
D
D
e
b
E
H
E
y
A
A
1
Seating Plane
D
G
G
E
Symbol
Min. Nom.
Max.
Max.
Nom.
Min.
Dimension in inch
Dimension in mm
A
b
c
D
e
H
E
L
y
A
A
1
2
E
b
1
H
D
G
G
D
E
Notes:
on final visual inspection spec.
4. General appearance spec. should be based
3. Controlling dimension: Inches
protrusion/intrusion.
2. Dimension b1 does not include dambar
flash.
1. Dimension D & E do not include interlead
0.020
0.145
0.026
0.016
0.008
0.648
0.590
0.680
0.090
0.150
0.028
0.018
0.010
0.653
0.610
0.690
0.100
0.050
BSC
0.185
0.155
0.032
0.022
0.014
0.658
0.630
0.700
0.110
0.004
0.508
3.683
0.66
0.406
0.203
16.46
14.99
17.27
2.296
3.81
0.711
0.457
0.254
16.59
15.49
17.53
2.54
1.27
4.699
3.937
0.813
0.559
0.356
16.71
16.00
17.78
2.794
0.10
BSC
16.71
16.59
16.46
0.658
0.653
0.648
16.00
15.49
14.99
0.630
0.610
0.590
17.78
17.53
17.27
0.700
0.690
0.680
44-pin QFP
Seating Plane
11
22
12
See Detail F
e
b
A
y
1
A
A
L
L
1
c
E
E
H
1
D
44
H
D
34
33
Detail F
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
0.254
0.101
0.010
0.004
Notes:
Symbol
Min.
Nom.
Max.
Max.
Nom.
Min.
Dimension in inch
Dimension in mm
A
b
c
D
e
H
D
H
E
L
y
A
A
L
1
1
2
E
0.006
0.152
---
0.002
0.075
0.01
0.081
0.014
0.087
0.018
1.90
0.25
0.05
2.05
0.35
2.20
0.45
0.390
0.025
0.063
0.003
0
7
0.394
0.031
0.398
0.037
9.9
0.80
0.65
1.6
10.00
0.8
10.1
0.95
0.398
0.394
0.390
0.530
0.520
0.510
13.45
13.2
12.95
10.1
10.00
9.9
7
0
0.08
0.031
0.01
0.02
0.25
0.5
---
---
---
---
---
2
0.025
0.036
0.635
0.952
0.530
0.520
0.510
13.45
13.2
12.95
0.051
0.075
1.295
1.905
Preliminary W78C33B
Publication Release Date: June 1998
- 15 -
Revision A1
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.