Preliminary W78C33B

8-BIT MICROCONTROLLER

Publication Release Date: June 1998

- 1 -

Revision A1

GENERAL DESCRIPTION

The W78C33B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is functional compatible with the industry standard 80C32 microcontroller series except
the one extra 4-bit bit-addressable I/O port (Port 4).

The W78C33B contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.

The W78C33B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

8-bit CMOS microcontroller

Fully static design

Low standby current at full supply voltage

DC-40 MHz operation

256 bytes of on-chip scratchpad RAM

ROMless operation

64K bytes program memory address space

64K bytes data memory address space

Four 8-bit bidirectional ports

One extra

4-bit bidirectional port

Three 16-bit timer/counters

One full duplex serial port

Boolean processor

Six-

source, two-level interrupt capability

Built-in power management

Packages:

PLCC 44: W78C33BP-24/40

QFP 44: W78C33BF-24/40

TQFP 44: W78C33BM-24/40

Preliminary W78C33B

- 2 -

PIN CONFIGURATIONS

44-Pin QFP/TQFP (W78C33BF/W78C33BM)

40 39 38 37 36 35

44 43 42 41

33
32

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

P
4
.
0

P
4
.
2

P4.1

P4.3

44-Pin PLCC (W78C33BP)

2 1 44 43 42 41

6 5

4 3

39
38

30
29

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P4.1

P
4
.
0

P4.3

P
4
.
2

Preliminary W78C33B

Publication Release Date: June 1998

- 3 -

Revision A1

PIN DESCRIPTION

P0.0

P0.7

Port 0, Bits 0 through 7. Port 0 is a bi-directional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0

P1.7

Port 1, Bits 0 through 7. Port 1 is a bi-directional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.

P2.0

P2.7

Port 2, Bits 0 through 7. Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0

P3.7

Port 3, Bits 0 through 7. Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN

ALTERNATE FUNCTION

P3.0

RXD Serial Receive Data

P3.1

TXD Serial Transmit Data

P3.2

INT0 External Interrupt 0

P3.3

INT1 External Interrupt 1

P3.4

T0 Timer 0 Input

P3.5

T1 Timer 1 Input

P3.6

WR Data Write Strobe

P3.7

RD Data Read Strobe

P4.0

P4.3

Port 4, Bits 0 through 3. Port 4 is a bi-directional I/O port with internal pull-ups.

External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C33B operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

Preliminary W78C33B

- 4 -

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.

PSEN

Program Store Enable Output, active low.

PSEN enables the external ROM onto the Port 0

address/data bus during fetch and MOVC operations.

PSEN goes to a high state during reset with a

weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

, V

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

P3.0
~
P3.7

P1.0

P1.7

ALU

Port 0

Latch

Port 1

Latch

Timer

Port

UART

XTAL1

PSEN

ALE

GND

VCC

RST

XTAL2

Oscillator

Interrupt

PSW

Instruction

Decoder

Sequencer

Reset Block

Bus & Clock

Controller

SFR RAM

Address

Power control

256 bytes

RAM & SFR

Stack

Pointer

Addr. Reg.

Incrementor

DPTR

Temp Reg.

ACC

Port 3

Latch

Port 4

Latch

Port

Port 2

Latch

P4.0
~
P4.3

Port

Port
0

Port
2

P2.0
~
P2.7

P0.0
~
P0.7

Preliminary W78C33B

Publication Release Date: June 1998

- 5 -

Revision A1

FUNCTIONAL DESCRIPTION

The W78C33B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the

W78C33B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.

Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

Clock

The W78C33B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C33B relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C33B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Preliminary W78C33B

- 6 -

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C33B is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1.

Example: P4

REG

0D8H

MOV

P4, #0AH

; Output data "A" through P4.0

P4.3.

MOV

A, P4

; Read P4 status to Accumulator.

SETB

P4.0

; Set bit P4.0

CLR

P4.1

; Clear bit P4.1

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3

+7.0

Input Voltage

-0.3

+0.3

Operating Temperature

Storage Temperature

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

Preliminary W78C33B

Publication Release Date: June 1998

- 7 -

Revision A1

DC CHARACTERISTICS

-V

= 5V

10%, T

= 25

C, Fosc = 20 MHz, unless otherwise specified.)

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Operating Voltage

4.5

5.5

Operating Current

No load

= 5.5V

Idle Current

IDLE

Idle mode

= 5.5V

Power Down Current

PWDN

Power-down mode

= 5.5V

Input Current

P1, P2, P3, P4

IN1

-50

+10

= 5.5V

= 0V or V

Input Current

RST

IN2

-10

+300

= 5.5V

0 < V

< V

Input Leakage Current

P0,

-10

+10

= 5.5V

0V <V

< V

Logic 1 to 0 Transition
Current

P1, P2, P3, P4

[*4]

-500

-200

= 5.5V

=2.0V

Input Low Voltage

P0, P1, P2, P3, P4,

IL1

0.8

= 4.5V

Input Low Voltage

RST

IL2

0.8

= 4.5V

Input Low Voltage

XTAL1[*4]

IL3

0.8

= 4.5V

Input High Voltage

P0, P1, P2, P3, P4,

IH1

2.4

+0.2

= 5.5V

Input High Voltage

RST

IH2

3.5

+0.2

= 5.5V

Input High Voltage

XTAL1 [*4]

IH3

3.5

+0.2

= 5.5V

Output Low Voltage

P1, P2, P3, P4

OL1

0.45

= 4.5V

= +2 mA

Preliminary W78C33B

- 8 -

DC Characteristics, continued

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Output Low Voltage

P0, ALE, PSEN [*3]

OL2

0.45

= 4.5V

= +4mA

Sink Current

P1, P2, P3, P4

SK1

= 4.5V

Vs = 0.45V

Sink Current

P0, ALE, PSEN

SK2

= 4.5V

Vs = 0.45V

Output High Voltage

P1, P2, P3, P4

OH1

2.4

= 4.5V

= -100

Output High Voltage

P0, ALE, PSEN [*3]

OH2

2.4

= 4.5V

= -400

Source Current

P1, P2, P3, P4

SR1

-120

-180

= 4.5V

Vs = 2.4V

Source Current

P0, ALE, PSEN

SR2

-10

-14

= 4.5V

Vs = 2.4V

Notes:

*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 K

*3. P0, ALE and /PSEN are tested in the external access mode.

*4. XTAL1 is a CMOS input.

*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

approximates to 2V.

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T

), and actual parts will

usually experience less than a

20 nS variation. The numbers below represent the performance

expected from a 1.2 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

OP,

Preliminary W78C33B

Publication Release Date: June 1998

- 9 -

Revision A1

Continued

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

MHz

Clock Period

Clock High

Clock Low

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

Address Hold after ALE Low

AAH

1 T

1, 4

ALE Low to PSEN Low

APL

1 T

1Tcp

1Tcp+

PSEN Low to Data Valid

PDA

2 T

Data Hold after PSEN High

PDH

1 T

Data Float after PSEN High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN Pulse Width

PSW

3 T

Notes:

1. P0.0

P0.7, P2.0

P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.
4. "

" ( due to buffer driving delay and wire loading) is 20 nS.

Data Read Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

ALE Low to RD Low

DAR

3 T

CP+

1, 2

RD Low to Data Valid

DDA

4 T

Data Hold after RD High

DDH

2 T

Data Float after RD High

DDZ

2 T

RD Pulse Width

DRD

6 T

Notes:

1. Data memory access time is 8 T

2. "

" (due to buffer driving delay and wire loading) is 20 nS.

Preliminary W78C33B

- 10 -

Data Write Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to WR Low

DAW

3 T

CP+

Data Valid to WR Low

DAD

1 T

Data Hold from WR High

DWD

1 T

WR Pulse Width

DWR

6 T

Note: "

" ( due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

1 T

Port Input Hold from ALE Low

PDH

Port Output to ALE

PDA

1 T

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

TIMING WAVEFORMS

Program Fetch Cycle

XTAL1

ALE

PORT 2

A0-A7

Data

A0-A7

Code

A0-A7

Data

Code

PORT 0

PSEN

PDH,

PDZ

PDA

AAH

AAS

PSW

APL

ALW

Preliminary W78C33B

Publication Release Date: June 1998

- 13 -

Revision A1

TYPICAL APPLICATION CIRCUIT

Using External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

O0 11
O1 12
O2 13
O3 15
O4 16
O5 17
O6 18
O7 19

27512

AD0

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74LS373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

43
42
41

40
39
38

37
36

25
26
27

28
29
30
31

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN 32

ALE

TXD

RXD

W78C33BP

10 u

8.2 K

CRYSTAL

AD1
AD2
AD3
AD4
AD5
AD6

AD7

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3
A4
A5
A6
A7

A1
A2
A3
A4
A5
A6
A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10

A11
A12

A13

A14
A15

GND

A9
A10
A11
A12
A13
A14

A15

P4.0
P4.1
P4.2
P4.3

44-pin PLCC

23
34

Figure A

CRYSTAL

16 MHz

30P

24 MHz

15P

33 MHz

10P

6.8K

40 MHz

6.8K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

Preliminary W78C33B

- 14 -

PACKAGE DIMENSIONS

44-pin PLCC

Seating Plane

Symbol

Min. Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

44-pin QFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

Preliminary W78C33B

Publication Release Date: June 1998

- 15 -

Revision A1

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78C33BP-40

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78C33BP-40