W78C54

8-BIT MICROCONTROLLER

Publication Release Date: December 1997

- 1 -

Revision A2

GENERAL DESCRIPTION

The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal
ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM.

This device provides an enhanced architecture that makes it more powerful and suitable for a variety
of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate
large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,
three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator
clock circuits.

FEATURES

DC to 40 MHz extensive operating frequency

256-byte on-chip scratch pad RAM

16K-byte on-chip mask ROM

64K-byte address space for external Program Memory

64K-byte address space for external Data Memory

Three 16-bit timer/counters

Four 8-bit bit-addressable I/O ports

One extra 4-bit bit-addressable I/O port, additional INT2/ INT3
(Available on 44-pin PLCC/QFP package)

Eight-source, two priority-level interrupts

Low EMI emission mode

Built-in programmable power-saving modes - Idle mode & Power-down mode

Packages:

DIP 40: W78C54-16/24/40

PLCC 44: W78C54P-16/24/40

QFP 44: W78C54F-16/24/40

TQFP 44: W78C54M-16/24/40

W78C54

- 2 -

PIN CONFIGURATIONS

VCC

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA
ALE

PSEN

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

T2, P1.0

40-Pin DIP (W78C54)

P1.2

P1.3

P1.4

P1.5

P1.6

RXD, P3.0
TXD, P3.1

P1.7

RST

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

WR, P3.6

RD, P3.7

XTAL1

XTAL2

VSS

T2EX, P1.1

44-Pin PLCC (W78C54P)

44-Pin QFP/TQFP (W78C54F/W78C54M)

40 39 38 37 36 35

44 43 42 41

33
32

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

1 44 43 42 41

39
38

30
29

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P1.5

P1.6

P1.7

RST

RXD, P3.

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P
4
.
0

/
I
N
T
3
,
P
4
.
2

P4.1

P
4
.
0

INT2, P4.3

/
I
N
T
3
,
P
4
.
2

W78C54

Publication Release Date: December 1997

- 3 -

Revision A2

PIN DESCRIPTION

SYMBOL

TYPE

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out
of external ROM. The ROM address and data will not be present on the bus if

the

pin is high and the program counter is within the 16 KB area.

Otherwise they will be present on the bus.

PSEN

O H

PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus.

When internal ROM access is performed, no PSEN strobe signal outputs
originate from this pin.

ALE

O H

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.

RST

I L

RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.

XTAL1

CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.

XTAL2

CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: ground potential.

POWER SUPPLY: Supply voltage for operation.

P0.0

P0.7

I/O D

PORT 0: Function is the same as that of the standard 8052.

P1.0

P1.7

I/O H

PORT 1: Function is the same as that of the standard 8052.

P2.0

P2.7

I/O H

PORT 2: Function is the same as that of the standard 8052.

P3.0

P3.7

I/O H

PORT 3: Function is the same as that of the standard 8052.

P4.0

P4.3

I/O H

PORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal
pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt
(INT2/INT3) source input.

INT2 (P4.3)

I H

External interrupt 2: An extra interrupt input source. It cascades to pin P4.3
internally.

INT3 (P4.2)

I H

External interrupt 3: An extra interrupt input source. It cascades to pin P4.2
internally.

* Note :

TYPE

I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

W78C54

- 4 -

BLOCK DIAGRAM

P3.0
~
P3.7

P1.0
~
P1.7

ALU

Port 0

Latch

Port 1

Latch

Timer

Port

UART

XTAL1

PSEN

ALE

GND

VCC

RST

XTAL2

Oscillator

Interrupt

PSW

16KB
ROM

Instruction

Decoder

Sequencer

Reset Block

Bus & Clock

Controller

SFR RAM

Address

Power control

256 bytes

RAM & SFR

Stack

Pointer

Addr. Reg.

Incrementor

DPTR

Temp Reg.

ACC

Port 3

Latch

Port 4

Latch

Port

Port 2

Latch

P4.0

~
P4.3

Port

Port
0

Port
2

P2.0
~
P2.7

P0.0
~
P0.7

INT2

INT3

Figure 2. Architecture of the W78C54

W78C54

Publication Release Date: December 1997

- 5 -

Revision A2

FUNCTIONAL DESCRIPTION

The W78C54 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has
been replaced with 16K of internal mask ROM. The processor supports 111 different opcodes and
references both 64K program address space and 64K data storage space.

Clock

The W78C54 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78C54 relatively insensitive to duty cycle
variations in the clock.

Crystal Oscillator

The

W78C54

incorporates a built-in crystal oscillator. To make the oscillator work, a crystal is

connected across pins XTAL1 and XTAL2. In addition, a load capacitance of 30 pf (typically) must be
connected from each pin to ground. Resistor must also be connected from XTAL1 to XTAL2 to
provide a DC bias when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDLE bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the

W78C54

is used

with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

W78C54

- 6 -

1. INT2 / INT3

Two additional external interrupts, INT2 and INT3, whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

2. PORT4

Another bit-address port P4 is also available except only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources
(INT2/INT3).

Example:

REG

0D8H

MOV

P4, #0AH

; Output data "A" through P4.0

P4.3.

MOV

A, P4

; Read P4 status to Accumulator.

SETB

P4.0

; Set bit P4.0

CLR

P4.1

; Clear bit P4.1

Reduce EMI Emission

Because of the large on-chip mask-ROM, when a program is running in internal ROM space, the ALE
will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI
emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the
AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program
accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will
turn off again after it has been completely accessed or the program returns to internal ROM code
space..

POF Flag

The Power-Off-Reset flag is set by on-chip circuitry when the V

level rises from 0 to 5V. The POF

bit can be set/cleared by software allowing a user to determine if the reset is the result of a power-on
or a warm up by external reset. To avoid effect of POF flag, the power voltage must remain above
3V.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78C52C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

W78C54

Publication Release Date: December 1997

- 7 -

Revision A2

DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS)

SYM.

DEFINITION

ADDR.

MSB BIT ADDRESS, SYMBOL LSB

RESET

B register

F0H

(F7)

(F6)

(F5)

(F4)

(F3)

(F2)

(F1)

(F0)

00000000B

ACC

Accumulator

E0H

(E7)

(E6)

(E5)

(E4)

(E3)

(E2)

(E1)

(E0)

00000000B

P4*

Port 4

D8H

(DB)

INT2

(DA)

INT3

(D9)

(D8)

xxxx0000B

PSW

Program status word

D0H

(D7)

(D6)

(D5)

(D4)

RS1

(D3)

RS0

(D2)

(D1)

(D0)

00000000B

TH2

T2 reg. high

CDH

00000000B

TL2

T2 reg. low

CCH

00000000B

RCAP2H

T2 capture high

CBH

00000000B

RCAP2L

T2 capture low

CAH

00000000B

T2CON

Timer 2 control

C8H

(CF)

TF2

(CE)

EXF2

(CD)

RCLK

(CC)

TCLK

(CB)

EXEN2

(CA)

TR2

(C9)

C/T2

(C8)

CP/RL2

00000000B

XICON*

External interrupt
control

C0H

(C7)

PX3

(C6)

EX3

(C5)

IE3

(C4)

IT3

(C3)

PX2

(C2)

EX2

(C1)

IE2

(C0)

IT2

00000000B

Interrupt priority

B8H

PT2

PT1

PX1

PT0

PX0

xx000000B

Port 3

B0H

(B7)

(B6)

(B5)

(B4)

(B3)

INT1

(B2)

INT0

(B1)

TXD

(B0)

RXD

11111111B

Interrupt enable

A8H

(AF)

(AE)

(AD)

ET2

(AC)

(AB)

ET1

(AA)

EX1

(A9)

ET0

(A8)

EX0

00000000B

Port 2

A0H

(A7)

A15

(A6)

A14

(A5)

A13

(A4)

A12

(A3)

A11

(A2)

A10

(A1)

(A0)

11111111B

SBUF

Serial buffer

99H

xxxxxxxxB

SCON*

Serial control

98H

(9F)

SM0/FE

(9E)

SM1

(9D)

SM2

(9C)

REN

(9B)

TB8

(9A)

RB8

(99)

(98)

00000000B

P1*

Port 1

90H

(97)

(96)

(95)

(94)

(93)

(92)

(91)

T2EX

(90)

11111111B

AUXR*

Auxiliary

8EH

xxxxxxx0B

TH1

Timer high 1

8DH

00000000B

TH0

Timer high 0

8CH

00000000B

TL1

Timer low 1

8BH

00000000B

TL0

Timer low 0

8AH

00000000B

TMOD

Timer mode

89H

GATE

C/T

GATE

C/T

00000000B

TCON

Timer control

88H

(8F)

TF1

(8E)

TR1

(8D)

TF0

(8C)

TR0

(8B)

IE1

(8A)

IT1

(89)

IE0

(88)

IT0

00000000B

PCON*

Power control

87H

SMOD

SMOD0

POF+

GF1

GF0

IDL

00xxxx00B

DPH

Data pointer high

83H

00000000B

DPL

Data pointer low

82H

00000000B

Stack pointer

81H

00000111B

Port 0

80H

(87)

(86)

(85)

(84)

(83)

(82)

(81)

(80)

11111111B

W78C54

- 8 -

Note: In column

BIT_ADDRESS, SYMBOL

, containing ( ) item means the bit address.

* SFRs modified or added to the W78C52. + Reset value depends on reset condition.

W78C54 SFRs address location map:

+ B

+ ACC

+P4

+ PSW

+T2CON

RCAP2L

RCAP2H

TL2

TH2

+XICON

+ IP

+ P3

+ IE

+ P2

+ SCON

SBUF

+ P1

+ TCON

TMOD

TL0

TL1

TH0

TH1

AUXR

+P0

DPL

DPH

PCON

Notes:

1. + SFR is bit-addressable.

2. is additional defined function.

Power-off Flag

***PCON - Power Control (87H)

SMOD

SMOD0

POF

GF1

GF0

IDL

SMOD:

Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is
being used in either modes 1, 2, 3.

SMOD0:

Enable FE bit in SCON. This bit is an alternative switch of SM0 and FE (Frame Error)

bit.

When set to a 1, SCON.7 means a FE bit, otherwise a SM0 bit.

POF:

Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD:

Power down mode bit. Set it to enter power down mode.

IDL:

Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when V

has been applied to the part. It can

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

W78C54

Publication Release Date: December 1997

- 9 -

Revision A2

* Interrupts

***IE - Interrupt Enable (A8H)

ET2

ET1

EX1

ET0

EX0

EA: Lobal interrupt enable flag

ET2: Timer 2 overflow interrupt enable

ES: Serial port interrupt enable

EX1: External interrupt 1 enable

ET1: Timer 1 overflow interrupt enable

EX0: External interrupt 0 enable

***IP - Interrupt Priority (B8H)

PT2

PT1

PX1

PT0

PX0

PT2: Timer 2 interrupt priority high if set

PS: Serial port priority high if set

PT1: Timer 1 interrupt priority high if set

PX1: External interrupt 1 priority high if set

PT0: Timer 0 interrupt priority high if set

PX0: External interrupt 0 priority high if set

***XICON - External Interrupt Control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

The W78C54 supports an eight-source and a four-priority-level interrupt architectures. Besides the
SFRs of IP and IE to control the six-source of the standard 8052 interrupt functions. There is an
another SFR (XICON) to control the extra two-source of the external interrrupt (INT2 and INT3). This
priority scheme is formed by combining IPH with IP to determine the priority of each interrupt. Except
the INT2 and INT3, they are not defined in IP

SFR

but in XICON.

W78C54

- 10 -

Following tables show the interrupt informations and priority definitions.

Eight-source interrupt informations:

INTERRUPT

SOURCE

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

External Interrupt 0

03H

0 (highest)

IE.0

TCON.IT0

Timer/Counter 0

0BH

IE.1

External Interrupt 1

13H

IE.2

TCON.IT1

Timer/Counter 1

1BH

IE.3

Serial Port

23H

IE.4

Timer/Counter 2

2BH

IE.5

External Interrupt 2

33H

XICON.EX2

XICON.IT2

External Interrupt 3

3BH

7 (lowest)

XICON.EX3

XICON.IT3

*Timer/Counter

***TL0, TH0, TL1, TH1, TL2, TH2, RCAP2L, RCAP2H
***TMOD - Timer 0, 1 mode (89H)

GATE

C//T

GATE

C//T

TIMER0

TIMER1

GATE: Gating control. When set, Timer/counter x is enabled only while INTx pin is high and TRx

control pin is set. When cleared, Timer x is enabled whenever the TRx conrol bit is set.

C//T:

Timer or Counter Selector. Cleared for timer operation. Set for counter operation.

M1 M0: Operating Mode

0 0: 13-bit Timer/Counter.

0 1: 16-bit Timer/Counter.

1 0: 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx

each time it overflows.

1 1: Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

Timer 1: Timer/counter 1 stopped.

***TCON - Timer 0, 1 Control (88H)

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1: Timer 1 overflow flag. Set by hardware on timer/counter overflow. cleared by hardware when

processor vectors to interrupt routine.

W78C54

Publication Release Date: December 1997

- 11 -

Revision A2

TR1: Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off.

TF0: Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when

processor vectors to interrupt routine.

TR0: Timer 0 run control bit. Set/cleared by software to turn timer/counter on or off.

IE1: Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when

interrupt processed.

IT1: Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupt.

IE0: Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when

interrupt processed.

IT0: Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupt.

***T2CON - Timer 2 Control (C8H)

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C//T

CP//RL2

TF2:

Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will
not be set when RCLK = 1 or TCLK = 1.

EXF2:

Timer2 external flag. Set when either a capture or reload is caused by a negative transition
on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.

RCLK:

Receive clock flag. RCLK = 1 causes the serial port to use Timer 2 overflow pulses for its
receive clock in mode 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the

receive

clock.

TCLK:

Transmit clock flag. TCLK = 1 causes the serial port to use Timer 2 overflow pulses for its
transmit clock in mode 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the
transmit clock.

EXEN2: Timer 2 external enable flag. EXEN2 = 1 allows a capture or reload to occur as a result of a

negative transition on T2EX if Timer 2 is not used to clock the serial port. EXEN2 = 0

causes

Timer 2 to ignore events at T2EX.

TR2:

TR2 = 1/0: turns on/off Timer 2.

C//T:

Timer or Counter select. Set 1/0 for external event counter(falling edge triggered)/inter

timer.

CP//RL2: Capture/reload flag.

*Reduced EMI Mode

The AO bit in the AUXR register, when set, disables the ALE output.

***AUXR - Auxiliary Register (8EH)

AO: Turn off ALE output.

W78C54

- 12 -

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3

+7.0

Input Voltage

-0.3

+0.3

Operating Temperature

Storage Temperature

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC CHARACTERISTICS

= 5V

10%, T

= 25

C, Fosc = 20 MHz, unless otherwise specified.)

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Operating Voltage

4.5

5.5

Operating Current

No load

= 5.5V

Idle Current

IDLE

Idle mode

= 5.5V

Power Down Current

PWDN

Power-down mode

= 5.5V

Input Current

P1, P2, P3, P4

IN1

-50

+10

= 5.5V

= 0V or V

Input Current

RST

IN2

-10

+300

= 5.5V

0 < V

< V

Input Leakage Current

P0, EA

-10

+10

= 5.5V

0V < V

< V

Logic 1 to 0 Transition
Current

P1, P2, P3, P4

[*4]

-500

-200

= 5.5V

= 2.0V

Input Low Voltage

P0, P1, P2, P3, P4, EA

IL1

0.8

= 4.5V

Input Low Voltage

RST

IL2

0.8

= 4.5V

Input Low Voltage

XTAL1[*4]

IL3

0.8

= 4.5V

W78C54

Publication Release Date: December 1997

- 13 -

Revision A2

DC Characteristics, continued

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Input High Voltage

P0, P1, P2, P3, P4, EA

IH1

2.4

+0.2

= 5.5V

Input High Voltage

RST

IH2

3.5

+0.2

= 5.5V

Input High Voltage

XTAL1 [*4]

IH3

3.5

+0.2

= 5.5V

Output Low Voltage

P1, P2, P3, P4

OL1

0.45

= 4.5V

= +2 mA

Output Low Voltage

P0, ALE, PSEN [*3]

OL2

0.45

= 4.5V

= +4 mA

Sink Current

P1, P2, P3, P4

SK1

= 4.5V

Vs = 0.45V

Sink Current

P0, ALE, PSEN

SK2

= 4.5V

Vs = 0.45V

Output High Voltage

P1, P2, P3, P4

OH1

2.4

= 4.5V

= -100

Output High Voltage

P0, ALE, PSEN [*3]

OH2

2.4

= 4.5V

= -400

Source Current

P1, P2, P3, P4

SR1

-120

-180

= 4.5V

Vs = 2.4V

Source Current

P0, ALE, PSEN

SR2

-10

-14

= 4.5V

Vs = 2.4V

Notes:

*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 K

*3. P0, ALE and /PSEN are tested in the external access mode.

*4. XTAL1 is a CMOS input.

*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

approximates to 2V.

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T

), and actual parts will

usually experience less than a

20 nS variation. The numbers below represent the performance

expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers.

W78C54

- 14 -

Clock Input Waveform

XTAL1

OP,

Continued

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

MHz

Clock Period

Clock High

Clock Low

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

External Program Memory Fetch Cycle

(see Figure 6)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UINT

NOTES

Address Valid to ALE Low

AAS

Address Hold After ALE Low

AAH

ALE Low to PSEN Low

APL

PSEN Low to Data Valid

PDA

Data Hold After PSEN High

PDH

Data Float After PSEN High

PDZ

ALE Pulse Width

ALW

PSEN Pulse Width

PSW

Notes:

1. P00-P07, P20-P27 remain stable through entire memory cycle.

2. Memory access time is 3 Tcp.

3. Data has been latched internally prior to /PSEN going high.

is 20 ns (due to buffer driving delay and wire loading).

W78C54

Publication Release Date: December 1997

- 15 -

Revision A2

Data Read Cycle

External Data Memory Read Cycle

(see Figure 7)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UINT

NOTES

ALE Low to

Low

DAR

3 Tcp-

3 Tcp

3 Tcp+

1, 2

Low to Data Valid

DDA

4 Tcp

Data hold After

High

DDH

2 Tcp

Data Float After

High

DDZ

2 Tcp

Pulse Width

DRD

6 Tcp-

6 Tcp

6 Tcp+

Notes:

1. Data Memory access time is 5 Tcp.

is 20 ns (due to buffer driving delay and wire loading.

Data Write Cycle

External Data Memory Write Cycle

(see Figure 8)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UINT

NOTE

ALE Low to

Low

DAW

3 Tcp-

3 Tcp

3 Tcp+

Data Valid to

Low

DAD

1 Tcp-

Data hold After

High

DWD

1 Tcp-

Pulse Width

DWR

6 Tcp-

6 Tcp

6 Tcp+

*Note:

is 20 ns (due to buffer driving delay and wire loading)

Port Access Cycle

(see Figure 9)

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UINT

Port Input Setup to ALE Low

PDS

1Tcp

Port Input Hold After ALE Low

PDH

Port Output to ALE High

PDA

1Tcp-

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

W78C54

- 18 -

APPLICATION CIRCUIT

Expanded External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

27512

AD0

74LS373

AD0

RESET

INT0

INT1

P1.0

P1.1
P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

39
38
37
36

24
25
26
27
28

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN

ALE

TXD

RXD

W78C54

VCC

10u

8.2K

VCC

CRYSTAL

AD1
AD2
AD3
AD4
AD5
AD6

AD7

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3
A4
A5
A6

A1
A2
A3
A4
A5
A6
A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10
A11
A12
A13
A14
A15

GND

A9
A10
A11
A12
A13
A14
A15

41
40

Figure A

Table 1 Shows the typical values of off-chip components to configure the on-chip oscillator.

Table 1. Off-chip components list

CRYSTAL FREQ.

12 MHz

30 pF

16 MHz

30 pF

20 MHz

15 pF

24 MHz

15 pF

33 MHz

10 pF

6.8 K

40MHz

5 pF

4.3 K

Notes:

1. Refer to Figure 10 for C1, C2 and R.

2. It is recommended that an oscillator be used as external clock source when operating freq. is above 35MHz. Apply the

external clock signal to XTAL1, and leave XTAL2 float, as shown in Figure 10.

W78C54

Publication Release Date: December 1997

- 19 -

Revision A2

Application Circuit, continued

Expanded External Data Memory and Oscillator

10u

8.2K

VCC

OSCILLATOR

VCC

RESET

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

W78C54

38
37
36

42
41
40

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

AD7

AD0
AD1
AD2
AD3
AD4
AD5
AD6

3
4
7
8
13
14
17

A0
A1
A2
A3
A4
A5
A6
A7

2
5
6
9
12
15
16
19

74LS373

A0
A1
A2
A3
A4
A5
A6
A7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

11
12
13
15
16
17
18
19

D0
D1
D2
D3
D4
D5
D6
D7

A8
A9
A10
A11
A12
A13
A14

A10
A11
A12
A13
A14

GND

A1
A2
A3
A4
A5
A6
A7

9
8
7
6
5
4
3

A8
A9
A10
A11
A12
A13
A14

25
24
21
23

GND

22
27

20256

Figure B

W78C54

- 20 -

PACKAGE DIMENSIONS
40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

c
D

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

44-pin PLCC

Seating Plane

Symbol

Min. Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

W78C54

Publication Release Date: December 1997

- 21 -

Revision A2

Package Dimensions, continued

44-pin QFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

44-pin TQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.200

0.090

0.008

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

---

0.047

0.002

0.037

0.0039

0.039

0.013

0.041

0.015

0.95

0.22

0.05

1.00

0.32

1.05

0.38

0.390

0.018

0.039

0.003

0.394

0.024

0.398

0.030

9.9

0.80

0.45

1.00

10.00

0.60

10.1

0.75

0.398

0.394

0.390

0.476

0.472

0.468

12.10

12.00

11.90

10.1

10.00

9.9

0.08

0.031

0.004

0.006

0.10

0.15

---

1.20

b
c

0.025

0.036

0.635

0.952

0.476

0.472

0.468

12.10

12.00

11.90

---

W78C54

- 22 -

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792697
http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666

FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78C54P-40

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78C54P-40