W78E51C Data Sheet

8-BIT MICROCONTROLLER

Publication Release Date: April 20, 2005

- 1 -

Revision A2

Table of Contents-

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES ................................................................................................................................. 3

PIN CONFIGURATIONS............................................................................................................. 4

PIN DESCRIPTION..................................................................................................................... 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION.................................................................................................... 7

6.1

New Defined Peripheral.................................................................................................. 7

6.2

Reduce EMI Emission .................................................................................................... 8

6.3

Watchdog Timer ............................................................................................................. 9

6.4

Clock ............................................................................................................................. 10

6.5

Power Management...................................................................................................... 10

6.6

Reset............................................................................................................................. 11

SECURITY BITS ....................................................................................................................... 11

7.1

Lock Bit ......................................................................................................................... 11

7.2

MOVC Inhibit................................................................................................................. 12

7.3

Encryption ..................................................................................................................... 12

ELECREICAL CHARACTERISTICS......................................................................................... 12

8.1

Absolute Maximum Ratings .......................................................................................... 12

8.2

D.C. Characteristics...................................................................................................... 12

8.3

A.C. Characteristics ...................................................................................................... 14

8.3.1

Clock Input Waveform ....................................................................................................14

8.3.2

Program Fetch Cycle......................................................................................................14

8.3.3

Data Read Cycle ............................................................................................................15

8.3.4

Data Write Cycle.............................................................................................................15

8.3.5

Port Access Cycle ..........................................................................................................15

8.3.6

Program Operation .........................................................................................................16

TIMING WAVEFORMS ............................................................................................................. 17

9.1

Program Fetch Cycle .................................................................................................... 17

9.2

Data Read Cycle........................................................................................................... 17

9.3

Data Write Cycle ........................................................................................................... 18

9.4

Port Access Cycle......................................................................................................... 18

W78E51C

- 2 -

10.

TYPICAL APPLICATION CIRCUITS ........................................................................................ 19

10.1

Expanded External Program Memory and Crystal ....................................................... 19

10.2

Expanded External Data Memory and Oscillator.......................................................... 20

11.

PACKAGE DIMENSIONS ......................................................................................................... 21

11.1

40-pin DIP ..................................................................................................................... 21

11.2

44-pin PLCC ................................................................................................................. 21

11.3

44-pin PQFP ................................................................................................................. 22

12.

REVISION HISTORY ................................................................................................................ 23

W78E51C

Publication Release Date: April 20, 2005

- 3 -

Revision A2

1. GENERAL DESCRIPTION

The W78E51C is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E51C is fully compatible with the standard 8051.
The W78E51C contains an 4K bytes Flash EPROM; a 128 bytes RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog
timer and a serial port. These peripherals are supported by seven sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78E51C allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.

The W78E51C microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

2. FEATURES

�

Fully static design 8-bit CMOS microcontroller

�

Wide supply voltage of 4.5V to 5.5V

�

128 bytes of on-chip scratchpad RAM

�

4 KB On-chip Flash EPROM

�

64 KB program memory address space

�

64 KB data memory address space

�

Four 8-bit bi-directional ports

�

One extra 4-bit bit-addressable I/O port, additional INT2 / INT3

(available on 44-pin PLCC/QFP package)

�

Two 16-bit timer/counters

�

One full duplex serial port(UART)

�

Watchdog Timer

�

Seven sources, two-level interrupt capability

�

EMI reduction mode

�

Built-in power management

�

Code protection mechanism

�

Packages:

DIP 40: W78E51C-40

PLCC 44: W78E51CP-40

PQFP 44: W78E51CF-40

W78E51C

Publication Release Date: April 20, 2005

- 5 -

Revision A2

4. PIN DESCRIPTION

SYMBOL DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is within
on-chip ROM area.

PSEN

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.

ALE

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.

RST

RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.

XTAL1

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.

XTAL2

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

POWER SUPPLY: Supply voltage for operation.

P0.0

P0.7

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 are open-
drain and should connect to pull up resistors if necessary while in programming.

P1.0

P1.7

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control

P2.0

P2.7

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0

P3.7

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output

INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input

WR (P3.6) : External Data Memory Write Strobe

(P3.7) : External Data Memory Read Strobe

P4.0

P4.3

PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
(INT2 /INT3 ).

W78E51C

Publication Release Date: April 20, 2005

- 7 -

Revision A2

6. FUNCTIONAL DESCRIPTION

The W78E51C architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

6.1 New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Seven-source interrupt information

INTERRUPT SOURCE

VECTOR

ADDRESS

POLLING SEQUENCE

WITHIN PRIORITY

LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT TYPE

EDGE/LEVEL

External Interrupt 0

03H

0 (highest)

IE.0

TCON.0

Timer/Counter 0

0BH

IE.1

External Interrupt 1

13H

IE.2

TCON.2

Timer/Counter 1

1BH

IE.3

Serial Port

23H

IE.4

External Interrupt 2

33H 5 XICON.2

XICON.0

External Interrupt 3

3BH

6 (lowest) XICON.6

XICON.3

W78E51C

- 8 -

Port 4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 ,

INT3 ).

Example:
P4 REG 0D8H

MOV

P4,

#0AH

;

Output

data

"A"

through

P4.0

P4.3.

MOV A, P4 ; Read P4 status to Accumulator.
ORL P4,#00000001B ; Set bit P4.0
ANL P4,#11111101B ; Clear bit P4.1

6.2 Reduce EMI Emission

Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which
is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E51C allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may effect to external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1, C2 may need adjustment while running at lower gain.

***AUXR - Auxiliary register (8EH)

- - - - - - - AO

AO: Turn off ALE output.

Power-off Flag

***PCON - Power control (87H)

POF

GF1 GF0 PD IDL

POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to

determine

chip

reset

warm

boot

cold

boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when V

has been applied to the part. It can

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

W78E51C

Publication Release Date: April 20, 2005

- 9 -

Revision A2

6.3 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit: 7 6 5 4 3 2 1 0

ENW CLRW

WIDL

PS2 PS1 PS0

Mnemonic:

WDTC Address:

8FH

ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

128

1 1 1

256

The time-out period is obtained using the following equation:

OSC

PRESCALER 1000 12 mS

�

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

W78E51C

- 10 -

OSC

1/12

PRESCALER

14-BIT TIMER

CLEAR

CLRW

EXTERNAL

RESET

INTERNAL

RESET

WIDL

IDLE

ENW

Watchdog Timer Block Diagram

Typical Watch-dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

0 0 0

19.66 mS

0 0 1

39.32 mS

0 1 0

78.64 mS

0 1 1

157.28 mS

1 0 0

314.57 mS

1 0 1

629.14 mS

1 1 0

1.25 S

1 1 1

2.50 S

6.4 Clock

The W78E51C is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78E51C relatively insensitive to duty
cycle variations in the clock. The W78E51C incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.

6.5 Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a
reset.

W78E51C

Publication Release Date: April 20, 2005

- 11 -

Revision A2

6.6 Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E51C is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

7. SECURITY BITS

During the programmer operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The
protection of Flash EPROM and those operations on it are described below. The W78E51C has a
Special Setting Register, the Security Register, which can be accessed in normal mode. The register
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers
can not be changed once they have been programmed from high to low. They can only be reset
through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode
by address #0FFFFh.

B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,

logic 0 : the MOVC instruction in external memory

cannot access the code in internal memory.

logic 1 : no restriction.

Default 1 for all security bits.

Special Setting Register

D7 D6 D5 D4 D3 D2 D1 D0

Security Bits

4KB Flash EPROM

Program Memory

Reserved

Security Register

0FFFFh

0000h

0FFFh

Reserved

B2 : Encryption

logic 0 : the encryption logic enable

logic 1 : the encryption logic disable

Reserved bits must be kept in logic 1.

B7 : Osillator Control

logic 0 : 1/2 gain

logic 1 : Full gain

7.1 Lock Bit

This bit is used to protect the customer's program code in the W78E51C. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
on-chip ROM data and Special Setting Registers can not be accessed again.

W78E51C

- 12 -

7.2 MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.

7.3 Encryption

This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

8. ELECREICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings

PARAMETER SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3 +7.0 V

Input Voltage

-0.3

+0.3

Operating Temperature

0 70

�

Storage Temperature

-55

+150

�

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

8.2 D.C. Characteristics

= 5V

�

10%, T

= 25

�

C, unless otherwise specified.

SPECIFICATION

PARAMETER SYMBOL

TEST

CONDITIONS

MIN. MAX.

UNIT

Operating Voltage

4.5 5.5 V

Operating Current

No load V

= 5.5V

Idle Current

IDLE

Idle mode V

= 5.5V

Power Down Current

PWDN

Power-down mode
V

= 5.5V

- 50

�

Input Current
P1, P2, P3, P4

IN1

= 5.5V

= 0V or V

-50 +10

�

Logical 1-to-0 Transition

Current P1, P2, P3

(*1)

, P4

= 5.5V

= 2.0V

(*1)

-550 -

�

Input Current

RST

(*2)

IN2

= 5.5V

= V

-10 +300

�

W78E51C

Publication Release Date: April 20, 2005

- 13 -

Revision A2

DC Characteristics, continued

SPECIFICATION

PARAMETER SYMBOL

TEST

CONDITIONS

MIN. MAX.

UNIT

Input Leakage Current
P0, EA

= 5.5V

0V < V

< V

-10 +10

�

Output Low Voltage
P1, P2, P3, P4

OL1

= 4.5V

OL1

= +2 mA

- 0.45

Output Low Voltage

ALE, PSEN , P0

(*3)

OL2

= 4.5V

OL2

= +4 mA

- 0.45

Output High Voltage
P1, P2, P3, P4

OH1

= 4.5V

OH1

= -100

�

2.4 - V

Output High Voltage
ALE, PSEN , P0

(*3)

OH2

= 4.5V

OH2

= -400

�

2.4 - V

Input Low Voltage
(Except RST)

IL1

= 4.5V

0.8

Input Low Voltage

RST

(*4)

IL2

= 4.5V

0.8

Input Low Voltage
XTAL1

(*4)

IL3

= 4.5V

0.8

Input High Voltage
(Except RST)

IH1

= 4.5V

2.4

+0.2

Sink Current
P1, P2, P3, P4

SK1

= 4.5V

Vs = 0.45V

4 12

Input High Voltage

RST

(*4)

IH2

= 4.5V

0.67 V

+0.2

Input High Voltage
XTAL1

(*4)

IH3

= 4.5V

0.67 V

+0.2

Sink Current
P0, ALE, PSEN

(*3)

SK2

= 4.5V

Vs = 0.45V

8 16

Source Current
P1, P2, P3, P4

SR1

= 4.5V

= 2.4V

-100

-250

Source Current
P0, ALE, PSEN

(*3)

SR2

= 4.5V

= 2.4V

-8 -14

Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current

reaches its maximum value when V

is approximately 2V.

*2. RST pin has an internal pull-down resistor.

*3. P0, ALE, PSEN are in the external access memory mode.

*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.

W78E51C

- 14 -

8.3 A.C. Characteristics

The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T

), and actual parts will usually

experience less than a

�

20 nS variation. The numbers below represent the performance expected

from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

8.3.1 Clock Input Waveform

XTAL1

OP,

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

0 - 40

MHz 1

Clock Period

Clock High

10 - - nS 3

Clock Low

10 - - nS 3

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

8.3.2 Program Fetch Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

- - nS 4

Address Hold from ALE Low

AAH

1 T

- - nS 1,

ALE Low to

PSEN

Low

APL

1 T

- - nS 4

PSEN

Low to Data Valid

PDA

- -

nS 2

Data Hold after PSEN High

PDH

nS 3

Data Float after PSEN High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN Pulse Width

PSW

3 T

Notes:
1.

P0.0

P0.7, P2.0

P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.

" (due to buffer driving delay and wire loading) is 20 nS.

W78E51C

Publication Release Date: April 20, 2005

- 15 -

Revision A2

8.3.3 Data

Read

Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

ALE Low to RD Low

DAR

3 T

nS 1,

RD Low to Data Valid

DDA

- -

nS 1

Data Hold from RD High

DDH

2 T

Data Float from RD High

DDZ

0 -

RD Pulse Width

DRD

6 T

Notes:

1. Data memory access time is 8 T

" (due to buffer driving delay and wire loading) is 20 nS.

8.3.4 Data

Write

Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to WR Low

DAW

3 T

Data Valid to WR Low

DAD

1 T

- - nS

Data Hold from WR High

DWD

1 T

- - nS

WR Pulse Width

DWR

6 T

Note: "

" (due to buffer driving delay and wire loading) is 20 nS.

8.3.5 Port Access Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

1 T

- - nS

Port Input Hold from ALE Low

PDH

0 - -

Port Output to ALE

PDA

1 T

- - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

W78E51C

Publication Release Date: April 20, 2005

- 19 -

Revision A2

10. TYPICAL APPLICATION CIRCUITS

10.1 Expanded External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

27512

AD0

74373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

W78E51B

10 u

8.2 K

CRYSTAL

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD1

AD2

AD3

AD4

AD5

AD6

AD7

GND

A6
A7

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A10

A11

A12

A13

A14

A15

GND

A10

A11

A12

A13

A14

A15

Figure A

CRYSTAL C1

C2 R

16 MHz

30P

24 MHz

15P

33 MHz

10P

6.8K

40 MHz

4.7K

Above table shows the reference values for crystal applications (full gain).

Note: C1, C2, R components refer to Figure A.

W78E51C

- 20 -

Typical Application Circuits, continued

10.2 Expanded External Data Memory and Oscillator

10 u

8.2 K

OSCILLATOR

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

W78E51B

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0
AD1

AD2

AD3
AD4

AD5

AD6

AD7

74373

A0
A1

A4
A5

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A10

A11

A12

A13

A14

A9
A10

A11

A12

A13
A14
CE

GND

A10

A11

A12

A13

A14

GND

OE
WR

20256

Figure B

W78E51C

Publication Release Date: April 20, 2005

- 21 -

Revision A2

11. PACKAGE DIMENSIONS

11.1 40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

11.2 44-pin PLCC

Seating Plane

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

W78E51C

- 22 -

Package Dimensions, continued

11.3 44-pin PQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

W78E51C

Publication Release Date: April 20, 2005

- 23 -

Revision A2

12. REVISION HISTORY

VERSION DATE PAGE

DESCRIPTION

Nov. 26, 2004

Formerly issued

April 20, 2005

Add Important Notice

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

Электронный компонент: W78E51C