W78E58

8-BIT MICROCONTROLLER

Publication Release Date: November 1997

- 1 -

Revision A2

GENERAL DESCRIPTION

The W78E58 is an 8-bit microcontroller that is functionally compatible with the W78C58, except that
the mask ROM is replaced by a flash EEPROM with a size of 32 KB. To facilitate programming and
verification, the flash EEPROM inside the W78E58 allows the program memory to be programmed
and read electronically. Once the code is confirmed, the user can protect the code for security.

The W78E58 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the
market. It is functionally compatible with the industry-standard 80C52 microcontroller series, except

that one extra 4-bit bit-addressable I/O port(Port 4) and two additional external interrupts (

INT2

INT3 ).

The W78E58 contains four 8-bit bi-directional and bit-addressable I/O ports, three 16-bit
timer/counters, and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 32 KB flash EEPROM for application
programs.

The W78E58 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

8-bit CMOS microcontroller

Fully static design

Low standby current at full supply voltage

DC-40 MHz operation

256 bytes of on-chip scratchpad RAM

32 KB electrically erasable/programmable EPROM

64 KB program memory address space

64 KB data memory address space

Four 8-bit bidirectional ports

One extra 4-bit bit-addressable I/O port, additional

INT2

/ INT3

(available on 44-pin PLCC/QFP package)

Three 16-bit timer/counters

One full duplex serial port

Boolean processor

Eight-source, two-level interrupt capability

Built-in power management

Code protection mechanism

Packages:

DIP 40: W78E58-16/24/40

PLCC 44: W78E58P-16/24/40

QFP 44: W78E58F-16/24/40

TQFP 44: W78E58M-16/24/40

W78E58

- 2 -

PIN CONFIGURATIONS

VCC

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA
ALE

PSEN

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

T2, P1.0

40-Pin DIP (W78E58)

P1.2

P1.3

P1.4

P1.5

P1.6

RXD, P3.0
TXD, P3.1

P1.7

RST

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

WR, P3.6

RD, P3.7

XTAL1

XTAL2

VSS

T2EX, P1.1

44-Pin PLCC (W78E58P)

44-Pin QFP/TQFP (W78E58F/W78E58M)

40 39 38 37 36 35

44 43 42 41

33
32

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

1 44 43 42 41

39
38

30
29

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
C
C

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

T
2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P
4
.
0

/
I
N
T
3
,
P
4
.
2

P4.1

P
4
.
0

INT2, P4.3

/
I
N
T
3
,
P
4
.
2

W78E58

Publication Release Date: November 1997

- 3 -

Revision A2

PIN DESCRIPTION

The W78E58 has two operating modes, normal and flash. In normal mode, the W78E58 corresponds
to the W78C58. In flash mode, the user (the maker of the flash EEPROM writer) can access the flash
EEPROM.

P0.7

P0.0 Port 0, Bits 7

MODE

DESCRIPTION

Normal

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.

Flash

This port provides the data bus during access to the flash EEPROM.

P1.7

P1.0 Port 1, Bits 7

MODE

DESCRIPTION

Normal

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins
P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2
capture/reload trigger), respectively.

Flash

This port provides the low-order address bus during access to the flash EEPROM.

P2.7

P2.0 Port 2, Bits 7

MODE

DESCRIPTION

Normal

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port
also provides the upper address bits for accesses to external memory..

Flash

This port provides the high-order address bus during access to the flash EEPROM.

P3.7

P3.0 Port 3, Bits 7

MODE

DESCRIPTION

Normal

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits
have alternate functions.

Flash

P3.3

P3.0 and P3.7

P3.6 are the flash mode configuration pins, Input.

P3.3

P3.0 and P3.7

P3.6 are configured to select or execute the flash operations. For

details, see

Flash Operations

P4.3

P4.0 Port 4, Bits 3

0 (available on 44-pin PLCC/QFP package)

MODE

DESCRIPTION

Normal

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O pins or external interrupt input sources

(

INT2

/ INT3 ).

W78E58

- 4 -

Flash

No function in this mode.

EA/V

MODE

DESCRIPTION

Normal

External Access, Input, active low.

This pin forces the processor to execute a program from the external ROM. When the
internal flash EEPROM is accessed as in the W78C58, this pin should be kept high.

Flash

, Program Power supply pin, Input.

This pin accepts the high voltage (12V) needed for programming the flash EEPROM.

RST

MODE

DESCRIPTION

Normal

RST, Reset, Input, active high.

This pin resets the processor. It must be kept high for at least two machine cycles in
order to be recognized by the processor.

Flash

Flash mode configuration pin, Input, active high.

RST is used to configure the flash operations. For details, see

Flash Operations

ALE

MODE

DESCRIPTION

Normal

ALE, Address Latch Enable, Output, active high.

ALE is used to enable the address latch that separates the address from the data on
Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped
during external data memory accesses. ALE goes to a high impedance state with a
weak pull-up during reset state.

Flash

Flash mode configuration pin, Input, active low.

ALE is used to configure the flash operations. For details, see

Flash Operations

PSEN

MODE

DESCRIPTION

Normal

PSEN,

Program Store Enable, Output, active low.

This pin enables the external ROM onto the Port 0 address/data bus during fetch and
MOVC operations. PSEN goes to a high impedance state with a weak pull-up during
reset state

Flash

Flash mode configuration pin, Input, active high.

PSEN is used to configure the flash operations. For details, see

Flash Operations.

XTAL1

MODE

DESCRIPTION

W78E58

- 6 -

BLOCK DIAGRAM

P3.0
~
P3.7

P1.0

P1.7

ALU

Port 0

Latch

Port 1

Latch

Timer

Port

UART

XTAL1

PSEN

ALE

Vss

Vcc

RST

XTAL2

Oscillator

Interrupt

PSW

Instruction

Decoder

Sequencer

Reset Block

Bus & Clock

Controller

SFR RAM

Address

Power Control

256 bytes

RAM & SFR

Stack

Pointer

Addr. Reg.

Incrementor

DPTR

Temp Reg.

ACC

Port 3

Latch

Port 4

Latch

Port

Port 2

Latch

P4.0
~
P4.3

Port

Port
0

Port
2

P2.0
~
P2.7

P0.0
~
P0.7

INT2

INT3

W78E58

Publication Release Date: November 1997

- 7 -

Revision A2

FUNCTIONAL DESCRIPTION

The W78E58 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.

The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78E58: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.

Clock

The W78E58 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E58 relatively insensitive to duty cycle
variations in the clock.

Crystal Oscillator

The W78E58 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.

W78E58

- 8 -

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E58 is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Option Setting

Users write programs into the W78E58 by using the Winbond proprietary writer. The writer programs
the data into an internal 32 KB region and reads the data back for verification. After confirming that
the program is correct, the user can lock the data so that they can no longer be read.

Lock Bit

This bit is used to protect the customer data in the W78E58. It may be turned on after the
programmer finishes the programming and verify sequence. Once this bit is set to logic 0, no flash
data can be accessed again.

MOVC Execute

This bit is used to restrict the region accessible to the MOVC instruction. It can prevent the program
from being downloaded using this instruction if the program needs to jump outside to get data. When
this bit is set to logic 0, a MOVC instruction in external program memory space will be able to
access code in the external memory, but it will not be able to access code in the internal memory. A
MOVC instruction in internal program memory space will always be able to access code in both
internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt

INT2

, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:

INT2/INT3

Two additional external interrupts,

INT2

and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

W78E58

Publication Release Date: November 1997

- 9 -

Revision A2

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

INTERRUPT

SOURCE

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL

External Interrupt 0

03H

0 (highest)

IE.0

TCON.0

Timer/Counter 0

0BH

IE.1

External Interrupt 1

13H

IE.2

TCON.2

Timer/Counter 1

1BH

IE.3

Serial Port

23H

IE.4

Timer/Counter 2

2BH

IE.5

External Interrupt 2

33H

XICON.2

XICON.0

External Interrupt 3

3BH

7 (lowest)

XICON.6

XICON.3

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

alternative function pins. It can be used as general I/O pins or external interrupt input sources (

INT2

INT3 ).

Example:

REG

0D8H

MOV

P4, #0AH

; Output data "A" through P4.0

P4.3.

MOV

A, P4

; Read P4 status to Accumulator.

SETB

P4.0

; Set bit P4.0

CLR

P4.1

; Clear bit P4.1

3. Reduce EMI Emission

Because of the large on-chip flash EEPROM, when a program is running in internal ROM space, the
ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI

W78E58

- 10 -

emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the
AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program
accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will
turn off again after it has been completely accessed or the program returns to internal ROM code
space..

The AO bit in the AUXR register, when set, disables the ALE output.

***AUXR - Auxiliary register (8EH)

AO: Turn off ALE output.

4. Power-off Flag

***PCON - Power control (87H)

SMOD

POF

GF1

GF0

IDL

SMOD:

Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is

being used in either modes 1, 2, 3.

POF:

Power off flag. Bit is set by hardware when power on reset. It can be cleared by software

to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:

Power down mode bit. Set it to enter power down mode.

IDL:

Idle mode bit. Set it to enter idle mode.

The power-off flag is located at PCON.4. This bit is set when V

has been applied to the part. It can

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

Flash Operations

In normal operation, the W78E58 is functionally compatible with the W78C58. In the flash operating
mode, the flash EEPROM can be programmed and verified repeatedly. Once the code inside the
flash EEPROM is confirmed, the code can be protected. The flash EEPROM and the operations on it
are described below.

All of the operations are configured by the pins RST, ALE, PSEN, A9CTRL (P3.0), A13CTRL (P3.1),

A14CTRL (P3.2), OECTRL (P3.3),

(P3.6),

(P3.7), A0 (P1.0) and V

(

). In these

operations, A15 to A0 (P2.7 to P2.0, P1.7 to P1.0) and D7 to D0 (P0.7 to P0.0) serve as the address
and data bus, respectively.

Read Operation

This operation enables customers to read their codes and the option bits. The data will not be valid if
the lock bit is programmed to low.

W78E58

Publication Release Date: November 1997

- 11 -

Revision A2

Program Operation

This operation is used to program data to the flash EEPROM and the option bits. Programming is

initiated when V

reaches V

(12.5V) level,

is set to low, and

is set to high.

Program Verify Operation

All data must be checked after programming. This operation should be performed after each byte is
programmed, and it will ensure a substantial program margin.

OPERATION

P3.0

(A9

CTRL)

P3.1

(A13

CTRL)

P3.2

(A14

CTRL)

P3.3

(OE

CTRL)

P3.6

( CE )

P3.7

( OE )

)

P2, P1

(A15 TO A0)

(D7 TO D0)

NOTES

Read

Address

Data Out

1, 2

Program

Address

Data In

1, 2

Program Verify

Address

Data Out

Notes:

1. During all of these operations, RST = V

, ALE = V

IL,

and PSEN = V

2. V

= 12V, V

= V

, V

= Vss.

3. The program verify operation should follow the programming operaion.

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3

+7.0

Input Voltage

-0.3

+0.3

Operating Temperature

Storage Temperature

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

the device.

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

EA/Vpp

ALE

RST

PSEN

Vss

A0 to A7

A8 to A15

PGM DATA

+5V

Programming Configuration

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

EA/Vpp

ALE

RST

PSEN

Vss

A0 to A7

A8 to A15

PGM DATA

+5V

Programming Verification

W78E58

- 12 -

DC CHARACTERISTICS

-V

= 5V

10%, T

= 25

C, Fosc = 20 MHz, unless otherwise specified.)

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Operating Voltage

4.5

5.5

Operating Current

No load

= 5.5V

Idle Current

IDLE

Idle mode

= 5.5V

Power Down Current

PWDN

Power-down mode

= 5.5V

Input Current

P1, P2, P3, P4

IN1

-50

+10

= 5.5V

= 0V or V

Input Current

RST

IN2

-10

+300

= 5.5V

0 < V

< V

Input Leakage Current

P0,

-10

+10

= 5.5V

0V <V

< V

Logic 1 to 0 Transition
Current

P1, P2, P3, P4

[*4]

-500

-200

= 5.5V

=2.0V

Input Low Voltage

P0, P1, P2, P3, P4,

IL1

0.8

= 4.5V

Input Low Voltage

RST

IL2

0.8

= 4.5V

Input Low Voltage

XTAL1[*4]

IL3

0.8

= 4.5V

Input High Voltage

P0, P1, P2, P3, P4,

IH1

2.4

+0.2

= 5.5V

Input High Voltage

RST

IH2

3.5

+0.2

= 5.5V

Input High Voltage

XTAL1 [*4]

IH3

3.5

+0.2

= 5.5V

Output Low Voltage

P1, P2, P3, P4

OL1

0.45

= 4.5V

= +2 mA

W78E58

Publication Release Date: November 1997

- 13 -

Revision A2

DC Characteristics, continued

PARAMETER

SYM.

SPECIFICATION

UNIT

TEST CONDITIONS

MIN.

MAX.

Output Low Voltage

P0, ALE, PSEN [*3]

OL2

0.45

= 4.5V

= +4mA

Sink Current

P1, P2, P3, P4

SK1

= 4.5V

Vs = 0.45V

Sink Current

P0, ALE, PSEN

SK2

= 4.5V

Vs = 0.45V

Output High Voltage

P1, P2, P3, P4

OH1

2.4

= 4.5V

= -100

Output High Voltage

P0, ALE, PSEN [*3]

OH2

2.4

= 4.5V

= -400

Source Current

P1, P2, P3, P4

SR1

-120

-250

= 4.5V

Vs = 2.4V

Source Current

P0, ALE, PSEN

SR2

-8

-14

= 4.5V

Vs = 2.4V

Notes:

*1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 K

*3. P0, ALE and /PSEN are tested in the external access mode.

*4. XTAL1 is a CMOS input.

*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

approximates to 2V.

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T

), and actual parts will

usually experience less than a

20 nS variation. The numbers below represent the performance

expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

W78E58

- 14 -

XTAL1

OP,

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

MHz

Clock Period

Clock High

Clock Low

Notes:

1. The clock may be stopped indefinitely in either state.

2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

Address Hold from ALE Low

AAH

1 T

1, 4

ALE Low to PSEN Low

APL

1 T

PSEN Low to Data Valid

PDA

2 T

Data Hold after PSEN High

PDH

1 T

Data Float after PSEN High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN Pulse Width

PSW

3 T

Notes:

1. P0.0

P0.7, P2.0

P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.
4. "

" (due to buffer driving delay and wire loading) is 20 nS.

Data Read Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTE

ALE Low to RD Low

DAR

3 T

1, 2

RD Low to Data Valid

DDA

4 T

W78E58

Publication Release Date: November 1997

- 15 -

Revision A2

Data Hold from RD High

DDH

2 T

Data Float from RD High

DDZ

2 T

RD Pulse Width

DRD

6 T

Notes:

1. Data memory access time is 8 T

2. "

" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to WR Low

DAW

3 T

Data Valid to WR Low

DAD

1 T

Data Hold from WR High

DWD

1 T

WR Pulse Width

DWR

6 T

Note: "

" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

1 T

Port Input Hold from ALE Low

PDH

Port Output to ALE

PDA

1 T

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Program Operation

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Setup Time

VPS

2.0

Data Setup Time

2.0

Data Hold Time

2.0

Address Setup Time

2.0

Address Hold Time

Program Pulse Width for

Program Operation

PWP

295

300

305

Program Pulse Width for

Program Operation

OPWP

295

300

305

OECTRL Setup Time

OCS

2.0

OECTRL Hold Time

OCH

2.0

W78E58

- 20 -

TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

O1 12
O2 13
O3 15
O4 16
O5 17
O6 18
O7 19

27512

AD0

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74LS373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

39
38
37
36
35

34
33
32

21
22
23
24
25
26
27
28

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN 29

ALE 30

TXD 11
RXD

W78E58

10 u

8.2 K

CRYSTAL

AD1
AD2
AD3
AD4
AD5
AD6

AD7

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3
A4
A5
A6

A1
A2
A3
A4
A5
A6
A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10

A11
A12

A13

A14
A15

GND

A9
A10
A11
A12
A13
A14
A15

Figure A

CRYSTAL

16 MHz

30P

24 MHz

15P

33 MHz

10P

6.8K

40 MHz

4.7K

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

W78E58

Publication Release Date: November 1997

- 21 -

Revision A2

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

10 u

8.2 K

OSCILLATOR

XTAL1

XTAL2

RST

INT0

INT1

1
2
3
4
5
6

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6

P1.7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

W78E58

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

AD0
AD1
AD2
AD3
AD4
AD5
AD6

AD7

A0
A1
A2
A3
A4
A5
A6
A7

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74LS373

A0
A1
A2
A3
A4
A5
A6
A7

9
8
7
6
5
4
3

A0
A1
A2
A3
A4
A5
A6
A7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

11
12
13
15
16
17
18
19

D0
D1
D2
D3
D4
D5
D6
D7

A8
A9
A10
A11
A12
A13
A14

25
24
21
23

A8
A9
A10
A11

A12
A13
A14

GND

A10
A11
A12
A13
A14

GND

22
27

20256

Figure B

PACKAGE DIMENSIONS

40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

c
D

A
A

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

W78E58

- 22 -

Package Dimensions, continued

44-pin PLCC

Seating Plane

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

b
c
D

L
y

A
A

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

44-pin QFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

W78E58

Publication Release Date: November 1997

- 23 -

Revision A2

Timing Waveforms, continued

44-pin TQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.200

0.090

0.008

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

---

0.047

0.002

0.037

0.0039

0.039

0.013

0.041

0.015

0.95

0.22

0.05

1.00

0.32

1.05

0.38

0.390

0.018

0.039

0.003

0.394

0.024

0.398

0.030

9.9

0.80

0.45

1.00

10.00

0.60

10.1

0.75

0.398

0.394

0.390

0.476

0.472

0.468

12.10

12.00

11.90

10.1

10.00

9.9

0.08

0.031

0.004

0.006

0.10

0.15

---

1.20

b
c

0.025

0.036

0.635

0.952

0.476

0.472

0.468

12.10

12.00

11.90

---

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792697
http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666

FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

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