W78E858

8-BIT MICROCONTROLLER

Publication Release Date: November 27, 2002

- 1 -

Revision A3

1. GENERAL DESCRIPTION

The W78E858 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E858 is fully compatible with the standard 8052. The
W78E858 contains a 32K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 32KB main Flash EPROM to be updated by the loader program
located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM; 128 bytes of EEPROM, 8
extra power down wake-up through INT2 to INT9; 4 channel 8-bit PWM; four 8-bit bi-directional and
bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters where the TIMER2
with programmable clock output and 17-bit watchdog timer are built in this device; a serial port. These
peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming
and verification, the Flash EPROM inside the W78E858 allows the program memory to be
programmed and read electronically. Once the code is confirmed, the user can protect the code for
security.

2. FEATURES

Fully static design 8-bit CMOS micro-controller up to 40 MHz

32K bytes of in-system programmable FLASH EPROM for Application Program (APROM)

4K bytes of auxiliary FLASH EPROM for Loader Program (LDROM)

Low standby current at full supply voltage

256 + 512 bytes of on-chip RAM

128 bytes on-chip EEPROM memory

64K bytes program memory address space and 64K bytes data memory address space

Four 8-bit bi-directional ports

One 4-bit bi-directional port

Extra interrupts INT2 to INT9 at PORT1

Wake-up via external interrupts INT0

- INT9

Three 16-bit timer/counters

One full duplex serial port

Fourteen-sources, two-level interrupt capability

Programmable Timer2 clock output via P1.0

17-bits watchdog timer

Four channels 8-bit PWM

Built-in power management

Code protection

Packaged in PDIP 40 / PLCC 44 / PQFP 44

W78E858

- 2 -

3. PIN CONFIGURATIONS

44-pin

PLCC

1 44 43 42 41

39
38
37
36
35

34
33
32
31
30
29

P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7

ALE

PSEN
P2.7, A15
P2.6, A14
P2.5, A13

P1.5
P1.6
P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

2
.
3
,
A

1
1

2
.
2
,
A

1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

T
A
L
2

3
.
7
,
/

R
D

3
.
6
,
/

W
R

P4.1

P4.3

P
4
.

P
1
.
4

P
1
.
3

P
1
.
2

T
2
E
X
.

P
1
.
1

T
2
.

P
1
.
0

P
4
.
2

V
D
D

A
D
0

.
P
0
.
0

A
D
1

.
P
0
.
1

A
D
2

.
P
0
.
2

A
D
3

.
P
0
.
3

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

W R, P3.6

RD, P3.7

XTAL2

XTAL1

VSS

VCC

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

ALE

PSEN
P2.7, A15

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

P2.0, A8

40-pin

DIP

1
2

37
36

40 39 38 37 36

33
32

29
28

P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7

EA
P4.1

ALE

PSEN
P2.7, A15
P2.6, A14
P2.5, A13

P1.5

P1.6
P1.7

RST

RXD, P3.0

P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

1
.
4

P
1
.
3

1
.
2

2
E
X
.
P

1
.
1

T
2
.
P
1
.
0

V
D
D

A
D
0
.

P
0
.
0

A
D
1
.

P
0
.
1

A
D
2
.

P
0
.
2

A
D
3
.

P
0
.
3

P
4
.
2

44 43 42 41

T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

2
.
3
,
A

1
1

2
.
2
,
A

1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

T
A
L
2

3
.
7
,
/

R
D

3
.
6
,
/

W
R

P
4
.
0

44-pin PQFP

W78E858

Publication Release Date: November 27, 2002

- 3 -

Revision A3

4. PIN DESCRIPTION

SYMBOL TYPE

DESCRIPTIONS

External Access Enable:

low forces the processor to execute the

external ROM. The ROM address and data will not be present on the bus if
the

pin is high and the program counter is within the 32 KB area.

Otherwise they will be present on the bus.

PSEN

O/H

Program Strobe Enable:

PSEN

enables the external ROM data in the Port 0

address/data bus. When internal ROM access is performed, no

PSEN

strobe

signal outputs originate from this pin.

ALE

O/H

Address Latch Enable: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.

RST

I/L

RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device. RST has a Schmitt trigger input stage to provide
additional noise immunity with a slow rising input voltage.

XTAL1

Crystal 1: This is the crystal oscillator input. This pin may be driven by an
external clock

XTAL2

Crystal 2: This is the crystal oscillator output. It is the inversion of XTAL1.

Ground: Ground potential.

Power Supply: Supply voltage for operation.

P0.0

- P0.7 I/O D Port 0: Function is the same as that of the standard 8052.

P1.0

- P1.7 I/O H

Port 1: Function is the same as that of the standard 8052. Port1 also service
the alternative function INT2

- INT9. P1.0 provide a timer2 programmable

clock output. Four channel PWM clock output via P1.4

- P1.7

P2.0

- P2.7 I/O H Port 2: Port 2 is a bi-directional I/O port with internal pull-ups and emits the

high-order address byte during accesses external memory

P3.0

- P3.7 I/O H Port 3: Function is the same as that of the standard 8052

P4.0

- P4.3 I/O H Port 4: Function is the same as Port1

* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain

W78E858

- 4 -

5. BLOCK DIAGRAM

RAM

256

RAM 256

Auxiliary

RAM 512

Bytes

Auxiliary

MTP-ROM

4K Bytes

Main

MTP-ROM

32K Bytes

CPU

Core

SFR

PORT0

PORT1

PORT2

PORT4

TIMER2

PW M

TIMER1

INT0

INT1

INT2~9

W atch-dog

UART

TIMER0

PORT3

Power Down

W ake Up

EEPROM

128 Bytes

PROGRAMMABLE
CLOCK OUTPUT

Interrupts

8051

Data Bus

6. FUNCTIONAL DESCRIPTION

The W78E858 architecture consists of a core controller surrounded by various registers, four 8-bit
general purpose I/O ports, one 4-bits general purpose I/O port, 256 bytes data RAM and 512 bytes
auxiliary RAM, 128 bytes embedded EEPROM memory, three timer/counters, one serial port, 17-bit
watch-dog timer, 8-bit four channels PWM, programmable timer2 clock output, extra external
interrupts INT2 to INT9, power-down wake up via external interrupts INT0

- INT9. And a black box of

Eastern pay TV control block. The CPU supports 111 different op-codes and references both a 64K
program address space and a 64 K data storage space.

RAM

The internal data RAM in W78E858

is 768 bytes. It is divided into two banks: 256 bytes of data RAM

and 512 bytes of auxiliary RAM. These RAM are addressed by different ways.
· RAM 00H - 7FH can be addressed directly and indirectly as the same as in 80C51. Address

pointers are R0 and R1 of the selected register bank.

· RAM 80H - FFH can only be addressed indirectly as the same as in 80C51. Address pointers are

R0, R1 of the selected registers bank.

Auxiliary RAM 0000H

- 01FFH is addressed indirectly as the same way to access external data

memory with the MOVX instruction. Address pointers are R0 and R1 of the selected register bank
and DPTR register. By setting ENAUXRAM flag in CHPCON register bit4 to enable on-chip
auxiliary RAM 512 bytes. When the auxiliary RAM is enabled, the data and address will not appear
on P0 and P2, they will keep their previous status that before the MOVX instruction be executed.
Write the page select 00H or 01H to MXPSR register if R0 and R1 are used as address pointer.
When the address of external data memory locations higher than 01FFH or disable auxiliary RAM
512 bytes micro-controller will be performed with the MOVX instruction in the same way as in the
80C51. The auxiliary RAM 512 bytes default is disabled after chip reset.

W78E858

Publication Release Date: November 27, 2002

- 5 -

Revision A3

EEPROM

The 128 bytes EEPROM is defined in external data memory space that located in FF80H-FFFFH in
standard 8-bit series. It is accessed the same as auxiliary RAM512 bytes, the ENEEPROM flag in
CHPCON register bit5 is set. Write the page select 03H to MXPSR register, R0 and R1are used as
address pointer. The EEPROM provided byte write, page write mode and software write protection is
used to protect the data lose when power on or noise. They are described as below:

Byte Write Mode
Once a byte write has been started, it will automatically time itself to completion. A BUSY signal
(MXPSR.7) will be used to detect the end of write operation.

Page Write Mode
The EEPROM is divided into 2 pages and each page contains 64 bytes. The page write allows one to
64 bytes of data to be written into the memory during a single internal programming cycle. Page write
is initiated in the same manner as byte write mode. After the first byte is written, it can then be
followed by one to 63 additional bytes. If a second byte is written within a byte-load cycle time (TBLC)
of 150us, the EEPROM will stay at page load cycle. Additional bytes can then be loaded
consecutively. The page load cycle will be terminated and the internal programming cycle will start if
no additional byte is load within 300us from the last byte be loaded. The address bit6 specify the page
address. All bytes that are loaded to the buffer must have the same page address. The data for page
write may be loaded in any order, the sequential loading is not required.

Software Protected Data Write

The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme
is enabled, any write operation requires a series of three-byte program commands (with specific data
to a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up or power-down. Once enabled, the software data protection will remain
enabled unless the disable commands are issued. To reset the device to unprotected mode, a six-
byte command sequence is required.
The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM
flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The
data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.

Command Codes for Software Data Protection Enable/Disable and Software Erase

BYTE

ENABLE WRITE PROTECT

DISABLE WRITE PROTECT

SOFTWARE ERASE

SEQUENCE ADDRESS

DATA ADDRESS

DATA

Write FFD5H AAH FFD5H AAH FFD5H AAH

Write FFAAH 55H FFAAH 55H FFAAH 55H

2 Write

FFD5H

A0H

FFD5H

80H

FFD5H

80H

3 Write

FFD5H

AAH

FFD5H

AAH

4 Write

FFAAH

55H

FFAAH

55H

5 Write

FFD5H

20H

FFD5H

10H

W78E858

- 6 -

Auiliary RAM 512 Bytes

0000H

01FFH
0200H

EEPROM 128 Bytes

FF80H

FFFFH

External M emory

Fig. On-Chip External Memory Addressed Mapping

(a) Standard 51 Series

Softw are Data Protection

Enable Flow

Load data AAH

address FF55H

Load data 55H

address FF2AH

Load data A0H

address FF55H

Load data AAH

address FF55H

Load data 55H

address FF2AH

Load data 80H

address FF55H

Load data AAH

address FF55H

Load data 55H

address FF2AH

Load data 20H

address FF55H

Softw are Data Protection

Disable Flow

Load data AAH

address FF55H

Load data 55H

address FF2AH

Load data 80H

address FF55H

Load data AAH

address FF55H

Load data 55H

address FF2AH

Load data 10H

address FF55H

Softw are Erase Flow

Software Data Protection and Erase Acquisition Flow

W78E858

Publication Release Date: November 27, 2002

- 7 -

Revision A3

On-chip Flash EPROM

The W78E858 includes two banks of FLASH EPROM. One is 32K bytes of main FLASH EPROM for
application program (APROM) and another 4K bytes of FLASH EPROM for loader program (LDROM)
when operating the in-system programming feature. In normal operation, the micro-controller will
execute the code from the 32K bytes of APROM. By setting program registers, user can force CPU to
switch to the programming mode which will execute the code (loader program) from the 4K bytes of
auxiliary LDROM, and this loader program is going to update the contents of the 32K bytes of
APROM. After chip reset, the micro-controller executes the new application program in the APROM.
This in-system programming feature makes the job easy and efficient in which the application needs
to update firmware frequently. In some applications, the in-system programming feature make it
possible that end-user is able to easily update the system firmware by themselves without opening
the chassis.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of bit
C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator.
The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.

Clock

The W78E858 is designed to use with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used by default. This makes the W78E858 relatively insensitive to
duty cycle variations in the clock.

Crystal Oscillator

The W78E858 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.

Power Management

Idle Mode
The CPU will enter to idle by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

W78E858

- 8 -

Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. There are two ways to exit power-down
mode, one is by a chip reset and another is via external interrupts wake up if the related control flags
are enabled.

Wake-up Via External Interrupts INT0 to INT9
If the external interrupts INT0 to INT9 are enabled, the W78E858 can be awakened from power down
mode with the external interrupts if the EA flag in IE register and related interrupt enable is set before
enter power down mode. To ensure that the oscillator is stable before the controller starts, the internal
clock will remain inactive for some oscillator periods. This is controlled by a on-chip delay counter.
The delay time is software selectable and the reset default value is 1536 periods. By setting the PS2

PS0 bits in AUXR register the delay periods is given as below:

PS2 PS1 PS0 DELAY

PERIODS

DELAY TIME (20 MHZ)

0 0 0

192

0.0096

0 0 1

384

0.0192

0 1 0

768

0.0384

1536

0.0768 mS

1 0 0

3072

0.1536

1 0 1

6144

0.372

1 1 0

12288

0.6144

1 1 1

24576

1.2288

Interrupt IN0~INT9

Oscillator

RESET-Pin

Power-Down

delay counter x Tosc

> 24 x Tosc

....

...

Internal Clock

Fig. Power-Down W ake Up Operation

W78E858

Publication Release Date: November 27, 2002

- 9 -

Revision A3

OR8

W ake Up

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

IX1

IEN1

IRQ1

Fig. Port1 External Interrupt Configuration

Reset

The external RST signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the RA80xx is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.

W78E858 Special Function Registers and Reset Values

F8 +IP1

0000000

F0 +B

00000000

CHPENR

00000000

E8 +IE1

00000000

IX1

00000000

E0 +ACC

00000000

W78E858

- 10 -

W78E858 Special Function Registers and Reset Values, continued

+P4

11111111

D0 +PSW

00000000

C8 +T2CON

00000000

T2MOD

Xxxxxx0x

RCAP2L

00000000

RCAP2H

00000000

TL2

00000000

TH2

00000000

C0 +IRQ1

00000000

SFRAL

00000000

SFRAH

00000000

SFRFD

00000000

SFRCN

00000000

B8 +IP

000000

CHPCON

0xx00000

B0 +P3

00000000

A8 +IE

01000000

A0 +P2

11111111

MXPSR

0xxxxx00

98 +SCON

00000000

SBUF

xxxxxxxx

90 +P1

11111111

PWMCN

Xxxx0000

PWMP

00000000

DAC0

00000000

DAC1

00000000

DAC2

00000000

DAC3

00000000

88 +TCON

00000000

TMOD

00000000

TL0

00000000

TL1

00000000

TH0

00000000

TH1

00000000

AUXR

xxxx0110

WDTC

000xx000

80 +P0

11111111

00000111

DPL

00000000

DPH

00000000

WDTEST

--------

PCON

00110000

Note: the SFRs marked with a plus sign(+) are both byte and bit-addressable.

Pulse Width Modulator System

The pulse width modulator system of W78E858 contains four PWM output channels with a common 8-
bit counter. These channels generate pulses of programmable length and interval. The prescaler and
counter are common to four PWM channels.

PWCON (C3H)

BIT NAME

FUNCTION

- 4

Reverse

PWM3

Enable P1.7 as PWM clock output.

PWM2

Enable P1.6 as PWM clock output.

PWM1

Enable P1.5 as PWM clock output.

PWM0

Enable P1.4 as PWM clock output.

PWMP (92H)
The prescaler is loaded with the complement of the PWMP register during counter overflow. The
repetition frequency is defined by 8-bit prescaler which clocks the counter. The prescaler division
factor = (PWMP + 1). Reading the PWMP gives the current reload value. The actual count of the
prescaler can't be read.

W78E858

Publication Release Date: November 27, 2002

- 11 -

Revision A3

The PWM counter is enabled with any bit PWEn (n = 0, 1, 2, 3) of the PWCON register. Output to the
port pin is separately enabled by setting the PWEn bits in the PWCON register. The PWM function is
reset by a chip reset. In idle mode, the PWM will function as configurated in PWCON. In power-down
state of the PWM will freeze when the internal clock stops. If the chip is awakened with an external
interrupt, the PWM will continue to function its state when power-down was entered.
The repetition frequency is given by:

Fpwm =

Fosc

[255 x (1+PWMP)]

An oscillator frequency of 24 MHz results in a repetition range of 367.65 Hz to 94.12 KHz. The
high/low ratio of PWMn is DACn/(255-DACn) for DACn values except 255. A DACn value 255 results
in a high PWMn output.

PW MEN0

PW MEN1

PW MEN2

PW MEN3

ENDAC

PW MP SFR

8-BIT PRESCALER

8-BIT UP COUNTER

DAC2

8-BIT DETECT

DAC3

DAC0

8-BIT DETECT

DAC1

AND

Fosc

INTERNAL

BUS

OUTPUT

BUFFER

OUTPUT

BUFFER

OUTPUT

BUFFER

OUTPUT

BUFFER

P1.4

P1.5

P1.6

P1.7

Fig. Four Channels 8-Bit PW M Function Block Diagram

In-system Programming System

The W78E858 provided in-system programming function for new firmware updated. After the related
register and flags are set, user can start timer and force the CPU enter idle mode, then W78E858 will
perform the in-system program mode function specify in SFRCN register, the destination data and
address will come from the related SFR.

W78E858

- 12 -

The CHPCON is read only by default. Firmware designer must write 87H, 59H sequentially to this
special register CHPENR to enable the CHPCON write attribute, and write other value to disable
CHPCON write attribute. This register protects from writing to the CHPCON register carelessly.

SFRAL (C4H)
The programming low-order byte address of FLASH EPROM in-system programming mode

SFRAH (C5H)
The programming high-order byte address of FLASH EPROM in-system programming mode

SFRFD (C6H)
The programming data for on-chip FLASH EPROM in-system programming mode

SFRCN (C7H)

BIT NAME

FUNCTION

7 -

Reserve.

6 WFWIN

On-chip FLASH EPROM bank select for in-system programming.
= 0: 32K bytes FLASH EPROM bank is selected as destination for re-

programming.

= 1: 4K bytes FLASH EPROM bank is selected as destination for re-

programming.

OEN

FLASH EPROM output enable.

CEN

FLASH EPROM chip enable.

- 0

CTRL[3:0] The flash control signals

In-system Programming Mode Operating Table

MODE

CTRL<3:0

WFWIN OEN CEN SFRAL SFRAH SFRFD

Erase 32K APROM

0010

Erase 4K LDROM

0010

Program 32K
APROM

0001

Address

Data In

Program 4K LDROM

0001

Address

Data In

Read 32K APROM

0000

Address

Data Out

Read 4K LDROM

0000

Address

Data Out

W78E858

Publication Release Date: November 27, 2002

- 13 -

Revision A3

CHPCON (BFH)

BIT NAME

FUNCTION

SWRESET

(F04KMODE)

When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation.
To read this bit can determine that the F04KBOOT mode is running.

6 -

Reserve.

ENEEPROM Enable on-chip 128 bytes EEPROM.

ENAUXRAM Enable on-chip 512 bytes auxiliary RAM.

- 2

- -

1 FBOOTSL

The loader program location selection.

= 0: loader program in 32K memory bank.
= 1: loader program in 4K memory bank.

0 FPROGEN

In system programming enable flag.

= 1: enable. The CPU switches to the programming flash mode after

entering the idle mode and waken up from interrupt. The CPU will
execute the loader program while in on-chip programming mode.

= 0: disable. The on-chip FLASH EPROM read-only. In-system

programmability is inhibit.

MXPSR (A2H)

BIT NAME

FUNCTION

7 BUSY

EEPROM BUSY signal.
1: EEPROM is writing.

6-2 -

Reserved.

1-0 ADDRPNT

Address pointer by MOVX instruction
0: read or write lower 256 byte Auxiliary RAM by pointer of R0 or R1 register
1: read or write Higher 256 byte Auxiliary RAM by pointer of R0 or R1

2: 128 byte EEPROM by pointer of R0 or R1 register

Interrupt System

External events and the real-time-driven on-chip peripherals require service by the CPU
asynchronous to do execution of any particular section of code. To tie the asynchronous actives of
these functions to normal program execution, a multiple-source, two-priority-level, nested interrupt
system is provided. The W78E858 acknowledges interrupt requests from fourteen sources as below:

· INT0 and INT1

W78E858

- 14 -

· INT0 and INT1
· Timer0 and Timer1
· UART serial I/O
· INT2 to INT9 (at Port1)

External Interrupts INT2 to INT9

Port1 lines serve an alternative purpose at eight additional interrupts INT2 to INT9. When enabled,
each of these lines may "wake-up" the device from power-down mode. Using the IX1 register, the
each pin may be initialized to either active HIGH or LOW. IRQ1 is the interrupt request flag register.
Each flag, if the interrupt is enabled will be set on an interrupt request but must be cleared by
software, i.e. via the interrupt software or when the interrupt is disable.
The Port1 interrupts are level sensitive. A Port1 interrupt will be recognized when a level (HIGH or
LOW depending on Interrupt Polarity Register IX1) on P1.x is held active for at least one machine
cycle. The interrupt request is not served until the next machine cycle.

IE1 (E8H)

BIT NAME

FUNCTION

EX9

Enable external interrupt 9

EX8

Enable external interrupt 8

EX7

Enable external interrupt 7

EX6

Enable external interrupt 6

EX5

Enable external interrupt 5

EX4

Enable external interrupt 4

EX3

Enable external interrupt 3

EX2

Enable external interrupt 2

IP1 (F8H)

BIT NAME

FUNCTION

PX9

External interrupt 9 priority level

PX8

External interrupt 8 priority level

PX7

External interrupt 7 priority level

PX6

External interrupt 6 priority level

PX5

External interrupt 5 priority level

PX4

External interrupt 4 priority level

PX3

External interrupt 3 priority level

PX2

External interrupt 2 priority level

W78E858

Publication Release Date: November 27, 2002

- 15 -

Revision A3

IX1 (E9H)

BIT NAME

FUNCTION

IL9

External interrupt 9 polarity level

IL8

External interrupt 8 polarity level

IL7

External interrupt 7 polarity level

IL6

External interrupt 6 polarity level

IL5

External interrupt 5 polarity level

IL4

External interrupt 4 polarity level

IL3

External interrupt 3 polarity level

IL2

External interrupt 2 polarity level

IRQ1 (C0H)

BIT NAME

FUNCTION

IQ9

External interrupt 9 request flag

IQ8

External interrupt 8 request flag

IQ7

External interrupt 7 request flag

IQ6

External interrupt 6 request flag

IQ5

External interrupt 5 request flag

IQ4

External interrupt 4 request flag

IQ3

External interrupt 3 request flag

IQ2

External interrupt 2 request flag

Interrupt Priority and Vector Address

PRIORITY INTERRUPT VECTOR SOURCE PRIORITY INTERRUPT VECTOR SOURCE

INT0

0003H

External 0

TF1

001BH

Timer 1

INT5

0053H

External 5

SINT

0023H

UART

TF0

000BH

Timer 0

TF2

002BH

Timer 2

INT6

005BH

External 6

INT3

0043H

External 3

INT1

0013H

External 1

INT8

006BH

External 8

INT2

003BH

External 2

INT4

004BH

External 4

INT7

0063H

External 7

INT9

0073H

External 9

W78E858

- 16 -

F04KBOOT Mode (Boot From 4K Bytes LDROM)

The W78E858 boots from APROM program (32K bytes bank) by default after chip reset. On some
occasions, user can force the W78E858 to boot from the LDROM program (4K bank) after chip reset.
The setting for this special mode is as follow.

F04KBOOT Mode

P4.3 P2.7 P2.6

MODE

X L

L FO4KBOOT

L X X FO4KBOOT

Note: In application system design, user must take care the P2, P3, ALE,

and

PSEN

pin status at reset to avoid

W78E858 entering the programming mode or F04KBOOT mode in normal operation.

Enter 4K Reboot Mode Timing

Ts=1us

Th > 24 clocks

P2.6

P2.7

RESET

Security

During the on-chip FLASH EPROM programming mode, the FLASH EPROM can be programmed and
verified repeatedly. Until the code inside the FLASH EPROM is confirmed OK, the code can be
protected. The protection of FLASH EPROM and those operations on it are described below:
The W78E858 has several special setting registers in FLASH EPROM block. Those bits of the
security register can't be changed once they have been programmed from high to low. They can only
be reset through erase-all operation. The security register is located at the FFFFH on the same bank
with 4K LDROM i.e., P3.6 must set high at writer mode.

W78E858

Publication Release Date: November 27, 2002

- 17 -

Revision A3

Security Register

4KB LDROM

FFFFH

0000H

0FFEH

On-Chip

Reversed

Lock Bit (Bit0)
This bit is used to protect the customer's program code in the W78E858. It may be set after the
programmer finishes the programming and verifies sequence. Once these bits are set to logic 0, both
the FLASH EPROM data and all data in FLASH EPROM block can't be accessed again.

MOVC Lock (Bit1)
When this bit is program to "0", the MOVC instruction will be disable when the program counter more
than 7FFFh or

pin is forced low.

Scramble Enable (Bit2)
This bit is used to protect the customer's program code in the W78E858. If this bit is set to logic 0, the
dump ROM code are scrambled by a scramble circuit and the dump ROM code will become a random
ROM code.

Oscillator Gain Select (Bit7)
If this bit is set to logic 0 (for 24 MHz), the EMI effect will be reduce. If this bit is set to logic 1 (for 40
MHz), the W78E858 could to use 40 MHz crystal, but the EMI effect is major. So we provide the
option bit which could be chose by customer.

Watch Dog Timer

For more system reliability, W78E858 provides a programmable watch-dog time-out reset function.
From programming prescaler select, user can choose a variable prescaler from divided by 2 to divided
by 256 to get a suitable time-out period. The time-out period is given by:

tim e-out

Fosc

PRESCALER

x 1000 x 12 (mS)

(Note: Fosc unit = Hz)

W78E858

- 18 -

WDTC (8FH)

BIT NAME

FUNCTION

ENW

Enable watch-dog timer if set.

6 CLRW

Clear watch-dog timer and prescaler if set. This flag will be cleared auto-
matically.

5 WIDL

If this bit is set, watch-dog is enabled under idle mode. If cleared, watch-dog
is disable under idle mode. Default is cleared.

- 3

- Reversed.

PS2

Watch-dog prescaler timer select.

PS1

Watch-dog prescaler timer select.

PS0

Watch-dog prescaler timer select.

PS2 PS1 PS0 PRESCALER

SELCET WATCH-DOG TIME-OUT PERIOD (F

OSC

= 20 MHz)

0 0 0

19.66

0 0 1

39.32

0 1 0

78.64

0 1 1

157.28

1 0 0

314.57

1 0 1

629.14

1 1 0

128

1.25

1 1 1

256

2.52

Programmable Clock-out

A 50% duty cycle clock can be programmed to come out on P1.0. To configure the timer/counter2 as
a clock generator, bit C/T2 in T2CON register must be cleared and bit T2OE in T2MOD register must
be set. Bit TR2 (T2CON.2) also must be set to start timer. The clock-out frequency depends on the
oscillator frequency and reload value of Timer2 capture register (RCAP2H, RCAP2L) as shown in this
equation:

))

(

65536

(

RCAP

frequency

oscillatot

In the clock-out mode, timer2 roll-overs will not generate an interrupt. This is similar to when it is used
as a baud-rate generator. It is possible to use Timer2 as a baud-rate generator and a clock and a
clock generator simultaneously.

Reduce EMI Emission

The transition of ALE will cause noise, so it cab be turned off to reduce the EMI emission if it is
useless. Turn off the ALE signal transition only need too set the ALEOFF flag in the AUXR register
When ALE is turned off, it will be reactived when program access external ROM or RAM data or jump
to execute external ROM code. After access completely or program returns to internal ROM code,
ALE signal will turn off again.

W78E858

Publication Release Date: November 27, 2002

- 19 -

Revision A3

PRESCALER

14-BIT TIMER

EXTERNAL RESET

SYSTEM RESET

ENW

W IDL

IDLE

Fosc

1/12

CLRW

Fig. 17-BIT W atch-Dog Timer Function Block Diagram

7. ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL

MIN. MAX.

UNIT

DC Power Supply

- V

-0.3 +6.0

Input Voltage

Vin

-0.3

+0.3

Operating Temperature

°C

Storage Temperature

Tst

-55

+150

°C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

8. D.C. ELECTRICAL CHARACTERISTICS

= 5V

±10%, T

= 25

° C, Fosc = 20 MHz, unless otherwise specified.)

SPECIFICATION

PARAMETER SYM.

MIN. MAX. UNIT

TEST CONDITIONS

Operating Voltage

4.5

5.5

RST = 1, P0 = V

Operating Current

- 20

No load
V

= 5.5V

Idle Current

IDLE

- 6

Idle mode
V

= 5.5V

Power Down Current

PWDN

- 50

µA

Power-down mode
V

= 5.5V

Input Current
P1, P2, P3, P4

IN1

-50 +10

µA

= 5.5V

= 0V or V

Input Current
RST

IN2

-10 +300

µA

= 5.5V

0 < V

< V

Input Leakage Current

P0,

-10 +10

µA

= 5.5V

0 < V

< V

W78E858

- 20 -

D.C. Electrical Characteristics, continued

SPECIFICATION

PARAMETER SYM.

MIN. MAX. UNIT

TEST CONDITIONS

Logic 1 to 0 Transition
Current
P1, P2, P3, P4

[*4]

-500 -

µA

= 5.5V

= 2.0V

Input Low Voltage

P0, P1, P2, P3, P4,

IL1

0 0.8 V

= 4.5V

Input Low Voltage
RST

IL2

0 0.8 V

= 4.5V

Input Low Voltage
XTAL1

[*4]

IL3

0 0.8 V

= 4.5V

Input High Voltage

P0, P1, P2,

P3, P4,

IH1

2.4

+0.2

V V

= 5.5V

Input High Voltage
RST

IH2

3.5

+0.2

V V

= 5.5V

Input High Voltage
XTAL1

[*4]

IH3

3.5

+0.2

V V

= 5.5V

Output Low Voltage
P1, P2, P3, P4

OL1

- 0.45 V

= 4.5V

= +2 mA

Output Low Voltage

P0, ALE,

PSEN

[*3]

OL2

- 0.45 V

= 4.5V

= +4 mA

Sink Current
P1, P3, P4

SK1

4 12 mA

= 4.5V

= 0.45V

Sink Current

P0, P2, ALE,

PSEN

SK2

10 20 mA

= 4.5V

= 0.45V

Output High Voltage
P1, P2, P3, P4

OH1

2.4 - V

= 4.5V

= -100

µA

Output High Voltage

P0, ALE,

PSEN

[*3]

OH2

2.4 - V

= 4.5V

= -400

µA

Source Current
P1, P2, P3, P4

SR1

-120 -250

µA

= 4.5V

= 2.4V (latch)

Source Current

P0, P2, ALE,

PSEN

SR2

-8 -20 mA

= 4.5V

= 2.4V

Notes:

*1. RST pin is a Schmitt trigger input.

*3. P0, ALE and

PSEN are tested in the external access mode.

*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V

approximates to 2V.

W78E858

Publication Release Date: November 27, 2002

- 21 -

Revision A3

9. AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T

), and actual parts will

usually experience less than a

±20 nS variation. The numbers below represent the performance

expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

OP,

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

0 -

MHz

Clock Period

- - nS 2

Clock High

10 - - nS 3

Clock Low

10 - - nS

Notes:
1. The clock may be stopped indefinitely in either state.
2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

- - nS 4

Address Hold from ALE Low

AAH

1 T

- - nS

ALE Low to

PSEN Low

APL

1 T

- - nS 4

PSEN Low to Data Valid

PDA

- -

nS 2

Data Hold after

PSEN

High

PDH

1 T

nS 3

Data Float after

PSEN

High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN

Pulse Width

PSW

3 T

Notes:
1. P0.0

- P0.7, P2.0 - P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.
4. "

" (due to buffer driving delay and wire loading) is 20 nS.

W78E858

- 22 -

Data Read Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

ALE Low to

Low

dar

3 T

CP+

nS 1,

Low to Data Valid

dda

- -

nS 1

Data Hold from

High

ddh

2 T

Data Float from

High

ddz

0 -

Pulse Width

drd

6 T

Notes:
1. Data memory access time is 8 T

2. "

" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to

Low

DAW

3 T

Data Valid to

Low

DAD

1 T

- - nS

Data Hold from

High

DWD

1 T

- - nS

Pulse Width

DWR

6 T

Note: "

" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

- - nS

Port Input Hold from ALE Low

PDH

0 - - nS

Port Output to ALE

PDA

- - nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

Flash Mode Timing

PARAMETER SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Reset Valid

9 10 11

µS

Enter Flash Mode Reset Low

EFRL

9 10 11

µS

Program Pulse High

PPH

18 20 22

µS

Program Pulse Low

PPL

40 50 60

µS

Erase Pulse Low

EPL

25 30 50 mS -

Read Pulse Low

RPL

1.35 1.5 1.65

µS

Address PreFix

APF

45 50 55 nS -

Data Remain

81 90 99 nS -

W78E858

Publication Release Date: November 27, 2002

- 25 -

Revision A3

11. TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

O0 11
O1 12
O2 13
O3 15
O4 16
O5 17
O6 18

O7 19

2764

AD0

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74LS373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

43
42
41

37
36

25
26

27
28
29
30
31

P0.0
P0.1

P0.2
P0.3
P0.4
P0.5

P0.6
P0.7

P2.0

P2.1
P2.2
P2.3
P2.4

P2.5
P2.6

P2.7

PSEN 32

ALE 33

TXD 13
RXD

W78E858

10 u

8.2 K

CRYSTAL

AD1

AD2

AD3

AD4

AD5
AD6
AD7

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3

A4
A5
A6
A7

A1
A2

A3
A4
A5
A6

A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10

A11
A12

A13
A14

A15

GND

A9
A10

A11
A12

A13
A14
A15

Figure A

CRYSTAL C1

C2 R

6 MHz

68P

- 100P

68P

- 100P

6.8K

16 MHz

20P

- 100P

20P

- 100P

6.8K

24 MHz

10P

- 68P

10P

- 68P

6.8K

32 MHz

- 20P

6.8K

40 MHz

3.3K

Above table shows the reference values for crystal applications.

Notes:

1. C1, C2, R components refer to Figure A

2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.

W78E858

- 26 -

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

10 u

8.2 K

OSCILLATOR

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.0 43

P0.1 42

P0.2 41

P0.3 40

P0.4 39

P0.5 38

P0.6 37

P0.7 36

P2.0

P2.1 25

P2.2

P2.3 27

P2.4

P2.5

P2.6

P2.7 31

PSEN 32

ALE

TXD

RXD 11

W78E858

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0
AD1

AD2

AD3
AD4

AD5

AD6

AD7

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74LS373

A0
A1

A4
A5

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A10

A11

A12

A13

A14

A9
A10

A11

A12

A13
A14
CE

GND

A10

A11

A12

A13

A14

GND

20256

Figure B

W78E858

Publication Release Date: November 27, 2002

- 27 -

Revision A3

12. PACKAGE DIMENSIONS

40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

44-pin PLCC

Seating Plane

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

W78E858

- 28 -

Package Dimensions, continued

44-pin PQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,
Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78E858/P/F

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78E858/P/F