W78LE812

8-BIT MTP MICROCONTROLLER

Publication Release Date: February 1999

- 1 -

Revision A2

GENERAL DESCRIPTION

The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages
with low power consumption. The instruction set for the W78LE812 is fully compatible with the
standard 8051. The W78LE812 contains an 8K bytes MTP ROM (Multiple-Time Programmable
ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 6-bit I/O
port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals
are supported by a fourteen sources two-level interrupt capability. To facilitate programming and
verification, the MTP-ROM inside the W78LE812 allows the program memory to be programmed and
read electronically. Once the code is confirmed, the user can protect the code for security.

The W78LE812 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

Fully static design 8-bit CMOS microcontroller

Wide supply voltage of 2.4V to 5.5V

256 bytes of on-chip scratchpad RAM

8 KB electrically erasable/programmable MTP-ROM

64 KB program memory address space

64 KB data memory address space

Four 8-bit bi-directional ports

Three 16-bit timer/counters

Timer 2 Clock-out

One full duplex serial port(UART)

Watchdog Timer

Direct LED drive outputs

Fourteen sources, two-level interrupt capability

Wake-up via external interrupts at Port 1

EMI reduction mode

Built-in power management

Code protection mechanism

Packages:

DIP 40: W78LE812-24

PLCC 44: W78LE812P-24

PQFP 44: W78LE812F-24

W78LE812

- 2 -

PIN CONFIGURATIONS

VDD

P0.0, AD0

P0.1, AD1

P0.2, AD2

P0.3, AD3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA,VPP
ALE,P4.5

PSEN,P4.6

P2.5, A13

P2.6, A14

P2.7, A15

P2.0, A8

P2.1, A9

P2.2, A10

P2.3, A11

P2.4, A12

INT2,,T2, P1.0

40-Pin DIP (W78LE812)

INT4,P1.2

INT5,P1.3

INT6,P1.4

INT7,P1.5

INT8,P1.6

A9CTRL,RXD, P3.0

A13CTR,LTXD, P3.1

INT9,P1.7

RST

A14CTRL,INT0, P3.2

OECTRL,INT1, P3.3

T0, P3.4

T1, P3.5

CE,WR, P3.6

OE,RD, P3.7

XTAL1

XTAL2

VSS

INT3,T2EX, P1.1

44-Pin PLCC (W78LE812P)

44-Pin PQFP (W78LE812F)

1 44 43 42 41

39
38

30
29

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA,VPP

ALE,P4.5

PSEN,P4.6
P2.7, A15

P2.6, A14

P2.5, A13

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P4.1

P
4
.
0

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

P
4
.
2

N
T

T
6

N
T
5

N
T
4

N
T
2

INT7,P1.5
INT8,P1.6

INT9,P1.7

RST

A9CTRL,RXD, P3.0

A13CTRL,TXD, P3.1

A14CTRL,INT0, P3.2

OECTRL,INT1, P3.3

T0, P3.4

T1, P3.5

P4.3

40 39 38 37 36 35

44 43 42 41

33
32

24
23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA,VPP

ALE,P4.5

PSEN,P4.6

P2.7, A15

P2.6, A14

P2.5, A13

X
T
A
L
1

V
S
S

P
2
.
4
,
A
1
2

P
2
.
3
,
A
1
1

P
2
.
2
,
A
1
0

P
2
.
1
,
A
9

P
2
.
0
,
A
8

X
T
A
L
2

P
3
.
7
,
/
R
D

P
3
.
6
,
/
W
R

P
4
.
0

P4.1

A
D
3
,
P
0
.
3

T
2
,
P
1
.
0

P
1
.
2

V
D
D

A
D
2
,
P
0
.
2

A
D
1
,
P
0
.
1

A
D
0
,
P
0
.
0

2
E
X
,
P
1
.
1

P
1
.
3

P
1
.
4

P
4
.
2

N
T
3

T
6

N
T

N
T
4

N
T
2

C
E

O
E

INT7,P1.5
INT8,P1.6

INT9,P1.7

RST

A9CTRL,RXD, P3.0

A13CTRL,TXD, P3.1

A14CTRL,INT0, P3.2

OECTRL,INT1, P3.3

T0, P3.4

T1, P3.5

P4.3

C
E

O
E

W78LE812

Publication Release Date: February 1999

- 3 -

Revision A2

PIN DESCRIPTION

SYMBOL

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external
ROM. It should be kept high to access internal ROM. The ROM address and data will
not be present on the bus if

pin is high and the program counter is within on-chip

ROM area. Otherwise they will be present on the bus.

PSEN

PROGRAM STORE ENABLE:

PSEN

enables the external ROM data onto the Port 0

address/data bus during fetch and MOVC operations. When internal ROM access is
performed, no

PSEN

strobe signal outputs from this pin. This pin also serves the

alternative function P4.6.

ALE

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0. This pin also serves the alternative function P4.5

RST

RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.

XTAL1

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.

XTAL2

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

POWER SUPPLY: Supply voltage for operation.

P0.0

P0.7

PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.

P1.0

P1.7

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
INT2

INT9 (P1.0

P1.7):External interrupt 2 to 9

P2.0

P2.7

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0

P3.7

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7
can be configured with high sink current which can drive LED displays directly. All bits
have alternate functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output

INT0

(P3.2) : External Interrupt 0

INT1

(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input

(P3.6) :External Data Memory Write Strobe

(P3.7) : External Data Memory Read Strobe

P4.0-P4.6

PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are
available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative
function corresponding to ALE and

PSEN

W78LE812

- 4 -

BLOCK DIAGRAM

P3.0

P3.7

P1.0

P1.7

ALU

Port 0

Latch

Port 1

Latch

Timer

Port

UART

XTAL1

PSEN

ALE

Vss

VCC

RST

XTAL2

Oscillator

Interrupt

PSW

Instruction

Decoder

Sequencer

Reset Block

Bus & Clock

Controller

SFR RAM

Address

Power control

256 bytes

RAM & SFR

Stack

Pointer

Addr. Reg.

Incrementor

DPTR

Temp Reg.

ACC

Port 3

Latch

Port 4

Latch

Port

Port 2

Latch

P4.0

P4.6

Port

Port
0

Port
2

P2.0

P2.7

P0.0

P0.7

INT2~9

Watchdog

Timer

FUNCTIONAL DESCRIPTION

The W78LE812 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.

Timers 0, 1, and 2

Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control
functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a special feature of the W78LE812: it is a 16-bit up/down
counter that is configured and controlled by the T2CON and T2MOD registers. Like Timers 0 and 1,
Timer 2 can operate as either an external event counter or as an internal timer, depending on the

W78LE812

Publication Release Date: February 1999

- 5 -

Revision A2

setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate
generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In
the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When
counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The
Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode,
timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE
(T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 roll-
overs will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and
the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by
following equation:

Clock-out Frequency = Oscillator Frequency / [ 4

( 65536 - RCAP2H, RCAP2L ) ]

OSC

1/2

T2 (P1.0)

T2CON.6

TR2 (T2CON.2)

T2EX (P1.1)

EXEN2 (T2CON.3)

EXF2

Timer 2

Interrupt

TH2

TL2

RCAP2H

RCAP2L

1/2

Timer 2 Clock-Out Mode

TIMER 2 MODE CONTROL

Bit:

T2OE

Mnemonic: T2MOD

Address: C9h

T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function.

I/O Port Options

The Port 0 and Port 3 of W78LE812 may be configured with different types by setting the bits of the
Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either
the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-
directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a
quasi-bi-directional I/O port with internal pull-up that is structurally the same as Port 2. The high
nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by
setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink
about 20mA current for driving LED display directly. After reset, the POR register is cleared and the
pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below.

W78LE812

- 6 -

Port Options Register

Bit:

EP6

EP5

HD7

HD6

HD5

HD4

PUP

Mnemonic: POR

Address: 86H

PUP : Enable Port 0 weak pull-up.

HD4

7 : Enable pins P3.4 to P3.7 individually with High Drive outputs.

EP5 : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5.

EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6

Port 4

The W78LE812 has one additional bit-addressable I/O port P4 in which the port address is D8H. The
Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and

P4.6 are the alternate function corresponding to pins ALE, PSEN . When program is running in the
internal memory without any access to external memory, ALE and PSEN may be individually
configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable
I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the, ALE

and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be
enabled by software. Care must be taken with the ALE pins when configured as the alternate
functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register
is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O
port P4.5.

Port 4

Bit:

P4.6

P4.5

P4.3

P4.2

P4.1

P4.0

Mnemonic: P4

Address: D8H

Interrupt System

The W78LE812 has twelve interrupt sources:

INT0

and

INT1

; Timer 0,1 and 2; Serial Port; INT2 to

INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine.
Each of these sources can be individually enabled or disabled by setting or clearing the
corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level
depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are
level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts
can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ
register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when a interrupt
request is recognized but

must be cleared by software. Note that the interrupt flags have to be

cleared before the interrupt service routine is completed, or else another interrupt will be generated.

W78LE812

Publication Release Date: February 1999

- 7 -

Revision A2

Interrupt Enable Register 0

Bit:

ET2

ET1

EX1

ET0

EX0

Mnemonic: IE

Address: A8H

EA : Global enable. Enable/disable all interrupts.
ET2: Enable Timer 2 interrupt.
ES : Enable Serial Port interrupt.
ET1: Enable Timer 1 interrupt
EX1: Enable external interrupt 1
ET0: Enable Timer 0 interrupt
EX0: Enable external interrupt 0

Interrupt Enable Register 1

Bit:

EX9

EX8

EX7

EX6

EX5

EX4

EX3

EX2

Mnemonic: IE1

Address: E8H

EX9: Enable external interrupt 9

Note: 0 = interrupt disabled, 1 = interrupt enabled.

EX8: Enable external interrupt 8
EX7: Enable external interrupt 7
EX6: Enable external interrupt 6
EX5: Enable external interrupt 5
EX4: Enable external interrupt 4
EX3: Enable external interrupt 3
EX2: Enable external interrupt 2

Interrupt Priority Register 0

Bit:

PS1

PT2

PT1

PX1

PT0

PX0

Mnemonic: IP0

Address: B8h

IP.7: Unused.
PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level.
PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.
PS : This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.
PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.
PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.
PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.
PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

W78LE812

- 8 -

Interrupt Priority Register 1

Bit:

PX9

PX8

PX7

PX6

PX5

PX4

PX3

PX2

Mnemonic: IP1

Address: F8h

PX9: This bit defines the External interrupt 9 priority. PX9 = 1 sets it to higher priority level.
PX8: This bit defines the External interrupt 8 priority. PX8 = 1 sets it to higher priority level.
PX7: This bit defines the External interrupt 7 priority. PX7 = 1 sets it to higher priority level.
PX6: This bit defines the External interrupt 6 priority. PX6 = 1 sets it to higher priority level.
PX5: This bit defines the External interrupt 5 priority. PX5 = 1 sets it to higher priority level.
PX4: This bit defines the External interrupt 4 priority. PX4 = 1 sets it to higher priority level.
PX3: This bit defines the External interrupt 3 priority. PX3 = 1 sets it to higher priority level.
PX2: This bit defines the External interrupt 2 priority. PX2 = 1 sets it to higher priority level.

Interrupt Polarity Register

Bit:

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

Mnemonic: IX

Address: E9H

IL9: External interrupt 9 polarity level.
IL8: External interrupt 8 polarity level.
IL7: External interrupt 7 polarity level.
IL6: External interrupt 6 polarity level.
IL5: External interrupt 5 polarity level.
IL4: External interrupt 4 polarity level.
IL3: External interrupt 3 polarity level.
IL2: External interrupt 2 polarity level.
Note: 0 = active LOW, 1 = active HIGH.

Interrupt Request Flag Register

Bit:

IQ9

IQ8

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

Mnemonic: IRQ

Address: C0H

IQ9: External interrupt 9 request flag.
IQ8: External interrupt 8 request flag.
IQ7: External interrupt 7 request flag.
IQ6: External interrupt 6 request flag.
IQ5: External interrupt 5 request flag.
IQ4: External interrupt 4 request flag.
IQ3: External interrupt 3 request flag.
IQ2: External interrupt 2 request flag.

W78LE812

Publication Release Date: February 1999

- 9 -

Revision A2

Table.1 Priority level for simultaneous requests of the same priority interrupt sources

SOURCE

FLAG

PRIORITY LEVEL

VECTOR ADDRESS

External Interrupt 0

IE0

(highest)

0003H

Serial Port

RI + TI

0023H

External Interrupt 5

IQ5

0053H

Timer 0 Overflow

TF0

000BH

External Interrupt 6

IQ6

005BH

External Interrupt 1

IE1

0013H

External Interrupt 2

IQ2

003BH

External Interrupt 7

IQ7

0063H

Timer 1 Overflow

TF1

001BH

Timer 2 Overflow

TF2 + EXF2

002BH

External Interrupt 3

IQ3

0043H

External Interrupt 8

IQ8

006BH

External Interrupt 4

IQ4

004BH

External Interrupt 9

IQ9

(lowest)

0073H

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

ENW

CLRW

WIDL

PS2

PS1

PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled

under IDLE mode. Default is cleared.

W78LE812

- 10 -

PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2

0 as follows:

PS2 PS1 PS0

PRESCALER SELECT

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

128

1 1 1

256

The time-out period is obtained using the following equation :

1000 12

OSC

PRESCALER

Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.

OSC

1/12

PRESCALER

14-BIT TIMER

CLEAR

CLRW

EXTERNAL

RESET

INTERNAL

RESET

WIDL

IDLE

ENW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

0 0 0

19.66 mS

0 0 1

39.32 mS

0 1 0

78.64 mS

0 1 1

157.28 mS

1 0 0

314.57 mS

1 0 1

629.14 mS

1 1 0

1.25 s

1 1 1

2.50 s

W78LE812

Publication Release Date: February 1999

- 11 -

Revision A2

Clock

The W78LE812 is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78LE812 relatively insensitive to duty
cycle variations in the clock. The W78LE812 incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator.

AUXR - Auxiliary Register

Bit:

Mnemonic: AUXR

Address: 8Eh

AO:

Turn off ALE signal.

Reduce EMI Emission

Because of the on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space..

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78LE812 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

W78LE812

- 12 -

ON-CHIP MTP ROM CHARACTERISTICS

The W78LE812 has several modes to program the on-chip MTP-ROM. All these operations are
configured by the pins RST, ALE,

PSEN

, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),

OECTRL(P3.3),

(P3.6),

(P3.7), A0(P1.0) and V

(

). Moreover, the A15

A0(P2.7

P2.0,

P1.7

P1.0) and the D7

D0(P0.7

P0.0) serve as the address and data bus respectively for these

operations.

READ OPERATION

This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.

OUTPUT DISABLE CONDITION

When the

is set to high, no data output appears on the D7..D0.

PROGRAM OPERATION

This operation is used to program the data to MTP ROM and the security bits. Program operation is
done when the V

is reach to V

(12.5V) level,

set to low, and

set to high.

PROGRAM VERIFY OPERATION

All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.

ERASE OPERATION

An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP
ROM cells and the security bits from 0 to 1. This erase operation is done when the V

is reach to

level,

set to low, and

set to high.

ERASE VERIFY OPERATION

After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if V

= V

(14.5V),

is high and

is low.

PROGRAM/ERASE INHIBIT OPERATION

This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(

) = V

, P3.7(

) = V

, erasing or programming of non-targeted chips is inhibited. So,

except for the P3.6 and P3.7 pins, the individual chips may have common inputs.

W78LE812

Publication Release Date: February 1999

- 13 -

Revision A2

COMPANY/DEVICE ID READ OPERATION

This operation is supported for MTP ROM programmer to get the company ID or device ID on the
W78LE812.

OPERATIONS

P3.0

(A9

CTRL)

P3.1
(A13

CTRL)

P3.2
(A14

CTRL)

P3.3

(OE

CTRL)

P3.6
(

)

P3.7

(

)

P2,P1

(A15..A0)

(D7..D0)

NOTES

Read

Address

Data Out

Output Disable

Hi-Z

Program

Address

Data In

Program Verify

Address

Data Out

Erase

A0:0,

others: X

Data In

0FFH

Erase Verify

Address

Data Out

Program/Erase
Inhibit

Company ID

A0 = 0

Data Out

Device ID

A0 = 1

Data Out

Notes:

1. All these operations happen in RST = V

, ALE = V

and PSEN

= V

2. V

= 12.5V, V

= 14.5V, V

= V

, V

= V

3. The program verify operation follows behind the program operation.

4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits.

5. The erase verify operation follows behind the erase operation.

SECURITY BITS

During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified
repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The
protection of MTP ROM and those operations on it are described below.
The W78LE812 has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in normal mode. These registers can only
be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be
changed once they have been programmed from high to low. They can only be reset through erase-
all operation.

The contents of the Company ID and Device ID registers have been set in factory. Both registers are
addressed by the A0 address line during the same specific condition.

The Security Register is addressed in the MTP-ROM operation mode by address #0FFFFh.

W78LE812

- 14 -

B0 : Lock bit, logic 0 : active

B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.

Default 1 for each bit.

Special Setting Registers

Company ID (#DAH)

Device ID (#E0H)

Security Bits

8KB MTP ROM

Program Memory

Reserved

Security Register

0FFFFh

0000h

1FFFh

Reserved

B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable

Lock bit
This bit is used to protect the customer's program code in the W78LE812. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.

MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.

Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

EA/Vpp

ALE

RST

PSEN

Vss

A0 to A7

A8 to A15

PGM DATA

+5V

Programming Configuration

P3.0

P3.1

P3.2

P3.3

P3.6

P3.7

X'tal1

X'tal2

EA/Vpp

ALE

RST

PSEN

Vss

A0 to A7

A8 to A15

PGM DATA

+5V

Programming Verification

W78LE812

Publication Release Date: February 1999

- 15 -

Revision A2

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

DC Power Supply

-0.3

+7.0

Input Voltage

-0.3

+0.3

Operating Temperature

Storage Temperature

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

DC CHARACTERISTICS

= 0V, TA = 25

C, unless otherwise specified.

SYMBOL

PARAMETER

SPECIFICATION

TEST CONDITIONS

MIN.

MAX.

UNIT

Operating Voltage

2.4

5.5

Operating Current

= 5.5V, 20 Mhz, no load,

RST = 1

= 2.4V, 12 Mhz, no load,

RST = 1

IDLE

Idle Current

= 5.5V, 20 Mhz, no load

1.5

= 2.4V, 12 Mhz, no load

PWDN

Power Down Current

= 5.5V, no load

= 2.4V, no load

Input

Input Current
P1, P2, P3, P4

-50

+10

= 5.5V

= 0V or V

Input Leakage Current

P0,

-10

+10

= 5.5V

IN2

Input Current RST

-10

= 5.5V

LK1

Input Leakage Current

P0,

-60

+300

= 5.5V

Logic 1-to-0 Transition
Current P1, P2, P3, P4

-500

= 5.5V

= 2V

IL1

Input Low Voltage

0.8

= 5.5V

P1, P2, P3, P4

0.5

= 2.4V

IL2

Input Low Voltage

0.8

= 5.5V

RST

[*3]

0.3

= 2.4V

W78LE812

- 16 -

DC Characteristics, continued

SYMBOL

PARAMETER

SPECIFICATION

TEST CONDITIONS

MIN.

MAX.

UNIT

IL3

Input Low Voltage

0.8

= 5.5V

XTAL1

[*3]

0.6

= 2.4V

IH1

Input High Voltage

3.5

+0.2

= 5.5V

P1, P2, P3, P4,

1.6

+0.2

= 2.4V

IH2

Input High Voltage

3.5

+0.2

= 5.5V

RST

1.7

+0.2

= 2.4V

IH3

Input High Voltage

3.5

+0.2

= 5.5V

XTAL1

[*4]

1.6

+0.2

= 2.4V

Output

OL1

Output Low Voltage

0.45

= 4.5V, I

= +2 mA

P1, P2, P3, P4

0.25

= 2.4V, I

= +1 mA

OL2

Output Low Voltage

0.45

= 4.5V, I

= +4 mA

P0, ALE, PSEN

[*4]

0.25

= 2.4V, I

= +2 mA

OL3

Output Low Voltage P3

[*6]

0.22

= 4.5V, I

= +2 mA

SK1

Sink current

= 4.5V, V

= 0.45V

P1, P2, P3

[5]

, P4<0:4>

1.8

5.4

= 2.4V, V

= 0.4V

SK2

Sink current

= 4.5V, V

= 0.45V

P0, ALE, PSEN , P4<5:6>

4.5

= 2.4V, V

= 0.4V

SK3

Sink current P3.4 to P3.7

= 4.5V, V

= 0.45V

in High-Drive mode

OH1

Output High Voltage

2.4

= 4.5V, V

= -100

P1, P2, P3, P4

1.4

= 2.4V, V

= -20

OH2

Output High Voltage

2.4

= 4.5V, I

= -400

P0, ALE, PSEN

[*4]

1.4

= 2.4V, I

= -200

SR1

Source current

-120

-250

= 4.5V, V

= 2.4V

P1, P2, P3, P4<0:4>

-20

-40

= 2.4V, V

= 1.4V

SR2

Source current

-10

-14

= 4.5V, V

= 2.4V

P0, ALE, PSEN , P4<5:6>

-1.9

-3.3

= 2.4V, V

= 1.4V

Notes:
*1. RST pin has an internal pull-down.
*2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0.
*3. RST is a Schmitt trigger input and XTAL1 is a CMOS input.

*4. P0, P2, ALE and PSEN are tested in the external access mode.
*5. P3.4 to P3.7 are in normal mode.
*6. P3(P3.4

P3.7) is used LED driver port by set SFR.

W78LE812

Publication Release Date: February 1999

- 17 -

Revision A2

AC CHARACTERISTICS

The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T

), and actual parts will

usually experience less than a

20 nS variation. The numbers below represent the performance

expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.

Clock Input Waveform

XTAL1

OP,

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Operating Speed

MHz

Clock Period

Clock High

Clock Low

Notes:
1. The clock may be stopped indefinitely in either state.
2. The T

specification is used as a reference in other specifications.

3. There are no duty cycle requirements on the XTAL1 input.

Program Fetch Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

Address Valid to ALE Low

AAS

1 T

Address Hold from ALE Low

AAH

1 T

1, 4

ALE Low to

PSEN Low

APL

1 T

PSEN Low to Data Valid

PDA

2 T

Data Hold after PSEN High

PDH

1 T

Data Float after PSEN High

PDZ

1 T

ALE Pulse Width

ALW

2 T

PSEN Pulse Width

PSW

3 T

Notes:
1. P0.0

P0.7, P2.0

P2.7 remain stable throughout entire memory cycle.

2. Memory access time is 3 T

3. Data have been latched internally prior to PSEN going high.
4. "

" (due to buffer driving delay and wire loading) is 20 nS.

W78LE812

- 18 -

Data Read Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

NOTES

ALE Low to RD Low

DAR

3 T

1, 2

RD Low to Data Valid

DDA

4 T

Data Hold from RD High

DDH

2 T

Data Float from RD High

DDZ

2 T

RD Pulse Width

DRD

6 T

Notes:

1. Data memory access time is 8 T

2. "

" (due to buffer driving delay and wire loading) is 20 nS.

Data Write Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

ALE Low to WR Low

DAW

3 T

Data Valid to WR Low

DAD

1 T

Data Hold from WR High

DWD

1 T

WR Pulse Width

DWR

6 T

Note: "

" (due to buffer driving delay and wire loading) is 20 nS.

Port Access Cycle

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Port Input Setup to ALE Low

PDS

1 T

Port Input Hold from ALE Low

PDH

Port Output to ALE

PDA

1 T

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

W78LE812

Publication Release Date: February 1999

- 19 -

Revision A2

Program Operation

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

Setup Time

VPS

2.0

Data Setup Time

2.0

Data Hold Time

2.0

Address Setup Time

2.0

Address Hold Time

Program Pulse Width for

Program Operation

PWP

290

300

310

OECTRL Setup Time

OCS

2.0

OECTRL Hold Time

OCH

2.0

Setup Time

OES

2.0

High to Output Float

DFP

130

Data Valid from

OEV

150

Note: Flash data can be accessed only in flash mode. The RST pin must pull in V

status, the ALE pin must pull in V

status, and

the PSEN pin must pull in V

status.

TIMING WAVEFORMS

Program Fetch Cycle

XTAL1

ALE

PORT 2

A0-A7

Data

A0-A7

Code

A0-A7

Data

Code

PORT 0

PSEN

PDH,

PDZ

PDA

AAH

AAS

PSW

APL

ALW

W78LE812

- 22 -

TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

AD0

A10

A11

A12

A13

A14

A15

O1 12
O2 13
O3 15
O4 16
O5 17
O6 18
O7 19

27512

AD0

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74373

AD0

XTAL1

XTAL2

RST

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

39
38
37
36
35

34
33
32

21
22
23
24
25
26
27
28

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

PSEN 29

ALE 30

TXD 11
RXD

W78LE812

10 u

8.2 K

CRYSTAL

AD1
AD2
AD3
AD4
AD5
AD6

AD7

AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

A1
A2
A3
A4
A5
A6

A1
A2
A3
A4
A5
A6
A7
A8
A9

AD1
AD2
AD3
AD4
AD5
AD6
AD7

A10

A11
A12

A13

A14
A15

GND

A9
A10
A11
A12
A13
A14
A15

Figure A

CRYSTAL

16 MHz

30P

24 MHz

15P

Above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

W78LE812

Publication Release Date: February 1999

- 23 -

Revision A2

Typical Application Circuits, continued

Expanded External Data Memory and Oscillator

10 u

8.2 K

OSCILLATOR

XTAL1

XTAL2

RST

INT0

INT1

1
2
3
4
5
6

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6

P1.7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

W78LE812

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

AD0
AD1
AD2
AD3
AD4
AD5
AD6

AD7

A0
A1
A2
A3
A4
A5
A6
A7

Q0 2

Q1 5

Q2 6

Q3 9

Q4 12

Q5 15

Q6 16

Q7 19

74373

A0
A1
A2
A3
A4
A5
A6
A7

9
8
7
6
5
4
3

A0
A1
A2
A3
A4
A5
A6
A7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

11
12
13
15
16
17
18
19

D0
D1
D2
D3
D4
D5
D6
D7

A8
A9
A10
A11
A12
A13
A14

25
24
21
23

A8
A9
A10
A11
A12
A13
A14

GND

A10
A11
A12
A13
A14

GND

22
27

20256

Figure B

W78LE812

- 24 -

PACKAGE DIMENSIONS

40-pin DIP

Seating Plane

1. Dimension D Max. & S include mold flash or

tie bar burrs.

2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

6. General appearance spec. should be based on

final visual inspection spec.

1.372

1.219

0.054

0.048

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

0.050

1.27

0.210

5.334

0.010

0.150

0.016

0.155

0.018

0.160

0.022

3.81

0.406

0.254

3.937

0.457

4.064

0.559

0.008

0.120

0.670

0.010

0.130

0.014

0.140

0.203

3.048

0.254

3.302

0.356

3.556

0.540

0.550

0.545

13.72

13.97

13.84

17.01

15.24

14.986

15.494

0.600

0.590

0.610

2.286

2.54

2.794

0.090

0.100

0.110

c
D

2.055

2.070

52.20

52.58

0.090

2.286

0.650

0.630

16.00

16.51

protrusion/intrusion.

4. Dimension B1 does not include dambar

5. Controlling dimension: Inches.

Base Plane

44-pin PLCC

Seating Plane

Symbol

Min. Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

Notes:

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

0.020

0.145

0.026

0.016

0.008

0.648

0.590

0.680

0.090

0.150

0.028

0.018

0.010

0.653

0.610

0.690

0.100

0.050

BSC

0.185

0.155

0.032

0.022

0.014

0.658

0.630

0.700

0.110

0.004

0.508

3.683

0.66

0.406

0.203

16.46

14.99

17.27

2.296

3.81

0.711

0.457

0.254

16.59

15.49

17.53

2.54

1.27

4.699

3.937

0.813

0.559

0.356

16.71

16.00

17.78

2.794

0.10

BSC

16.71

16.59

16.46

0.658

0.653

0.648

16.00

15.49

14.99

0.630

0.610

0.590

17.78

17.53

17.27

0.700

0.690

0.680

W78LE812

Publication Release Date: February 1999

- 25 -

Revision A2

Package Dimensions, continued

44-pin PQFP

Seating Plane

See Detail F

Detail F

1. Dimension D & E do not include interlead

flash.

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter
4. General appearance spec. should be based

on final visual inspection spec.

0.254

0.101

0.010

0.004

Notes:

Symbol

Min.

Nom.

Max.

Nom.

Min.

Dimension in inch

Dimension in mm

b
c
D

A
A

0.006

0.152

---

0.002

0.075

0.01

0.081

0.014

0.087

0.018

1.90

0.25

0.05

2.05

0.35

2.20

0.45

0.390

0.025

0.063

0.003

0.394

0.031

0.398

0.037

9.9

0.80

0.65

1.6

10.00

0.8

10.1

0.95

0.398

0.394

0.390

0.530

0.520

0.510

13.45

13.2

12.95

10.1

10.00

9.9

0.08

0.031

0.01

0.02

0.25

0.5

---

0.025

0.036

0.635

0.952

0.530

0.520

0.510

13.45

13.2

12.95

0.051

0.075

1.295

1.905

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798

Note: All data and specifications are subject to change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78LE812-24

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W78LE812-24