W83194BR-903

- II -

Table of Contents-

GENERAL DESCRIPTION ......................................................................................................... 1

PRODUCT FEATURES .............................................................................................................. 1

PIN CONFIGURATION ............................................................................................................... 2

BLOCK DIAGRAM ...................................................................................................................... 2

PIN DESCRIPTION..................................................................................................................... 3

5.1

Crystal I/O.................................................................................................................................3

5.2

CPU, AGP, and PCI Clock Outputs.........................................................................................3

5.3

Fixed Frequency Outputs.........................................................................................................4

5.4

I2C Control Interface ................................................................................................................4

5.5

Power Management Pins.........................................................................................................5

5.6

IREF selects Function ..............................................................................................................5

5.7

Power Pins................................................................................................................................5

FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6

C CONTROL AND STATUS REGISTERS............................................................................... 7

7.1

7.2

7.3

7.4

7.5

BFh) 8

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

Register 14: Control (Default: 0Ah)........................................................................................12

7.16

7.17

7.18

W83194BR-903

Publication Release Date: April 13, 2005

- III - Revision 1.1

7.19

7.20

7.21

7.22

Register21: Fix Mode Control (Default: 00h).........................................................................15

ACCESS INTERFACE .............................................................................................................. 16

8.1

Block Write Protocol...............................................................................................................16

8.2

Block Read Protocol...............................................................................................................16

8.3

Byte Write Protocol.................................................................................................................16

8.4

Byte Read protocol.................................................................................................................16

SPECIFICATIONS .................................................................................................................... 17

9.1

Absolute Maximum Ratings ...................................................................................................17

9.2

General Operating Characteristics ........................................................................................17

9.3

Skew Group Timing Clock .....................................................................................................17

9.4

CPU 0.7V Electrical Characteristics ......................................................................................18

9.5

AGP Electrical Characteristics...............................................................................................18

9.6

PCI Electrical Characteristics.................................................................................................18

9.7

24M, 48M Electrical Characteristics ......................................................................................19

9.8

REF Electrical Characteristics ...............................................................................................19

10.

ORDERING INFORMATION..................................................................................................... 20

11.

HOW TO READ THE TOP MARKING...................................................................................... 20

12.

PACKAGE DRAWING AND DIMENSIONS.............................................................................. 21

13.

REVISION HISTORY ................................................................................................................ 22

W83194BR-903

Publication Release Date: April 13, 2005

- 1 - Revision 1.1

1. GENERAL DESCRIPTION

The W83194BR-903 is a Clock Synthesizer for VIA PT880/PM880 chipset. W83194BR-903 provides
all clocks required for high-speed microprocessor and provides step-less frequency programming and
32 different frequencies of CPU, PCI, and AGP clocks setting, support two 25MHz clock outputs, all
clocks are externally selectable with smooth transitions.

The W83194BR-903 provides I

C serial bus interface to program the registers to enable or disable

each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable
S.S.T. scale to reduce EMI.

The W83194BR-903 also has watchdog timer and reset output pin to support auto-reset when
systems hanging caused by improper frequency setting.

The W83194BR-903 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

2. PRODUCT FEATURES

�

3 0.7V current-mode Differential pairs clock outputs

�

2 2.5V 25MHz clock outputs

�

3 AGP clock outputs

�

10 PCI synchronous clocks

�

1 24_48MHz clock output for super I/O.

�

1 48 MHz clock output for USB.

�

2 14.318MHz REF clock outputs.

�

AGP/PCI clock out supports synchronous and asynchronous mode

�

Smooth frequency switch with selections from 100 to 400MHz

�

Step-less frequency programming

�

C 2-Wire serial interface and support byte read/write and block read/write.

�

-0.5% and +/- 0.25% center type spread spectrum

�

Programmable S.S.T. scale to reduce EMI

�

Programmable registers to enable/stop each output and select modes

�

Programmable clock outputs Slew rate control and Skew control

�

Watch Dog Timer and RESET# output pins

�

48-pin SSOP package

W83194BR-903

- 2 -

3. PIN CONFIGURATION

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FS1* /REF0
FS0

/REF1

VDDREF

XIN

XOUT

GND

FS2

/PCI_F0

FS4

/PCI_F1

PCI_F2

VDDPCI

GND

MODE

/PCI0

PCI1
PCI2
PCI3
PCI4

VDDPCI

GND

PCI_STOP#*/PCI5

CPU_STOP#*/PCI6

FS3

/48MHz

SEL24_48#

/24_48MHz

GND

VDD48

VDDA
GND
IREF
CPUT_ITP
CPUC_ITP
GND
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
GND
25MHz_0
25MHz_1
VDD2.5
VTT_PWRGD/PD#*
SDATA*
SCLK*
RESET#
AGP_0
GND
VDDAGP
AGP_1
AGP_2

#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND

4. BLOCK DIAGRAM

PLL2

XTAL

OSC

PLL1

Spread

Spectrum

M/N/Ratio

ROM

Latch

&POR

Control

Logic

&Config

I2C

Interface

Divider

VCOCLK

48MHz

REF 0:1

CPUT0:1

CPUC0:1

AGP 0:2

PCI_F0:2,PC

I_0:6

RESET#

Rref

XIN

XOUT

VTT_PWRGD

FS(0:4)

PD#*

SEL24_48#

SDATA*

SCLK*

MODE

Divider

24_48MHz

25MHz_0:1

PCI_STOP#*

CPU_STOP#*

CPUT_ITP

CPUC_ITP

W83194BR-903

Publication Release Date: April 13, 2005

- 3 - Revision 1.1

5. PIN DESCRIPTION

BUFFER TYPE SYMBOL

DESCRIPTION

IN Input

tp120k

Latched input at power up, internal 120k pull up.

td120k

Latched input at power up, internal 120k pull down.

OUT Output

OD Open

Drain

I/OD

Bi-directional Pin, Open Drain.

# Active

Low

Internal 120k

pull-up

Internal 120 k

pull-down

5.1 Crystal I/O

PIN

PIN NAME

TYPE

DESCRIPTION

4 XIN IN

Crystal input with internal loading capacitors (18pF) and feedback
resistors.

5 XOUT OUT

Crystal output at 14.318MHz nominally with internal loading
capacitors (18pF).

5.2 CPU, AGP, and PCI Clock Outputs

PIN

PIN NAME

TYPE

DESCRIPTION

42, 39, 41,

CPUT [0:1]

CPUC [0:1]

OUT

Low skew (< 250ps) differential clock outputs for host
frequencies of CPU

45, 44

CPUT_ITP,

CPUC_ITP

OUT

Differential clock outputs for host frequencies of CPU

29, 26, 25

AGP0: 2

OUT

3.3V AGP clock outputs.

PCI_F0

OUT

3.3V PCI free running clock output.

FS2& INtd120k

Latched input for FS2 at initial power up for H/W selecting the
output frequency. This is internal 120K pull down.

PCI_F1

OUT

3.3V PCI free running clock output.

FS4& INtd120k

Latched input for FS4 at initial power up for H/W selecting the
output frequency, This is internal 120K pull down.

PCI0

OUT

3.3V PCI clock output.

MODE& INtd120k

Latched input for pin 19, 20 at initial power up selecting the
0=PCI5, PCI6 clock output, 1=PCI_STOP and CPU _STOP
control pin. This is internal 120K

pull down.

W83194BR-903

- 4 -

CPU, AGP, and PCI Clock Outputs, continued

PIN

PIN NAME

TYPE

DESCRIPTION

PCI_F2

OUT

3.3V PCI free running clock output.

PCI5 OUT

3.3V PCI clock output. Select by pin 12 MODE

power up

initial =0.

PCI_STOP#* IN

tp120k

Active low, Stop all PCI clock output besides the free running
clocks. Select by pin 12 MODE

power up initial =1.

PCI6 OUT

3.3V PCI clock output. Select by pin 12 MODE

power up

initial =0.

CPU_STOP#* IN

tp120k

Active low, Stop all CPU clock outputs. Select by pin 12
MODE

power up initial =1.

13,14,15,16 PCI [1:4]

OUT

Low skew (< 250ps) PCI clock outputs.

5.3 Fixed Frequency Outputs

PIN

PIN NAME

TYPE

DESCRIPTION

REF0 OUT

14.318MHz

output.

FS1* IN

tp120k

Latched input for FS1 at initial power up for H/W selecting the
output frequency. This is internal 120K pull up.

REF1 OUT

14.318MHz

output.

FS0

td120k

Latched input for FS0 at initial power up for H/W selecting the
output frequency. This is internal 120K pull down.

48MHz

OUT

48MHz clock output for USB.

FS3

td120k

Latched input for FS3 at initial power up for H/W selecting the
output frequency. This is internal 120K pull down.

24_48MHz OUT

24MHz or 48MHz(default) clock output, In power on reset
period, it is a hardware-latched pin, and it can be R/W by I2C
control after power on reset period. Select by register 5 bit 7.

SEL24_48#

td120k

Latched input for 24MHz or 48MHz select pin. This is internal
120K pull down default 48MHz. In power on reset period, it is a
hardware-latched pin, and it can be R/W by I2C control after
power on reset period. Select by register 5 bit 7.

36, 35

25MHz_[0:1]

OUT

25MHz 2.5V push pull clock output.

5.4 I2C Control Interface

PIN

PIN NAME

TYPE

DESCRIPTION

32 SDATA* I/OD

Serial data of I

C 2-wire control interface with internal 120K pull-

up resistor.

31 SCLK*

tp120k

Serial clock of I

C 2-wire control interface with internal 120K

pull-up resistor.

W83194BR-903

Publication Release Date: April 13, 2005

- 5 - Revision 1.1

5.5 Power Management Pins

PIN

PIN NAME

TYPE

DESCRIPTION

VTT_PWRGD

Power good input signal is power on trapping with HIGH active.
This 3.3V input is level sensitive strobe used to determine FS
[4:0]. This pin is HIGH active.

PD#* IN

tp120k

Power Down Function. This is power down pin, low active (PD#).
Internal 120K pull up

46 IREF OUT

Deciding the reference current for the CPUCLK pairs. The pin
was connected to the precision resistor tied to ground to decide
the appropriate current.

30 RESET# OD

System reset signal when the watchdog is time out. This pin will
generate 250ms low phase when the watchdog timer is timeout.

5.6 IREF selects Function

BOARD TARGET

TRACE/TERM Z

REFERENCE R,

IREF = ADD/(3*RR)

OUTPUT

CURRENT

VOH @ Z

Rr = 221 1%

IREF = 5.00mA

Ioh = 4*IREF

1.0V @ 50

Rr = 475 1%

IREF = 2.32mA

Ioh = 6*IREF

0.7V @ 50

5.7 Power Pins

PIN

PIN NAME

TYPE

DESCRIPTION

VDDREF

PWR

3.3V power supply for REF.

10,17

VDDPCI

PWR

3.3V power supply for PCI.

VDDAGP

PWR

3.3V power supply for AGP.

VDDCPU

PWR

3.3V power supply for CPU.

VDD48

PWR

3.3 power supply for 48MHz.

VDD2.5

PWR

2.5V power supply for 25MHz.

VDDA

PWR

3.3V power for Analog power

6, 11, 18, 23,

28, 37, 43, 47

GND PWR

Ground

W83194BR-903

- 6 -

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE

This frequency table is used at power on latched FS [4:0] value or software programming at SSEL
[4:0] (Register 0 bit 7 ~ 3).

FS4 FS3 FS2 FS1 FS0 CPU

(MHZ)

3V66

(MHZ)

PCI

(MHZ)

0 0 0 0 0 100.00

66.67

33.33

0 0 0 0 1 200.01

66.67

33.33

0 0 0 1 0 133.34

66.67

33.33

0 0 1 0 0 200.01

66.67

33.33

0 0 1 0 1 400.01

66.67

33.33

0 0 1 1 0 266.68

66.67

33.33

0 1 0 0 0

101.1

67.34

33.67

0 1 0 0 1

202.2

67.34

33.67

0 1 0 1 0 134.68

67.34

33.67

1 0 0 0 0 100.00

66.67

33.33

1 0 0 0 1 200.01

66.67

33.33

1 0 0 1 0 133.34

66.67

33.33

1 0 1 0 0 200.01

66.67

33.33

1 0 1 0 1 400.01

66.67

33.33

1 0 1 1 0 266.68

66.67

33.33

1 1 0 0 0 105.04

70.02

35.01

1 1 0 0 1 210.07

70.02

35.01

1 1 0 1 0 140.05

70.02

35.01

W83194BR-903

Publication Release Date: April 13, 2005

- 7 - Revision 1.1

7. I

C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select (Default = 10h)

BIT

NAME

PWD

DESCRIPTION

7 SSEL

[4] 0

6 SSEL

[3] 0

5 SSEL

[2] 0

4 SSEL

[1] 1

3 SSEL

[0] 0

Frequency selection by software via I

2 EN_SSEL 0

Enable software program FS [4:0].
0 = Select frequency by hardware.
1= Select frequency by software I

C - Bit 7~ 3.

1 EN_SPSP

Enable Spread Spectrum in the frequency table.
0 = Normal
1 = Spread Spectrum Enabled

0 EN_SAFE_FREQ

Enable reload safe frequency when the watchdog is timeout.
0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 5 bit 4~0.

7.2 Register 1: CPU Clock (1 = Enable, 0 = Stopped) (Default: E2h)

BIT

PIN NO

PWD

DESCRIPTION

45, 44

CPUT_IPT/CPUC_IPT output control.

42, 41

CPUT1 / C1 output control.

39, 38

CPUT0 / C0 output control.

Power on latched value of FS4 pin. Default: 0 (Read only)

Power on latched value of FS3 pin. Default: 0 (Read only)

Power on latched value of FS2 pin. Default: 0 (Read only)

Power on latched value of FS1 pin. Default: 1 (Read only)

Power on latched value of FS0 pin. Default: 0 (Read only)

W83194BR-903

- 8 -

7.3 Register 2: PCI Clock (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

PIN NO

PWD

DESCRIPTION

PCI_F2 output control.

PCI_F1 output control.

PCI_F0 output control.

4 Reserve 1 Reserved

3 20 1

PCI6

output

control.

2 19 1

PCI5

output

control.

1 16 1

PCI4

output

control.

0 15 1

PCI3

output

control.

7.4 Register 3: PCI, AGP Clock (1 = Enable, 0 = Stopped) (Default: FFh)

BIT

PIN NO

PWD

DESCRIPTION

7 14 1

PCI2

output

control.

6 13 1

PCI1

output

control.

5 12 1

PCI0

output

control.

4 - 1

Don't

modify

AGP_2 output control.

AGP_1 output control.

AGP_0 output control.

0 - 1

Don't

modify

7.5 Register 4: 24_48MHz, 48MHz, REF, 25MHz Control (1 = Enable, 0 = Stopped)

(Default: BFh)

BIT

PIN NO

PWD

DESCRIPTION

24_48MHz output control.

6 - 0

Reserved

48MHz output control.

4 - 1

Reserved

3 2 1

REF1

output

control.

2 1 1

REF0

output

control.

25MHz_1 output control.

25MHz_0 output control.

W83194BR-903

Publication Release Date: April 13, 2005

- 9 - Revision 1.1

7.6 Register 5: Watchdog Control (Default: 02h)

BIT

NAME

PWD

DESCRIPTION

7 SEL24_48 X

24 / 48 MHz output selection, 1: 24 MHz.0: 48 MHz.

(Default)

Default value follow hardware trapping data on SEL24_48# pin.

6 EN_WD 0

Program this bit =>
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.

5 WD_TIMEOUT

Read Back only, Timeout Flag, This bit is Read Only.
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.

4 SAF_FREQ

[4]

3 SAF_FREQ

[3]

2 SAF_FREQ

[2]

1 SAF_FREQ

[1]

0 SAF_FREQ

[0]

These bits will be reloaded in Reg-0 to select frequency table. As the
watchdog is timeout and EN_SAFE_FREQ=1.

7.7 Register 6: Reserved (Default: 50h) (Read Only)

BIT

NAME

PWD

DESCRIPTION

7 Reserved 0

6 Reserved 1

Reserved

5 Reserved 0

4 Reserved 1

Reserved

3 Reserved 0

2 Reserved 0

Reserved

1 Reserved 0

0 Reserved 0

Reserved

W83194BR-903

- 10 -

7.8 Register 7: Winbond Chip ID (Default: 70h) (Read Only)

BIT

NAME

PWD

DESCRIPTION

CHPI_ID [7]

Winbond Chip ID. W83194BR-903 (SA5870)

6 CHPI_ID

[6] 1 Winbond

Chip

ID.

5 CHPI_ID

[5] 1 Winbond

Chip

ID.

4 CHPI_ID

[4] 1 Winbond

Chip

ID.

CHPI_ID [3]

Winbond Chip ID.

2 CHPI_ID

[2] 0 Winbond

Chip

ID.

1 CHPI_ID

[1] 0 Winbond

Chip

ID.

0 CHPI_ID

[0] 0 Winbond

Chip

ID.

7.9 Register 8: M/N Program (Default: 90h)

BIT

NAME

PWD

DESCRIPTION

N_DIV [8]

Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.

6 M_DIV

[6] 0

5 M_DIV

[5] 0

4 M_DIV

[4] 1

3 M_DIV

[3] 0

2 M_DIV

[2] 0

1 M_DIV

[1] 0

0 M_DIV

[0] 0

Programmable M divisor value.

7.10 Register 9: M/N Program (Default: 7Ah)

BIT

NAME

PWD

DESCRIPTION

7 N_DIV

[7] 0

6 N_DIV

[6] 1

5 N_DIV

[5] 1

4 N_DIV

[4] 1

3 N_DIV

[3] 1

2 N_DIV

[2] 0

1 N_DIV

[1] 1

0 N_DIV

[0] 0

Programmable N divisor value bit 7 ~0. The bit 8 is defined in
Register 8.

W83194BR-903

Publication Release Date: April 13, 2005

- 11 - Revision 1.1

7.11 Register 10: M/N Program (Default: BBh)

BIT

NAME

PWD

DESCRIPTION

N_DIV [9]

Programmable N divisor bit 9.

6 N3<6> 0

5 N3<5> 1

4 N3<4> 1

3 N3<3> 1

2 N3<2> 0

1 N3<1> 1

0 N3<0> 1

Programmable N3 divisor bit 6 ~0 for programmable 25M clocks.
M3 = 10000 (Fix)
Frequency range: 21.7M ~ 28.8M
Resolution: 56K

7.12 Register 11: Spread Spectrum Programming (Default: 0Bh)

BIT

NAME

PWD

DESCRIPTION

7 SP_UP

[3] 0

6 SP_UP

[2] 0

5 SP_UP

[1] 0

4 SP_UP

[0] 0

Spread Spectrum Up Counter bit 3 ~ bit 0.

3 SP_DOWN

[3] 1

2 SP_DOWN

[2] 0

1 SP_DOWN

[1] 1

0 SP_DOWN

[0] 1

Spread Spectrum Down Counter bit 3 ~ bit 0
2's complement representation.
Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

7.13 Register 12: Divisor and Step-less Enable Control (Default: FBh)

BIT

NAME

PWD

DESCRIPTION

7 Reserved 1

Reserved

6 DS9 1

5 DS5 1

Define the AGP divider ratio
Table-2 integrate the all divider configuration

4 Reserved 1

3 Reserved 1

Reserved

2 DS2 0

1 DS1 1

0 DS0 1

Define the CPU divider ratio
Refer to Table-2

W83194BR-903

- 12 -

Table-2 CPU, AGP, PCI divider ratio selection Table

AGP CPU

Bit5 Bit1,

LSB
MSB

0 1 00

0 Div6 Div7 Div2 Div3 Div4 Div6

Bit2/

Bit9

1 Div10

Div12 Div8 Div8 Div8 Div8

7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh)

BIT

NAME

PWD

DESCRIPTION

7 EN_MN_PROG

0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
VCO

=14.318MHz*(N+4)/

Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0
- bit 0).

6 Reserved 0

Reserved

5 Reserved 0

Reserved

4 Reserved 0

Reserved

3 IVAL<3> 1
2 IVAL<2> 1
1 IVAL<1> 1
0 IVAL<0> 1

Charge pump current selection

7.15 Register 14: Control (Default: 0Ah)

BIT

NAME

PWD

DESCRIPTION

7 CPUT_DRI 0

CPUT output state in during POWER DOWN or Stop mode assertion.
1: Driven (2*Iref),
0: Tristate (Floating)
CPUC always tri-state (floating) in power down Assertion.

6 Reserved 0

Reserved

5 SPCNT

[5] 0

4 SPCNT

[4] 0

3 SPCNT

[3] 1

2 SPCNT

[2] 0

1 SPCNT

[1] 1

0 SPCNT

[0] 0

Spread Spectrum Programmable time, the resolution is 280ns. Default
period is 11.8us

W83194BR-903

Publication Release Date: April 13, 2005

- 13 - Revision 1.1

7.16 Register 15: SST & Skew Control (Default: 2Ch)

BIT

NAME

PWD

DESCRIPTION

INV_CPU

Invert the CPU phase, 0: Default, 1: Inverse

6 Reserved 0

Reserved

5 SPSP_TYPE 1

Spread spectrum implementation method
1: Pendulum type, 0: Original

4 SPSP1 0

3 SPSP0 1

Spread Spectrum type select.
00: Down 1%
01: Down 0.5%
10: Center +/- 0.5%
11: Center +/- 0.25%

2 ASKEW

[2] 1

1 ASKEW

[1] 0

0 ASKEW

[0] 0

CPU to AGP skew control, Skew resolution is 340ps
Expand the skew direction is same as
CPU_AGP_SKEW [2:0] setting

7.17 Register 16: Skew Control (Default: 24h)

BIT

NAME

PWD

DESCRIPTION

INV_AGP

Invert the AGP phase, 0: Default, 1: Inverse

INV_PCI

Invert the PCI phase, 0: Default, 1: Inverse

5 Reserved 1
4 Reserved 0
3 Reserved 0

Reserved

2 PSKEW

[2] 1

1 PSKEW

[1] 0

0 PSKEW

[0] 0

CPU to PCI skew control, Skew resolution is 340ps
Expand the skew direction is same as
CPU_PCI_SKEW [2:0] setting

7.18 Register 17: Slew rate Control (Default: 00h)

BIT

NAME

PWD

DESCRIPTION

7 PCI_F2_S2 0
6 PCI_F2_S1 0

PCI_F2 slew rate control
11: Strong, 00: Weak, 10/01: Normal

5 PCI_F0_S2 0
4 PCI_F0_S1 0

PCI_F1 / PCI_F0 slew rate control
11: Strong, 00: Weak, 10/01: Normal

3 AGP_2_S2 0
2 AGP_2_S1 0

AGP2 slew rate control
11: Strong, 00: Weak, 10/01: Normal

1 AGP_10_S2 0
0 AGP_10_S1 0

AGP_1 /AGP_0 slew rate control
11: Strong, 00: Weak, 10/01: Normal

W83194BR-903

- 14 -

7.19 Register 18: Slew rate Control (Default: 00h)

BIT

NAME

PWD

DESCRIPTION

7 PCI_65_S2 0

6 PCI_65_S1 0

PCI6, 5 slew rate control
11: Strong, 00: Weak, 10/01: Normal

5 PCI_42_S2 0

4 PCI_42_S1 0

PCI4, 3,2 slew rate control
11: Strong, 00: Weak, 10/01: Normal

3 PCI_10_S2 0

2 PCI_10_S1 0

PCI1, 0 slew rate control
11: Strong, 00: Weak, 10/01: Normal

1 REF_S2 0

0 REF_S1 0

REF0, 1 slew rate control
11: Strong, 00: Weak, 10/01: Normal

7.20 Register 19: Slew rate Control (Default: D2h)

BIT

NAME

PWD

DESCRIPTION

7 CPU1STOP_EN

Stop CPU1 clocks, 1: Enable stop feature, 0: Disable

6 CPU0STOP_EN

Stop CPU0 clocks, 1: Enable stop feature, 0: Disable

5 25MHz_S2 0

4 25MHz_S1 1

25MHz_1, 0 slew rate control
11: Strong, 00: Weak, 10/01: Normal

3 INV_48MHz 0

Invert the 48MHz phase, 0: In phase with 24_48MHz
1: 180 degrees out of phase

2 48MHz_S2 0

1 48MHz_S1 1

48MHz/24_48MHz slew rate control
11: Strong, 00: Weak, 10/01: Normal

0 MODE X

Pin 19,20

Mode selection

1: PCI_STOP, CPU_STOP Control pin
0: PCI5, PCI6 (Default)
Default value follow hardware trapping data on MODE

/PCI0 pin.

7.21 Register 20: Watch dog timer (Default: 08h)

BIT

NAME

PWD

DESCRIPTION

7 SRCF1 0

SRC frequency select, 00/01: 25MHz(Default), 10: 100mhZ, 11:
200MHz

6 WD_TIME

[6] 0

5 WD_TIME

[5] 0

4 WD_TIME

[4] 0

Setting the down count depth. One bit resolution represents 250ms.
Default time depth is 8*250ms = 2.0 second. If the watchdog timer is
counting, this register will return present down count value

W83194BR-903

Publication Release Date: April 13, 2005

- 15 - Revision 1.1

BIT

NAME

PWD

DESCRIPTION

3 WD_TIME

[3] 1

2 WD_TIME

[2] 0

1 WD_TIME

[1] 0

0 WD_TIME

[0] 0

7.22 Register21: Fix Mode Control (Default: 00h)

BIT

NAME

PWD

DESCRIPTION

Tri-state

Tri-state all output if set 1

6 Reserved 0

Don't

modify

Reserved

Don't modify it

4 FIX_SEL 0

AGP output frequency select mode
0: Output frequency according to frequency selection table
1: Output frequency according to FIX frequency Reg21 bit 0~2

SRCF0

SRC frequency select

2 ASEL_2 0

1 ASEL_1 0

0 ASEL_0 0

Asynchronous AGP/PCI frequency table selection ASEL_<2:0>
001: 66 / 33M 010: 75.43 / 37.7M
011: 88 / 44M 100: 88 / 44M
101: 66 / 33M 110: 75.43 / 33M
111: 88 / 33M 000: Clock from PLL1

W83194BR-903

Publication Release Date: April 13, 2005

- 17 - Revision 1.1

9. SPECIFICATIONS

9.1 Absolute Maximum

Ratings

Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).

PARAMETER

RATING

Absolute 3.3V Core Supply Voltage

-0.5V to +4.6V

Absolute 3.3V I/O Supple Voltage

-0.5 V to +4.6 V

Operating 3.3V Core Supply Voltage

3.135V to 3.465V

Operating 3.3V I/O Supple Voltage

3.135V to 3.465V

Storage Temperature

-65

�

C to +150

�

Ambient Temperature

-55

�

C to +125

�

Operating Temperature

�

C to +70

�

Input ESD protection (Human body model)

2000V

9.2 General Operating Characteristics

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Cl=10pF

PARAMETER

SYM.

MIN.

MAX.

UNITS

TEST CONDITIONS

Input Low Voltage

0.8 V

Input High Voltage

2.0 V

Output Low Voltage

0.4 V

All outputs using 3.3V power

Output High Voltage

2.4 V

All outputs using 3.3V power

Operating Supply Current

350 mA

CPU = 100 to 400 MHz
PCI = 33.3 MHz with load

Input pin capacitance

Cin

Output pin capacitance

Cout

Input pin inductance

Lin

9.3 Skew Group Timing Clock

VDDA=VDDAGP=VDDCPU=VDDREF=VDDPCI = 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Cl=10pF

PARAMETER

MIN.

TYP.

MAX.

UNITS

TEST CONDITIONS

AGP to PCI Skew

1.5

2.6

3.5

Measured at 1.5V

CPU to CPU Skew

200

Crossing

point

AGP to AGP Skew

250

Measured at 1.5V

PCI to PCI Skew

500

Measured at 1.5V

48MHz to 48MHz Skew

1000

Measured at 1.5V

REF to REF Skew

500

Measured at 1.5V

W83194BR-903

- 18 -

9.4 CPU 0.7V Electrical Characteristics

VDDA=VDDCPU= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=475, IREF=2.32mA, Ioh=6*IREF

PARAMETER

MIN.

MAX.

UNITS

TEST CONDITIONS

Rise Time

175

700

100 to 200 MHz

Fall Time

175

700

100 to 200MHz

Absolute crossing point Voltages

250

550

100 to 200MHz

Cycle to Cycle jitter

150

100 to 200MHz

Duty Cycle

100 to 200MHz

9.5 AGP

Electrical Characteristics

VDDAGP= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl=10pF,

PARAMETER

MIN.

MAX.

UNITS

TEST CONDITIONS

Rise Time

500

2000

Measure from 0.4V to 2.4V

Fall Time

500

2000

Measure from 2.4V to 0.4V

Cycle to Cycle jitter

250

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min

-33

Vout=1.0V

Pull-Up Current Max

-33

Vout=3.135V

Pull-Down Current Min

Vout=1.95V

Pull-Down Current Max

Vout=0.4V

9.6 PCI Electrical Characteristics

VDDPCI= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl=10pF,

PARAMETER

MIN.

MAX.

UNITS

TEST CONDITIONS

Rise Time

500

2000

Measure from 0.4V to 2.4V

Fall Time

500

2000

Measure from 2.4V to 0.4V

Cycle to Cycle jitter

250

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min

-33

Vout=1.0V

Pull-Up Current Max

-33

Vout=3.135V

Pull-Down Current Min

Vout=1.95V

Pull-Down Current Max

Vout=0.4V

W83194BR-903

Publication Release Date: April 13, 2005

- 19 - Revision 1.1

9.7 24M, 48M

Electrical Characteristics

VDD48= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl=10pF,

PARAMETER

MIN.

MAX.

UNITS

TEST CONDITIONS

Rise Time

500

2000

Measure from 0.4V to 2.4V

Fall Time

500

2000

Measure from 2.4V to 0.4V

Long term jitter

500

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min

-33

Vout=1.0V

Pull-Up Current Max

-33

Vout=3.135V

Pull-Down Current Min

Vout=1.95V

Pull-Down Current Max

Vout=0.4V

9.8 REF Electrical Characteristics

VDDREF= 3.3V

�

5 %, TA = 0

�

C to +70

�

C, Test load, Cl=10pF,

PARAMETER

MIN.

MAX.

UNITS

TEST CONDITIONS

Rise Time

1000

4000

Measure from 0.4V to 2.4V

Fall Time

1000

4000

Measure from 2.4V to 0.4V

Cycle to Cycle jitter

1000

Measure 1.5V point

Duty Cycle

45 55 %

Pull-Up Current Min

-33

Vout=1.0V

Pull-Up Current Max

-33

Vout=3.135V

Pull-Down Current Min

Vout=1.95V

Pull-Down Current Max

Vout=0.4V

W83194BR-903

- 22 -

13. REVISION HISTORY

VERSION DATE

PAGE

DESCRIPTION

n.a.

All of the versions before 0.50 are for internal
use.

0.5

09/07/03

n.a.

First published preliminary version.

0.6 10/28/03

6 Modify frequency table

0.7

12/18/03

7, 9, 19

Correction IC version, correction some
description and default value

1.0 12/23/04

Update

Web

1.1 4/13/2005

Add

disclaimer

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
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TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168
FAX: 886-2-8751-3579

Winbond Electronics Corporation America

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FAX: 1-408-5441798

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FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

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200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

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Taiwan, R.O.C.

Электронный компонент: W83194BR-903