W83194R-17/-17A

100MHZ AGP CLOCK FOR SIS CHIPSET

Publication Release Date: Sep. 1998

- 1 - Revision 0.20

1.0 GENERAL DESCRIPTION

The W83194R-17/-17A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel PentiumII, PentiumPro , AMD or Cyrix. Eight different
frequency of CPU, AGP and PCI clocks are externally selectable with smooth transitions. The
W83194R-17/-17A provides AGP clocks especially for clone chipset. The highest CPU frequency
provided by the W83194R-17 is up to 100MHz, but the one of W83194R-17A is up to 133MHz.

The W83193R-17/-17A provides I

C serial bus interface to program the registers to enable or disable

each clock outputs and choose the 0.5% or 1.5% center type spread spectrum to reduce EMI.

The W83194R-17/-17A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads
as maintaining 50

5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz

provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

Supports Pentium

, Pentium

Pro, Pentium

II, AMD and Cyrix CPUs with I

4 CPU clocks

12 SDRAM clocks for 3 DIMMs

Two AGP clocks

6 PCI synchronous clocks.

Optional single or mixed supply:

(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd =Vddq2 = Vddq3 = 3.3V, Vddq2b = 2.5V)

Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)

Smooth frequency switch with selections from 60 MHz to 133 MHz CPU

C 2-Wire serial interface and I

C read back

¡Ó

0.5% or

¡Ó

1.5% center type spread spectrum function to reduce EMI

Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

MODE pin for power Management

48 MHz for USB

24 MHz for super I/O

48-pin SSOP package

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 2 - Revision 0.20

3.0 BLOCK DIAGRAM

PLL2

XTAL
OSC

Spread
Spectrum

PLL1

LATCH

POR

STOP

¡Ò

Control

Logic

Config.

Reg.

STOP

PCI
clock
Divder

12
3

48MHz

24MHz

REF(0:1)

AGP(0:1)

CPUCLK(0:3)

SDRAM(0:11)

PCICLK(0:4)

PCICLK_F

FS(0:2)

MODE

CPU_STOP#

PCI_STOP#

SDATA

SCLK

CPU3.3#_2.5

4.0 PIN CONFIGURATION

48
47
46
45

43
42
41
40
39
38

37
36
35
34

33
32
31
30
29
28
27
26
25

1
2
3
4

6
7

9
10
11
12

13
14
15

17
18
19
20
21
22
23
24

Vdd

REF0/CPU3.3#_2.5

Vss

Xin

Xout

Vddq3

PCICLK_F/*FS1

PCICLK0/*FS2

Vss

PCICLK1

PCICLK2
PCICLK3
PCICLK4

Vddq3

AGP0

Vss

CPU_STOP#/SDRAM11

PCI_STOP#/SDRAM10

Vddq3

SDRAM 9
SDRAM 8

Vss

SDATA
SDCLK

Vddq2

AGP1

REF1

Vss

CPUCLK0

CPUCLK1
Vddq2b

CPUCLK2
CPUCLK3

Vss
SDRAM 0

SDRAM 1

SDRAM 2

Vddq3

SDRAM 3
Vss
SDRAM 4
SDRAM 5

SDRAM 6
SDRAM 7
Vss

Vddq3

48MHz/*FS0
24MHz/*MODE

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 3 - Revision 0.20

5.0 PIN DESCRIPTION

IN - Input

OUT - Output

I/O - Bi-directional Pin

# - Active Low

* - Internal 250k

pull-up

5.1 Crystal I/O

SYMBOL

PIN

I/O

FUNCTION

Xin

Crystal input with internal loading capacitors and
feedback resistors.

Xout

OUT

Crystal output at 14.318MHz nominally.

5.2 CPU, SDRAM, PCI Clock Outputs

SYMBOL

PIN

I/O

FUNCTION

CPUCLK [ 0:3 ]

40,41,43,44

OUT

Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Vddq2b is the supply voltage for these outputs.

AGP[ 0:1]

15,47

OUT

Accelerate Graphic Port clock outputs

SDRAM11/

CPU_STOP#

I/O

If MODE =1 (default), then this pin is a SDRAM
Clock buffered output. If MODE = 0 , then this pin is
CPU_STOP# input used in power management
mode for synchronously stopping the all CPU clocks.

SDRAM10/
PCI_STOP#

I/O

If MODE = 1 (default), then this pin is a SDRAM
clock output. If MODE = 0 , then this pin is
PCI_STOP # and used in power management mode
for synchronously stopping the all PCI clocks.

SDRAM [ 0:9]

20,21,28,29,31

,32,34,

35,37,38

SDRAM clock outputs which have the same
frequency as CPU clocks.

PCICLK_F/ *FS1

I/O

Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

Free running PCI clock during normal operation.

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 4 - Revision 0.20

5.2 CPU, SDRAM, PCI Clock Outputs, continued

SYMBOL

PIN

I/O

FUNCTION

PCICLK 0 / *FS2

I/O

Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.

PCI clock during normal operation.

PCICLK [ 1:4 ]

10,11,12,13

OUT

Low skew (< 250ps) PCI clock outputs.

5.3 I

C Control Interface

SYMBOL

PIN

I/O

FUNCTION

SDATA

I/O

Serial data of I

C 2-wire control interface

SDCLK

Serial clock of I

C 2-wire control interface

5.4 Fixed Frequency Outputs

SYMBOL

PIN

I/O

FUNCTION

REF0 / CPU3.3#_2.5

I/O

Internal 250k

pull-up.

Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.

Latched high - Vddq2b = 2.5V

Latched low - Vddq2b = 3.3V

REF1

I/O

Internal 250k

pull-up.

24MHz / *MODE

I/O

Internal 250k

pull-up.

Latched input for MODE at initial power up. 24MHz
output for super I/O during normal operation.

48MHz / *FS0

I/O

Internal 250k

pull-up.

Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 5 - Revision 0.20

5.5 Power Pins

SYMBOL

PIN

FUNCTION

Vdd

Power supply for REF0 crystal and core logic.

Vddq2

Power supply for AGP1, REF1either 2.5V or 3.3V.

Vddq2b

Power supply for CPUCLK[0:3], either 2.5V or 3.3V

Vddq3

6,14,19, 30, 36

Power supply for SDRAM, PCICLK and 48/24MHz
outputs.

Vss

3,9,16,22,27,

33,39,45

Circuit Ground.

6.0 FREQUENCY SELECTION

6.1 W83194R-17 FREQUECY TABLE

FS2

FS1

FS0

CPU,SDRAM

(MHz)

PCI (MHz)

AGP (MHz)

REF (MHz)

14.318

66.8

33.4

66.8

14.318

68.5

34.25

68.5

14.318

37.5

14.318

83.3

33.3

66.6

14.318

100

33.3

66.6

14.318

6.2 W83194R-17A FREQUECY TABLE

FS2

FS1

FS0

CPU,SDRAM

(MHz)

PCI (MHz)

AGP (MHz)

REF (MHz)

112

37.3

74.7

14.318

66.8

33.4

66.8

14.318

124

14.318

37.5

14.318

133.3

33.3

66.6

14.318

83.3

33.3

66.6

14.318

95.25

31.75

63.5

14.318

100.2

33.4

66.8

14.318

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 7 - Revision 0.20

8.0 FUNTION DESCRIPTION

8.1 POWER MANAGEMENT FUNCTIONS

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO

to stabilize prior to enabling clock outputs to

assure correct pulse widths. When MODE=0, pins 18 and 17 are inputs (PCI_STOP#),
(CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be
enabled as both the 2-wire serial control interface and one of these pins indicate that it should be
enabled.

The W83194R-17/-17A may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.

CPU_STOP#

PCI_STOP#

CPU & AGP

PCI

OTHER CLKs

XTAL & VCOs

LOW

RUNNING

LOW

RUNNING

LOW

RUNNING

8.2 2-WIRE I

C CONTROL INTERFACE

The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-17/-17A initializes with default register settings, and then it

optional to use the 2-wire

control interface.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command
code checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I

C registers after the string of data. The sequence order is as follows:

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 8 - Revision 0.20

Bytes sequence order for I

C controller :

Clock Address

A(6:0) & R/W

Ack

8 bits dummy

Command code

Ack

8 bits dummy

Byte count

Ack

Byte0,1,2...

until Stop

Set R/W to 1 when read back the data sequence is as follows :

Clock Address

A(6:0) & R/W

Ack

Byte 0

Ack

Byte2, 3, 4...

until Stop

Byte 1

8.3 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.

8.3.1 Register 0: CPU Frequency Select Register

Bit

@PowerUp

Pin

Description

0 =

¡Ó

1.5% Spread Spectrum Modulation

1 =

¡Ó

0.5% Spread Spectrum Modulation

SSEL2 ( Frequency table selection by software via I

SSEL1 ( Frequency table selection by software via I

SSEL0 ( Frequency table selection by software via I

0 = Selection by hardware

1 = Selection by software I

C - Bit 6:4

0 = Spread Spectrum center spread type

1 = Spread Spectrum down spread type

0 = Normal

1 = Spread Spectrum enabled

0 = Running

1 = Tristate all outputs

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 9 - Revision 0.20

W83194R-17 Frequency table selection by software via I

SSEL2

SSEL1

SSEL0

CPU,SDRAM

(MHz)

PCI (MHz) AGP (MHz)

REF (MHz)

14.318

66.8

33.4

66.8

14.318

68.5

34.25

68.5

14.318

37.5

14.318

83.3

33.3

66.6

14.318

100

33.3

66.6

14.318

W83194R-17A Frequency table selection by software via I

SSEL2

SSEL1

SSEL0

CPU,SDRAM

(MHz)

PCI (MHz)

AGP (MHz)

REF (MHz)

112

37.3

74.7

14.318

66.8

33.4

66.8

14.318

124

14.318

37.5

14.318

133.3

33.3

66.6

14.318

83.3

33.3

66.6

14.318

95.25

31.75

63.4

14.318

100.2

33.4

66.8

14.318

FUNCTION TABLE

Function

Outputs

Description

CPU

PCI

SDRAM

REF

IOAPIC

Tri-State

Hi-Z

Normal

see table

CPU

14.318

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 10 - Revision 0.20

8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

Reserved

CPUCLK3 (Active / Inactive)

CPUCLK2 (Active / Inactive)

CPUCLK1 (Active / Inactive)

CPUCLK0 (Active / Inactive)

8.3.3 Register 2: PCI Clock Register(1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

Reserved

PCICLK_F (Active / Inactive)

AGP0 (Active / Inactive)

PCICLK4 (Active / Inactive)

PCICLK3 (Active / Inactive)

PCICLK2 (Active / Inactive)

PCICLk1 (Active / Inactive)

PCICLK0 (Active / Inactive)

8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

SDRAM7 (Active / Inactive)

SDRAM6 (Active / Inactive)

SDRAM5 (Active / Inactive)

SDRAM4 (Active / Inactive)

SDRAM3 (Active / Inactive)

SDRAM2 (Active / Inactive)

SDRAM1 (Active / Inactive)

SDRAM0 (Active / Inactive)

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 11 - Revision 0.20

8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

Reserved

SDRAM11 (Active / Inactive)

SDRAM10 (Active / Inactive)

SDRAM9 (Active / Inactive)

SDRAM8 (Active / Inactive)

8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

Reserved

AGP1 (Active / Inactive)

Reserved

REF1 (Active / Inactive)

REF0 (Active / Inactive)

8.3.7 Register 6: Reserved Register

Bit

@PowerUp

Pin

Description

Reserved

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 12 - Revision 0.20

9.0 SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Symbol

Parameter

Rating

Vdd , V

Voltage on any pin with respect to GND

- 0.5 V to + 7.0 V

STG

Storage Temperature

- 65

C to + 150

Ambient Temperature

- 55

C to + 125

Operating Temperature

C to + 70

9.2 AC CHARACTERISTICS

Vdd = Vddq2= Vddq3 = 3.3V

5 %, Vddq2b = 2.375V~2.9V , T

= 0

C to +70

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Output Duty Cycle

Measured at 1.5V

CPU/SDRAM to PCI Offset

OFF

15 pF Load Measured at 1.5V

Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)

SKEW

250

15 pF Load Measured at 1.5V

CPU/SDRAM

Cycle to Cycle Jitter

CCJ

¡Ó

250

CPU/SDRAM

Absolute Jitter

500

Jitter Spectrum 20 dB

Bandwidth from Center

500

KHz

Output Rise (0.4V ~ 2.0V)

& Fall (2.0V ~0.4V) Time

TLH

THL

0.4

1.6

15 pF Load on CPU and PCI
outputs

Overshoot/Undershoot

Beyond Power Rails

over

0.7

1.5

at source of 8 inch PCB

run to 15 pF load

Ring Back Exclusion

RBE

0.7

2.1

Ring Back must not enter this
range.

9.3 DC CHARACTERISTICS

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 13 - Revision 0.20

Vdd = Vddq2= Vddq3 = 3.3V

5 %, Vddq2b = 2.375V~2.9V , T

= 0

C to +70

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Input Low Voltage

0.8

Input High Voltage

2.0

Input Low Current

-66

Input High Current

Output Low Voltage

= 4 mA

0.4

All outputs

Output High Voltage

= 4mA

2.4

All outputs using 3.3V power

Tri-State leakage Current

Ioz

Dynamic Supply Current

for Vdd + Vddq3

dd3

CPU = 66.6 MHz

PCI = 33.3 Mhz with load

Dynamic Supply Current

for Vddq2 + Vddq2b

dd2

Same as above

CPU Stop Current

for Vdd + Vddq3

CPUS3

Same as above

CPU Stop Current

for Vddq2 + Vddq2b

CPUS2

Same as above

PCI Stop Current

for Vdd + Vddq3

PD3

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 14 - Revision 0.20

9.4 BUFFER CHARACTERISTICS

9.4.1 TYPE 1 BUFFER FOR CPU (0:3)

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

OH(min)

-27

Vout = 1.0 V

Pull-Up Current Max

OH(max)

-27

Vout = 2.0V

Pull-Down Current Min

OL(min)

Vout = 1.2 V

Pull-Down Current Max

OL(max)

Vout = 0.3 V

Rise/Fall Time Min
Between 0.4 V and 2.0 V

RF(min)

0.4

10 pF Load

Rise/Fall Time Max
Between 0.4 V and 2.0 V

RF(max)

1.6

20 pF Load

9.4.2 TYPE 2 BUFFER FOR IOAPIC

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

OH(min)

Vout = 1.4 V

Pull-Up Current Max

OH(max)

-29

Vout = 2.7V

Pull-Down Current Min

OL(min)

Vout = 1.0 V

Pull-Down Current Max

OL(max)

Vout = 0.2 V

Rise/Fall Time Min
Between 0.7 V and 1.7 V

RF(min)

0.4

10 pF Load

Rise/Fall Time Max
Between 0.7 V and 1.7 V

RF(max)

1.8

20 pF Load

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 15 - Revision 0.20

9.4.3 TYPE 3 BUFFER FOR REF(0:1), 24MHZ, 48MHZ

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

OH(min)

-29

Vout = 1.0 V

Pull-Up Current Max

OH(max)

-23

Vout = 3.135V

Pull-Down Current Min

OL(min)

Vout = 1.95 V

Pull-Down Current Max

OL(max)

Vout = 0.4 V

Rise/Fall Time Min
Between 0.8 V and 2.0 V

RF(min)

1.0

10 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V

RF(max)

4.0

20 pF Load

9.4.4 TYPE 4 BUFFER FOR REF0 and SDRAM(0:11)

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

OH(min)

Vout = 1.65V

Pull-Up Current Max

OH(max)

-46

Vout = 3.135V

Pull-Down Current Min

OL(min)

Vout = 1.65 V

Pull-Down Current Max

OL(max)

Vout = 0.4 V

Rise/Fall Time Min
Between 0.8 V and 2.0 V

RF(min)

0.5

20 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V

RF(max)

1.3

30 pF Load

9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F)

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

OH(min)

-33

Vout = 1.0 V

Pull-Up Current Max

OH(max)

-33

Vout = 3.135 V

Pull-Down Current Min

OL(min)

Vout = 1.95 V

Pull-Down Current Max

OL(max)

Vout = 0.4 V

Rise/Fall Time Min
Between 0.8 V and 2.0 V

RF(min)

0.5

15 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V

RF(max)

2.0

30 pF Load

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 16 - Revision 0.20

10.0 POWER MANAGEMENT TIMING

10.1 CPU_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

CPU_STOP#

CPUCLK[0:3]

SDRAM

For synchronous Chipset, CPU_STOP# pin is a synchronous

active low

input pin used to stop the

CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU

locks on latency

is less than 2 CPU clocks and

locks off latency

is less then 2 CPU clocks.

10.2 PCI_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

PCI_STOP#

PCICLK[0:4]

For synchronous Chipset, PCI_STOP# pin is a synchronous

ctive low

input pin used to stop the

PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI

locks on latency

is less than 1 PCI clocks and

locks off

latency

is less then 1 PCI clocks.

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 17 - Revision 0.20

11.0 OPERATION OF DUAL FUCTION PINS

Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these
pins are latched into their appropriate internal registers. Once the correct information are properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.

Within 3ms

Input

Output

tri-state

Output

pull-low

2.5V

Output

tri-state

Output

pull-low

#2 REF0/CPU3.3#_2.5

#7 PCICLK_F/FS1

#8 PCICLK0/FS2

#25 24/MODE

#26 48/FS0

All other clocks

Vdd

Each of these pins are a large pull-up resistor ( 250 k

@3.3V ) inside. The default state will be logic

1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 k

resistor is recommended to be

connected to Vdd if logic 1 is expected. Otherwise, the 10 k

resistor is connected to ground if a logic

0 is desired. The 10 k

resistor should be place before the serious terminating resistor. Note that

these logic will only be latched at initial power on.

If optional EMI reducing capacitor are needed, they should be placed as close to the series
terminating resistor as possible and after the series terminating resistor. These capacitor has typical
values ranging from 4.7pF to 22pF.

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 19 - Revision 0.20

12.0 POWER SUPPLY SUGGESTION

1.A solid ground plane should be placed around the clock device. Ground connections should be tied

to this main ground plane as short as possible. No cuts should be made in the ground plane around
the device.

2.C21,C22,C31,C36 are decoupling capacitors ( 0.1

£g

F surface mount, low ESR, ceramic

capacitors.) They should be placed as possible as the Vdd pin and the ground via.

3.C1 and C2 are supply filtering capacitors for low frequency power supply noise. A 22

F (or

£g

F) tantalum capacitor is recommended.

4.Use of Ferrite Bead

(FB) are recommended to further reduce the power supply noise.

5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace

resistance is negligible.

Vdd2 Plane

FB2

Vdd2

(3.3Vor2.5V)

C21

C22

C36

C35

C34

C33

C32

C31

FB1

Vdd Plane

Vdd

(3.3V)

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 20 - Revision 0.20

13.0 ORDERING INFORMATION

Part Number

Package Type

Production Flow

W83194R-17/-17A

48 PIN SSOP

Commercial, 0

C to +70

14.0 HOW TO READ THE TOP MARKING

W83194R-17
28051234
814GBB

W83194R-17A
28051234
814GBB

1st line: Winbond logo and the type number: W83194R-17/-17A

2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B

814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR

BB: IC revision

All the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.

W83194R-17/-17A

PRELIMINARY

Publication Release Date: Sep. 1998

- 21 - Revision 0.20

15.0 PACKAGE DRAWING AND DIMENSIONS

Headquarters

No. 4, Creation Rd. III

Science-Based Industrial Park

Hsinchu, Taiwan

TEL: 886-35-770066

FAX: 886-35-789467

www: http://www.winbond.com.tw/

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

TLX: 16485 WINTPE

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II

123 Hoi Bun Rd., Kwun Tong

Kowloon, Hong Kong

TEL: 852-27516023-7

FAX: 852-27552064

Winbond Electronics
(North America) Corp.

2730 Orchard Parkway

San Jose, CA 95134 U.S.A.

TEL: 1-408-9436666

FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.

These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sale.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W83194R-17

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W83194R-17