W83194R-37/-58
100MHZ AGP CLOCK FOR VIA CHIPSET
Publication Release Date:Sep 1998
W83194R-37/58
Data Sheet Revision History
Pages Dates Version Version
On Web
Main Contents
1
n.a.
n.a.
All of the versions before 0.50 are for internal use.
2
n.a.
02/Apr
1.0
1.0
Change version and version on web site to 1.0
3
4
5
6
7
8
9
10
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 1 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro , AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU
clocks by software setting(additional register0 bit2). AGP and PCI clocks are externally selectable
with smooth transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and
makes SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, Pentium Pro, Pentium II, AMD and Cyrix CPUs with I
2
C.
4 CPU clocks
12 SDRAM clocks for 3 DIMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd = Vddq3 = Vddq2 = 3.3V, Vdq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)
SDRAM frequency synchronous to CPU or AGP clocks
Smooth frequency switch with selections from 60 to 100 MHz CPU(-37) and 66 to 150MHz(-58)
I
2
C 2-Wire serial interface and I
2
C read back
0.5% or 1.5%(-37) and 0.25%, 0.5%(-58) center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
- 2 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
3.0 BLOCK DIAGRAM
PLL2
XTAL
OSC
Spread
Spectrum
PLL1
LATCH
POR
STOP
2
Control
Logic
Config.
Reg.
STOP
STOP
PCI
clock
Divder
5
2
12
3
5
48MHz
24MHz
REF(0:1
)
AGP(0:1)
CPUCLK(0:3)
SDRAM(0:11)
PCICLK(0:4)
PCICLK_F
X1
X2
*FS(0:2) 3
*MODE
CPU_STOP#
PCI_STOP#
*SDATA
*SCLK
2
4
CPU3.3#_2.5
CPU_STOP#
PCI_STOP#
*SD_SEL#
4.0 PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vdd
* REF0/CPU3.3#_2.5
Vss
Xin
Xout
Vddq3
PCICLK_F/*FS1
PCICLK0/*FS2
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq3
AGP0
Vss
CPU_STOP#/SDRAM11
PCI_STOP#/SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
Vddq2
AGP1
REF1/*SD_SEL#
Vss
CPUCLK0
CPUCLK1
Vddq2b
CPUCLK2
CPUCLK3
Vss
SDRAM 0
SDRAM 1
SDRAM 2
Vddq3
SDRAM 3
Vss
SDRAM 4
SDRAM 5
SDRAM 6
SDRAM 7
Vss
Vddq3
48MHz/*FS0
24MHz/*MODE
- 3 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250k
pull-up
5.1 Crystal I/O
SYMBOL PIN
I/O
FUNCTION
Xin
4
IN
Crystal input with internal loading capacitors and
feedback resistors.
Xout
5
OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL PIN
I/O
FUNCTION
CPUCLK [ 0:3 ]
40,41,43,44
OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Vddq2b is the supply voltage for these outputs.
AGP[ 0:1]
15,47
OUT Accelerate Graphic Port clock outputs
SDRAM11/
CPU_STOP#
17
I/O
If MODE =1 (default), then this pin is a SDRAM clock
buffered output of the crystal. If MODE = 0 , then this
pin is CPU_STOP# input used in power
management mode for synchronously stopping the all
CPU clocks.
SDRAM10/
PCI_STOP#
18
I/O
If MODE = 1 (default), then this pin is a SDRAM clock
output. If MODE = 0 , then this pin is PCI_STOP #
and used in power management mode for
synchronously stopping the all PCI clocks.
SDRAM [ 0:9]
20,21,28,29,31
,32,34,
35,37,38
O
SDRAM clock outputs which have the same
frequency as CPU clocks.
PCICLK_F/ *FS1
7
I/O
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Free running PCI clock during normal operation.
- 4 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
5.2 CPU, SDRAM, PCI Clock Outputs, continued
SYMBOL PIN
I/O
FUNCTION
PCICLK 0 / *FS2
8
I/O
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
PCICLK [ 1:4 ]
10,11,12,13
OUT Low skew (< 250ps) PCI clock outputs.
5.3 I
2
C Control Interface
SYMBOL PIN
I/O
FUNCTION
SDATA
23
I/O
Serial data of I
2
C 2-wire control interface
SDCLK
24
IN
Serial clock of I
2
C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL PIN
I/O
FUNCTION
REF0 / CPU3.3#_2.5
2
I/O
Internal 250k
pull-up.
Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.
Latched high - Vddq2b = 2.5V
Latched low - Vddq2b = 3.3V
REF1 /*SD_SEL#
46
I/O
Internal 250k
pull-up.
Latched input at Power On selects either
CPU(SDSEL=1) or AGP(SD_SEL=0) frequencies for
SDRAM clock outputs.
24MHz / *MODE
25
I/O
Internal 250k
pull-up.
Latched input for MODE at initial power up. 24MHz
output for super I/O during normal operation.
48MHz / *FS0
26
I/O
Internal 250k
pull-up.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.
- 5 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
5.5 Power Pins
SYMBOL PIN
FUNCTION
Vdd
1
Power supply for Ref [0:1] crystal and core logic.
Vddq2
42
Power supply for AGP1 and REF1 output, either 2.5V or
3.3V.
Vddq2b
48
Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
Vddq3
6,14,19, 30, 36 Power supply for SDRAM, PCICLK and 48/24MHz
outputs.
Vss
3,9,16,22,27,
33,39,45
Circuit Ground.
6.0 FREQUENCY SELECTION BY HARDWARE
6.1 W83194R-37 Frequency Selection Table
FS2 FS1 FS0 CPU(MHz)
SDRAM (MHz)
PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL=1 SD_SEL=0
0 0 0
60
60
60
30
60
14.318
0 0 1 66.8
66.8 66.8 33.4
66.8
14.318
0 1 0 68.5
68.5 68.5 34.25
68.5
14.318
0 1 1
75
75
75
37.5
75
14.318
1 0 0
75
75
60
30
60
14.318
1 0 1 83.3
83.3 66.6 33.3
66.6
14.318
1 1 0
95
95 63.4 31.7
63.4
14.318
1 1 1
100
100 66.6 33.3
66.6
14.318
6.2 W83194R-58 Frequency Selection Table
FS2 FS1 FS0 CPU(MHz)
SDRAM (MHz)
PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL=1 SD_SEL=0
0 0 0
112
112 74.7 37.3
74.7
14.318
0 0 1 66.8
66.8 66.8 33.4
66.8
14.318
0 1 0
124
124 82.5 41.3
82.5
14.318
0 1 1
75
75
75
37.5
75
14.318
1 0 0 133.3 133.3 88.7 44.3
88.7
14.318
1 0 1 83.3
83.3 66.6 33.3
66.6
14.318
1 1 0 95.25 95.25 63.5 31.75
63.5
14.318
1 1 1 100.2 100.2 66.8 33.4
66.8
14.318
7.0 CPU 3.3#_2.5 BUFFER SELECTION
CPU 3.3#_2.5 ( Pin 2 ) Input Level
CPU Operate at
1
VDD = 2.5V
0
VDD = 3.3V
- 6 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
8.0 FUNCTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 18 and 17 are inputs (PCI_STOP#),
(CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be
enabled as both the 2-wire serial control interface and one of these pins indicate that it should be
enabled.
The W83194R-37/-58 may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
CPU & AGP
PCI
OTHER CLKs XTAL & VCOs
0 0 LOW
LOW
RUNNING
RUNNING
0 1 LOW
RUNNING
RUNNING
RUNNING
1 0
RUNNING
LOW
RUNNING
RUNNING
1 1
RUNNING
RUNNING
RUNNING
RUNNING
8.2 2-WIRE I
2
C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the
latches for verification. All proceeding bytes must be sent to change one of the control bytes. The
2-wire control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-37/-58 initializes with default register settings, and then itptional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle.
Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code
checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I
2
C registers after the string of data. The sequence order is as follows:
- 7 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
Bytes sequence order for I
2
C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Ack
Byte2, 3, 4...
until Stop
Byte 1
8.3 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits)
in these two bytes are considered "don't care", they must be sent and will be acknowledge. After
that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
8.3.1 Register 0: CPU Frequency Select Register
Bit @PowerUp Pin
Description
7 0 -
0 = 1.5% Spread Spectrum Modulation
1 = 0.5% Spread Spectrum Modulation(W83194R-37)
0 = 0.25% Spread Spectrum Modulation
1 = 0.5% Spread Spectrum Modulation(W83194R-58)
6
0
-
SSEL2 ( Frequency table selection by software via I
2
C)
5
0
-
SSEL1 ( Frequency table selection by software via I
2
C)
4
0
-
SSEL0 ( Frequency table selection by software via I
2
C)
3
0
-
0 = Selection by hardware
1 = Selection by software I
2
C - Bit 6:4
2
0
-
SSEL3 (Frequency table selection by software via I
2
C for
W83194R-58)
1
0
-
0 = Normal
1 = Spread Spectrum enabled
0 0 -
0
= Running
1 = Tristate all outputs
- 8 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
W83194R-37 Frequency table selection by software via I
2
C
SSEL2 SSEL1 SSEL0
CPU(MHz) SDRAM (MHz) PCI
(MHz)
AGP
(MHz)
REF (MHz)
SD_SEL=1 SD_SEL=0
0 0 0 60
60 60 30 60 14.318
0 0 1 66.8 66.8 66.8 33.4 66.8 14.318
0 1 0 68.5 68.5 68.5
34.25
68.5 14.318
0 1 1 75
75 75 37.5 75 14.318
1 0 0 75
75 60 30 60 14.318
1 0 1 83.3 83.3 66.6 33.3 66.6 14.318
1 1 0 95
95 63.4 31.7 63.4 14.318
1 1 1 100 100 66.6 33.3 66.6 14.318
W83194R-58 Frequency table selection by software via I
2
C
SSEL2 SSEL1 SSEL0
Register0
Bit2
CPU
(MHz)
SDRAM (MHz) PCI
(MHz)
AGP
(MHz)
REF
(MHz)
SSEL3
SD_SEL=1 SD_SEL=0
0 0 0 0 112 112 74.7 37.3
74.7
14.318
0 0 1 0 66.8 66.8 66.8 33.4
66.8
14.318
0 1 0 0 124 124 82.7 41.3
82.7
14.318
0 1 1 0 75 75
75 37.5
75
14.318
1 0 0 0 133.3
133.3 88.7 44..3
88.7
14.318
1 0 1 0 83.3 83.3 66.6 33.3
66.6
14.318
1 1 0 0 95.25
95.25 63.5
31.75
63.5
14.318
1 1 1 0 100.2
100.2 66.8 33.4
66.8
14.318
0 0 0 1 103 103 68.7 34.3
68.7
14.318
0 0 1 1 112 112 74.7 37.3
74.7
14.318
0 1 0 1 115 115 76.6 38.3
76.6
14.318
0 1 1 1 120 120 80 40 80
14.318
1 0 0 1 124 124 82 31 82
14.318
1 0 1 1 133.3
133.3 66.6 33.3
66.6
14.318
1 1 0 1 140 140 70 35 70
14.318
1 1 1 1 150 150 75 37.5
75
14.318
- 9 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
FUNCTION TABLE
Function Outputs
Description
CPU PCI SDRAM REF IOAPIC
Tri-State
Hi-Z Hi-Z Hi-Z
Hi-Z
Hi-Z
Normal
see table
see table
CPU
14.318
14.318
8.3.2 Register 1 : CPU , 48/24 MHz Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp
Pin
Description
7 1 -
Reserved
6 1 -
Reserved
5 1 -
Reserved
4 1 -
Reserved
3
1
40
CPUCLK3 (Active / Inactive)
2
1
41
CPUCLK2 (Active / Inactive)
1
1
43
CPUCLK1 (Active / Inactive)
0
1
44
CPUCLK0 (Active / Inactive)
8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp
Pin
Description
7 x -
Reserved
6
1
7
PCICLK_F (Active / Inactive)
5
1
15
AGP0 (Active / Inactive)
4
1
14
PCICLK4 (Active / Inactive)
3
1
12
PCICLK3 (Active / Inactive)
2
1
11
PCICLK2 (Active / Inactive)
1
1
10
PCICLk1 (Active / Inactive)
0
1
8
PCICLK0 (Active / Inactive)
8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp
Pin
Description
7
1
28
SDRAM7 (Active / Inactive)
6
1
29
SDRAM6 (Active / Inactive)
5
1
31
SDRAM5 (Active / Inactive)
4
1
32
SDRAM4 (Active / Inactive)
3
1
34
SDRAM3 (Active / Inactive)
2
1
35
SDRAM2 (Active / Inactive)
1
1
37
SDRAM1 (Active / Inactive)
- 10 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
0
1
38
SDRAM0 (Active / Inactive)
8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp
Pin
Description
7 x -
Reserved
6 x -
Reserved
5 x -
Reserved
4 x -
Reserved
3
1
17
SDRAM11 (Active / Inactive)
2
1
18
SDRAM10 (Active / Inactive)
1
1
20 SDRAM9 (Active / Inactive)
0
1
21 SDRAM8 (Active / Inactive)
8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)
Bit @PowerUp
Pin
Description
7 x -
Reserved
6 x -
Reserved
5 x -
Reserved
4
1
47
AGP1 (Active / Inactive)
3 x -
Reserved
2 x -
Reserved
1
1
46
REF1 (Active / Inactive)
0
1
2
REF0 (Active / Inactive)
8.3.7 Register 6: Reserved Register
Bit @PowerUp
Pin
Description
7 x -
Reserved
6 x -
Reserved
5 x -
Reserved
4 x -
Reserved
3 x -
Reserved
2 x -
Reserved
1 x -
Reserved
0 x -
Reserved
- 11 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
9.0 SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol Parameter
Rating
Vdd , V
IN
Voltage on any pin with respect to GND
- 0.5 V to + 7.0 V
T
STG
Storage Temperature
- 65
C to + 150C
T
B
Ambient Temperature
- 55
C to + 125C
T
A
Operating Temperature
0
C to + 70C
9.2 AC CHARACTERISTICS
Vddq2 = Vdd = Vddq3 = 3.3V
5 %, Vddq2b = 2.375V~2.9V , T
A
= 0
C to +70C
Parameter Symbol
Min
Typ
Max
Units
Test
Conditions
Output Duty Cycle
45
50
55
%
Measured at 1.5V
CPU/SDRAM to PCI Offset
t
OFF
1
4
ns
15 pF Load Measured at 1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
t
SKEW
250
ps
15 pF Load Measured at 1.5V
CPU/SDRAM
Cycle to Cycle Jitter
t
CCJ
250
ps
CPU/SDRAM
Absolute Jitter
t
JA
500 ps
Jitter Spectrum 20 dB
Bandwidth from Center
BW
J
500
KHz
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
t
TLH
t
THL
0.4
1.6
ns
15 pF Load on CPU and PCI
outputs
Overshoot/Undershoot
Beyond Power Rails
V
over
0.7 1.5 V 22
at source of 8 inch
PCB run to 15 pF load
Ring Back Exclusion
V
RBE
0.7
2.1
V
Ring Back must not enter this
range.
- 12 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
9.3 DC CHARACTERISTICS
Vddq2 = Vdd = Vddq3 = 3.3V
5 %, Vddq2b = 2.375V~2.9V , T
A
= 0
C to +70C
Parameter Symbol
Min
Typ
Max
Units Test
Conditions
Input Low Voltage
V
IL
0.8
V
dc
Input High Voltage
V
IH
2.0 V
dc
Input Low Current
I
IL
-66
A
Input High Current
I
IH
5
A
Output Low Voltage
I
OL
= 4 mA
V
OL
0.4
V
dc
All outputs
Output High Voltage
I
OH
= 4mA
V
OH
2.4 V
dc
All outputs using 3.3V power
Tri-State leakage Current
Ioz
10
A
Dynamic Supply Current
for Vdd + Vddq3
I
dd3
mA
CPU = 66.6 MHz
PCI = 33.3 Mhz with load
Dynamic Supply Current
for Vddq2 + Vddq2b
I
dd2
mA
Same as above
CPU Stop Current
for Vdd + Vddq3
I
CPUS3
mA
Same as above
CPU Stop Current
for Vddq2 + Vddq2b
I
CPUS2
mA
Same as above
PCI Stop Current
for Vdd + Vddq3
I
PD3
mA
- 13 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
9.4 BUFFER CHARACTERISTICS
9.4.1 TYPE 1 BUFFER FOR CPU (0:3)
Parameter Symbol
Min
Typ
Max
Units
Test
Conditions
Pull-Up Current Min
I
OH(min)
-27
mA
Vout = 1.0 V
Pull-Up Current Max
I
OH(max)
-27
mA
Vout = 2.0V
Pull-Down Current Min
I
OL(min)
mA
Vout = 1.2 V
Pull-Down Current Max
I
OL(max)
27
mA
Vout = 0.3 V
Rise/Fall Time Min
Between 0.4 V and 2.0 V
T
RF(min)
0.4
ns
10 pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
T
RF(max)
1.6
ns
20 pF Load
9.4.2 TYPE 2 BUFFER FOR IOAPIC
Parameter Symbol
Min
Typ
Max
Units Test
Conditions
Pull-Up Current Min
I
OH(min)
mA
Vout = 1.4 V
Pull-Up Current Max
I
OH(max)
-29
mA
Vout = 2.7V
Pull-Down Current Min
I
OL(min)
mA
Vout = 1.0 V
Pull-Down Current Max
I
OL(max)
28
mA
Vout = 0.2 V
Rise/Fall Time Min
Between 0.7 V and 1.7 V
T
RF(min)
0.4
ns
10 pF Load
Rise/Fall Time Max
Between 0.7 V and 1.7 V
T
RF(max)
1.8
ns
20 pF Load
- 14 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
9.4.3 TYPE 3 BUFFER FOR REF(0:1), 24MHZ, 48MHZ
Parameter Symbol
Min
Typ
Max
Units Test
Conditions
Pull-Up Current Min
I
OH(min)
-29
mA
Vout = 1.0 V
Pull-Up Current Max
I
OH(max)
-23
mA
Vout = 3.135V
Pull-Down Current Min
I
OL(min)
29
mA
Vout = 1.95 V
Pull-Down Current Max
I
OL(max)
mA
Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V
T
RF(min)
1.0
ns
10 pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V
T
RF(max)
4.0
ns
20 pF Load
9.4.4 TYPE 4 BUFFER FOR REF0 and SDRAM(0:11)
Parameter Symbol
Min
Typ
Max
Units Test
Conditions
Pull-Up Current Min
I
OH(min)
mA
Vout = 1.65V
Pull-Up Current Max
I
OH(max)
-46
mA
Vout = 3.135V
Pull-Down Current Min
I
OL(min)
mA
Vout = 1.65 V
Pull-Down Current Max
I
OL(max)
53
mA
Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V
T
RF(min)
0.5
ns
20 pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V
T
RF(max)
1.3
ns
30 pF Load
9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F)
Parameter Symbol
Min
Typ
Max
Units Test
Conditions
Pull-Up Current Min
I
OH(min)
-33
mA
Vout = 1.0 V
Pull-Up Current Max
I
OH(max)
-33
mA
Vout = 3.135 V
Pull-Down Current Min
I
OL(min)
30
mA
Vout = 1.95 V
Pull-Down Current Max
I
OL(max)
38
mA
Vout = 0.4 V
Rise/Fall Time Min
Between 0.8 V and 2.0 V
T
RF(min)
0.5
ns
15 pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V
T
RF(max)
2.0
ns
30 pF Load
- 15 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
CPUCLK[0:3]
SDRAM
1
2
1
2
For synchronous Chipset, CPU_STOP# pin is a synchronous " active low " input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU locks on latency" is less than 2 CPU clocks and
locks off latency" is less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
PCICLK[0:4]
1
2
1
2
For synchronous Chipset, PCI_STOP# pin is a synchronous ctive low" input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and
resume output with full pulse width. In this case, PCI locks on latency" is less than 1 PCI
clocks and locks off latency" is less then 1 PCI clocks.
- 16 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
11.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on
these pins are latched into their appropriate internal registers. Once the correct information are
properly latched, these pins will change into output pins and will be pulled low by default. At the end
of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms
Input
Output
Output
tri-state
Output
pull-low
2.5V
Output
tri-state
Output
pull-low
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
All other clocks
Vdd
Each of these pins are a large pull-up resistor ( 250 k
@3.3V ) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 k
resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, the 10 k
resistor is connected to ground if a logic
0 is desired. The 10 k
resistor should be place before the serious terminating resistor. Note that
these logic will only be latched at initial power on.
If optional EMI reducing capacitor are needed, they should be placed as close to the series
terminating resistor as possible and after the series terminating resistor. These capacitor has typical
values ranging from 4.7pF to 22pF.
- 17 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
Device
Pin
Vdd
Ground
Ground
10k
Series
Terminating
Resistor
Clock
Trace
EMI
Reducing
Cap
10k
Optional
Device
Pin
Vdd Pad
Ground Pad
Programming Header
Series
Terminating
Resistor
Clock
Trace
EMI
Reducing
Cap
Ground
10k
Optional
- 18 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
12.0 POWER SUPPLY SUGGESTION
1.A solid ground plane should be placed around the clock device. Ground connections should be
tied to this main ground plane as short as possible. No cuts should be made in the ground plane
around the device.
2.C21,C22,C31,C36 are decoupling capacitors ( 0.1F surface mount, low ESR, ceramic capacitors.)
They should be placed as possible as the Vdd pin and the ground via.
3.C1 and C2 are supply filtering capacitors for low frequency power supply noise. A 22F (or 10F)
tantalum capacitor is recommended.
4.Use of Ferrite Bead (FB) are recommended to further reduce the power supply noise.
5.The power supply race to the Vdd pins must be thick enough so that voltage drops across the trace
resistance is negligible.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vdd2 Plane
FB2
Vdd2
(3.3Vor2.5V)
C2
C21
C22
C36
C35
C34
C33
C32
C31
FB1
Vdd Plane
C1
Vdd
(3.3V)
- 19 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
13.0 ORDERING INFORMATION
Part Number
Package Type
Production Flow
W83194R-37/-58
48 PIN SSOP
Commercial, 0
C to +70C
14.0 HOW TO READ THE TOP MARKING
W83194R-37
28051234
814GBB
W83194R-58
28051234
814GBB
1st line: Winbond logo and the type number: W83194R-37/-58
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 814 G B B
814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR
BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
- 20 - Revision 1.0
W83194R-37/-58
Publication Release Date: Sep 1998
15.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
FAX: 886-35-789467
www: http://www.winbond.com.tw/
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District,
Taipei, 114, Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
Winbond Electronics
(North America) Corp.
2727 North First Street
San Jose, California 95134
TEL: 1-408-9436666
FAX: 1-408-9436668
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sale.
- 21 - Revision 1.0
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